System Power Supply for TV Series
FET Controller Type 3ch System Power Supply ICs
BD8627EFV
No.09034EAT05
●Description BD8627EFV has realized the high performance and reliability required as a power supply for thin-screen TV. With built-in FET 1ch current mode control, the DC/DC Converter series has the advantage of high-speed load response and wide phase margin. Due to the high-speed load response, it is most suitable for TV-purpose processors with increasingly high performance, and due to the wide phase margin it leaves a good margin for board pattern & constant setting and so facilitates its application design. As a high-reliability design, it has various built-in protection circuits (overcurrent protection, output voltage abnormal protection, thermal protection, and off-latch function at the time of abnormality etc.), therefore as an advantage it does not easily damage in every possible abnormal condition such as all-pin short circuit test etc. and hence most suitable for thin-screen TV which requires the high reliability. ●Features 1) High efficiency in all load area 2) 3.0A output current 3) Low RDS(ON) internal switches (PchMOS:85mΩ, NchMOS:65mΩ) 4) ±1% reference voltage accuracy 5) Programmable frequency : 250kHz-1MHz 6) Terminal RT OPEN/SHORT detecting function 7) Over current protection function 8) Output over voltage/low voltage protection function (over : FB > VREF +60mV , low : FB < VREF -60mV) 9) Timer off latch function in abnormal circumstances 10) Thermal shutdown function 11) Under voltage protection 12) Soft start/start delay circuit 13) Soft start time out function 14) HTSSOP-B20 package
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2009.05 - Rev.A
BD8627EFV
●ABSOLUTE MAXIMUM RATING (Ta=25℃) Parameter Input supply voltage Input terminal voltage Output terminal voltage Output current Power dissipation Operating temperature Storage temperature Symbol VIN VINP*1 VOUT*2 IOUT Pd Topr Tstg Limits 7 VIN VIN 4 3.2*3 -10 ~ 85 -55 ~ 150 Unit V V V A W ℃ ℃
Technical Note
*1 VINP Application terminal: EN, SS/DELAY, TEST, FB *2 VOUT Application terminal: SW, PDET, FC, RT, REG *3 (70mm x 70mm, thickness 1.6mm, and four layer glass epoxy substrates) When mounting substrate and the package back exposure part are connected with solder. Operating at higher than Ta=25℃, 25.6mW shall be reduced per 1
Parameter Input supply voltage Output current
Operation condition Symbol MIN VIN 4.5 IOUT -
TYP -
MAX 6.0 3.0
Unit V A
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2009.05 - Rev.A
BD8627EFV
● Electrical characteristic (Unless otherwise noted Ta=25℃, VIN=5.6V)
Technical Note
Specification value UNIT Condition MIN TYP MAX VIN supply current (operating) IQ_active 1.3 2.0 mA VFB = 0.83V, VFC = 1V VEN = 0V μA VIN supply current (standby) IQ_stby 350 700 Reference voltage (VREF) VREF 0.792 0.8 0.808 V Output rise detection voltage VOVP 30 60 90 mV Monitoring FB terminal Output decrease detection voltage VLVP -90 -60 -30 mV Monitoring FB terminal Terminal PDET output current IPDET 1 mA VPDET< 0.5V ROSC = 220kΩ Oscillation frequency fOSC 500 550 600 kHz Pch FET ON resistance RPFET 85 120 mΩ ISW = 1A Nch FET ON resistance RNFET 65 100 mΩ ISW = -1A UVLO voltage VUVLO 3.8 4.0 4.2 V μA SW leak current ILSW 0 1 VEN= 0V, VIN = 6V EN terminal H threshold voltage VENH 2.0 V EN terminal L threshold voltage VENL 0.5 V μA SS/DELAY terminal source current ISSSO 2 4 6 VFB :FB terminal voltage, VEN :EN terminal voltage, VFC :FC terminal voltage, VPDET: PDET terminal voltage Current capability should not exceed Pd. Parameter Symbol Permissible loss
4 Permissible loss : PD [W] 3 2 1 0
(70mm×70mm, thickness 1.6mm, and four layer glass epoxy substrates) When mounting substrate and the package back exposure part are connected with solder.
0
25
50
75
100
125
150
Surrounding temperature : Ta [℃]
Fig. 1 heat decrease curve
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2009.05 - Rev.A
BD8627EFV
● Block Diagram
18 SS/DELAY
Technical Note
17 TEST
15 REG
14 VIN
13 VIN
20 RT
19 FC
16 EN
OSC
enable
REG
REG
en
VIN
Detect Abnormal Voltage and Start error
REG
Err AMP
Shut Down
0.8V
REG
PWM CONTROL
Predrive
12 VIN SW 9
PGND 6
SGND 1
Fig.2 Block diagram ●Pin description No. Symbol 1 SGND 2 FB 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PDET SW SW PGND PGND PGND SW SW VIN VIN VIN VIN REG EN TEST Description Signal GND terminal Feed back terminal Off latch signal output Output terminal Power GND terminal Output terminal Explanation Small signal system GND Output voltage detection Reset output Switching output GND for power MOSFET Power Mos output
Power supply input terminal
Power supply input. The decoupling is done to PGND Internal regulator ON/OFF control for device operation GND short in application set The soft start time is adjusted with the connected capacitor Error amplifier phase compensation point The switching frequency is set by the connected resistance
Internal regulator Enable input TEST terminal Soft start adjustment capacity connection SS/DELAY terminal FC Error amplifier output Frequency adjustment resistance connection RT terminal
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PGND 7
PGND 8
PDET 3
SW 5
SW 10
SW 4
FB 2
11 VIN
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BD8627EFV
●Pin equivalence circuit diagram No. Symbol 1 SGND
Technical Note
Explanation
Terminal equivalent circuit diagram
GND (connected 0V)
VIN
2
FB
Output voltage detection terminal
2
SGND
3
PDET
Off latch signal output terminal
4,5,9,10
SW
Output terminal
6,7,8
PGND
Power GND (Same voltage as SGND)
11,12,13,14
VIN
Power supply input terminal
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2009.05 - Rev.A
BD8627EFV
No. Symbol Explanation
Technical Note
Terminal equivalent circuit diagram
VIN VIN
15
REG
Internal regulator output terminal
15
SGND
VIN
VIN
16
EN
Enable terminal
15
SGND
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2009.05 - Rev.A
BD8627EFV
No. Symbol Explanation
Technical Note
Terminal equivalent circuit diagram
VIN
18
SS
Soft start time adjustment terminal
18
SGND
19
FC
Error amplifier compensation terminal
VIN
20
RT
Oscillator frequency adjustment terminal
20
SGND
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2009.05 - Rev.A
BD8627EFV
● Operation description Enable control The device can be controlled ON/OFF by EN terminal (16 pin) voltage. An internal circuit starts when VEN reaches 0.65V.
VEN
Technical Note
EN terminal voltage
VENTH
0
VSSCLM
VSS
SS terminal voltage
VSSTH
0
VO
Output setting voltage
0
tSS
VPDET
PDET
0
Fig.3 ON/OFF transition wave form in EN controlling Soft start time set function As for BD8627EFV, output can do soft start without overshoot by charging soft start capacity (CSS) connected between SS and SGND terminal. Also, soft start time (tss) can be set by setting soft start capacity (CSS) arbitrarily.
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2009.05 - Rev.A
BD8627EFV
Technical Note
OSC oscillation frequency setting function The output oscillation frequency can be set by connecting resistance between terminal RT (20 pins) and SGND (range = 250kHz - 1MHz) The relation between RT terminal resistance and the oscillation frequency follows Fig.4.
10000
1000
Frequency [kHz]
100
10 10 100 1000 10000
RT terminal resistance [kΩ]
Fig. 4 RT resistance-oscillation frequency
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2009.05 - Rev.A
BD8627EFV
Technical Note
● Protection function Protection circuit is effective for destruction prevention due to accident so that avoid using under continuous protection operation. Low voltage protection function (LVP) The voltage of the terminal FB (2 pins) is compared with internal reference voltage VREF. If FB terminal voltage falls below VLVP(= VREF -60mV) and the state continues for 500us, output changes to low voltage and the state is fixed. In that case , PDET (3pin) output changes to L. Table 1 output low voltage protection function Low voltage protection Low voltage protection EN terminal SS terminal FB terminal function operation 1.4V(typ) Effective >VIHEN >VLVP OFF 1.4V(typ) Effective