TECHNICAL NOTE
IC Card Interface
Technical Note
BD8905F/FV, BD8906F/FV
●Summary
3V, 5V Smart card interfaces IC.
Install between smart card and controller. This IC operates as bi-directional buffer, and supply 3V or 5V to smart card.
Card contact pin will be protected by I/O cell, ESD capability is more than HBM: ±6000V.
●Feature
1) Half duplex bi-directional buffer 3 system.
2) All card contact pin is protected from short.
3) Card power supply (VREG) 3V or 5V.
4) Card supply has over current protection.
5) Include thermal shutdown circuit.
6) Include power supply voltage detector.
7) Automatically rising and Falling sequencer function
Rising sequence:Depend on controller signal(CMDVCCB↓)
Falling sequence:Depend on controller signal(CMDVCCB↑)and fault detection (ejection of card,
card supply short, IC heat detect, VDD or VDDP drop).
8) Enhanced ESD protection on Card contact pin (≧±6000V).
9) 2MHz – 26MHz crystal oscillator.
10) Clock generation for card is 1, 2, 4 or 8 divisions available.
11) RST output is controlled by RSTIN input signal (positive conversion output).
12) Card status output by OFFB.
●Application
Smart card interface
B-CAS card interface
2007.Oct.
ROHM Co., Ltd.
●Absolute Maximum Ratings(Ta=25℃)
Parameter
Symbol
Limit
Unit
VDD
VDDP
VIN
VOUT
-0.3~6.5
-0.3~6.5
V
V
VDD Supply voltage
VDDP Supply voltage
I/O pin voltage
-0.3~+6.5
V
Condition
Pin:XTAL1, XTAL2, VSEL, RSTIN, AUX1C, AUX2C,
IOC, CLKDIV1, CLKDIV2, CMDVCCB, OFFB,
PORADJ, S2
Pin:PRES, PRESB, CLK, RST, IO, AUX1, AUX2
Pin:VCH, S1
Card contact pin voltage
VREG
-0.3~+6.5
V
Charge pump voltage
Vn
-0.3~+14.0
V
Junction temperature
Tjmax
+150
℃
Operating temperature
Topr
-25~+85
℃
Storage temperature
Tstg
-55~+150
℃
Power
BD890XF
750
mW
Ta=-25~+85℃
Ptot
dissipation
1060
BD890XFV
・This product is not designed for protection against radioactive rays.
・Absolute Maximum Ratings does not warrant operating.
・BD890XF: BD8905F/BD8906F (Package: SOP28)
・This product is not designed for protection against radioactive rays.
・Absolute Maximum Ratings does not warrant operating.
・BD890XF: BD8905F/BD8906F (Package: SOP28)
・BD890XFV: BD8905FV/BD8906FV (Package: SSOP-B28)
●Operating Condition (Ta=25℃)
Parameter
VDD voltage
Symbol
BD8905F/FV
VDD
BD8906F/FV
VDDP voltage
VDDP
MIN
TYP
MAX
Unit
2.7
-
5.5
V
3.0
-
5.5
V
4.5
3.0
3.0
5.0
5.0
5.5
4.5
5.5
V
V
V
*See below about.
package power dissipation
Condition
VREG=5V; Ivreg≦60mA
VREG=5V; Ivreg≦20mA
VREG=3V; Ivreg≦60mA
●Package Dissipation
Package thermal capacity is plotted on figure below, only when you use Rohm standard board.
Don’t use at over thermal capacity condition. Please check your thermal capacity out.
BD890XF:
Pd=750mW, however de-rating in done at 6mW/℃ for operating above Ta≧25℃.
BD890XFV: Pd=1060mW, however de-rating in done at 8.5mW/℃ for operating above Ta≧25℃.
Rohm standard board:
3
size: 70×70×1.6(mm )
material: FR4 glass epoxy board (Copper foil area is below 3%)
1.2
0.8
1.1
0.7
1.0
0.9
0.6
0.8
0.5
Pd [W]
Pd [W]
0.7
0.4
0.6
0.5
0.3
0.4
0.3
0.2
0.2
0.1
0.1
0.0
0.0
-25
0
25
50
75
100
125
-40
150
-15
10
35
60
85
110
Ta [℃]
Ta [℃]
Fig.1 BD890XF
Fig.2 BD890XFV
2/11
135
●Block diagram
BD8905F/FV, BD8906F/FV
2.7V - 5.5V
3.0V - 5.5V
VDD
VDDP
REF
CHGPUMP
S1
VREF
VREF
VDD
CHARGE PUMP
doubler
doubler
DETREF
R1
PGND
VDD
PORADJ
S2
VDET
VREF
R2
(Not for the BD8906F/FV)
VCH
VDD
2.7MHz
OSC
VDD
LVS
EN1
VDD
VREF
TSD
ALARM
CLKUP
VSEL
POWER_ON
ALARM
TSD
EN2
LVS
VREG
OFFB
CARD REG
RSTIN
EN5
LVS
CMDVCCB
CGND
VCC
ALARM
RST BUF
RST
LVS
SEQUENCER
3V/5V
CLK BUF
CLK
EN
CLKDIV1
CLK
DIV
CLKDIV2
EN4
CLK
VDD
PRES
XT OSC
2MHz - 26MHz
AUX1C
VDD
MAX 1MHz
VREG
IO TRANS
VDD
MAX 1MHz
IO TRANS
VDD
MAX 1MHz
AUX2
VREG
LVS
IOC
AUX1
VREG
LVS
AUX2C
VDD
PRESB
LVS
XTAL2
VDD
EN3
XTAL1
IO TRANS
GND
Fig.3
3/11
IO
●Pin Direction
Pin no. Pin name
I/O
Signal level
Condition
1
CLKDIV1
I
VDD
Clock frequency setting input1
2
CLKDIV2
I
VDD
Clock frequency setting input1
3
VSEL
I
VDD
Card supply voltage setting input:“H”: VREG=5V, “L”: VREG=3V
4
PGND
S
GND
GND for charge pump
5
S2
I/O
-
6
VDDP
S
VDDP
7
S1
I/O
-
8
VCH
I/O
-
9
PRESB
I
VDD
10
PRES
I
VDD
11
12
13
14
15
16
IO
AUX2
AUX1
CGND
CLK
RST
I/O
I/O
I/O
S
O
O
VREG
VREG
VREG
GND
VREG
VREG
17
VREG
O
VREG
18
PORADJ/NC
I
-
19
20
21
22
CMDVCCB
RSTIN
VDD
GND
I
I
S
S
VDD
VDD
VDD
GND
23
OFFB
O
VDD
24
25
26
27
28
XTAL1
XTAL2
IOC
AUX1C
AUX2C
I
O
I/O
I/O
I/O
VDD
VDD
VDD
VDD
VDD
Capacitors connection for charge pump
(S1 to S2):C = 100nF (ESR < 100mΩ)
Charge pump power supply
Capacitors connection for charge pump
(S1 to S2):C = 100nF (ESR < 100mΩ)
Charge pump output: decupling capacitor;
C = 100nF (ESR < 100mΩ)connect during VCH and PGND.
Card insertion detect pin (Active ”L”)
When PRES or PRESB are active, decision on card inserted, and it will
enter input stabilization time of typ8ms.
2MΩ pull-up to VDD.
Card insertion detect pin (Active ”H”)
When PRES or PRESB are active, decision on card inserted, and it will
enter input stabilization time of typ. 8ms.
2MΩ pull-down to GND
I/O data line to smart card 11kΩ pull-up to VREG
I/O data line to smart card 11kΩ pull-up to VREG
I/O data line to smart card 11kΩ pull-up to VREG
GND
Card clock output
Card reset output
Connected capacitance (ESR < 100mΩ) of 100nF~220nF between Card
power supply and CGND.
Power-on-reset voltage set pin; using external bridge
(Not for the BD8906F/FV)
Activation sequence will start after detection of falling edge from controller.
Card reset signal input
VDD pin
GND
Alarm output pin (Active “L”)
NMOS output, 20kΩ pull-up to VDD
Cristal connected or external Clock input
Cristal connected (treat as open if clock supplied externally.)
I/O data line to controller 11kΩ pull-up to VDD
I/O data line to controller 11kΩ pull-up to VDD
I/O data line to controller 11kΩ pull-up to VDD
4/11
●Package
Package product name SOP28
(MAX size
18.85)
BD890XF
Lot No
1PIN MARK
(UNIT : mm)
Fig.4-1 BD890XF Package Outline
Package product name SSOP-B28
(MAX size
10.35)
BD890XFV
1PIN MARK
Lot No
(UNIT : mm)
Fig.4-2 BD890XFV Package Outline
5/11
●Function
1) Power supply
Power supply terminal is VDD and VDDP. VDD make a same voltage to signal from the system controller side.
VDDP and PGND are the power supplies, GND of charge pump circuit, and it is a POWER source of supply to the card.
Depends on setup pin VSEL 3V (VSEL: L) or 5V (VSEL: H) is supplied to the card through a VREG terminal.
2) VDD supply voltage detector (Not for the BD8906F/FV)
VDD power supply voltage detector setup (VDETR and VDETF: Fig.3) is done by connecting a resistance bridge
(R1 and R2: Fig.1) to the PORADJ.
After VDD rises more than VDETR and takes about 16ms (internal reset) more, power on reset (Alarm) is released.
And IC becomes sleep state until CMDVCCB becomes H to L.
◆The calculation of the power supply voltage detector resistance bridge R1 and R2.
Alarm release voltage (VDETR) and a low voltage detection voltage (VDETF) are calculated with the following equation.
You must set up VDETF more than 2.3V.
VDD rising PORADJ voltage: VDDTHR
VDD falling PORADJ voltage: VDDTHF
⎛ R1 ⎞
⎛ R1 ⎞
VDETR = ⎜
VDETF = ⎜
+ 1⎟ × VDDTHF
+ 1⎟ × VDDTHR
R2
⎠
⎝
⎝ R2
⎠
VDD
ALARM
(internal signal)
tW=16ms
tW=16ms
Power on
Power supply drop
Power off
Fig.5 VDD power supply detection
3) Operation sequence
3-1) Standby mode
An IC becomes standing by condition until a CMDVCCB signal becomes H->L after a VDD voltage rose more than
VDTER and the power on resetting (Alarm) was canceled.
VDD power supply voltage detector (VDET) a thermal shutdown circuit (TSD), a voltage reference circuit (VREF), a crystal
oscillation circuit (XT OSC) and internal oscillator circuit (OSC) operate in this mode.
Pull-up is done by the resistance of 11KΩ with IOC, AUX1C and AUX2C to VDD. And all card contact terminals are Lo
levels.
3-2) Card insertion
The insertion condition of the card is detected by the PRES or the PRESB. It is judged that a card is being inserted when
either a PRES terminal or a PRESB terminal is active.
Table 1
PRES
PRESB
“High”
Active
“Lo”
Active
When a card is inserted under the sleep condition, either terminal of the card insertion distinction terminal PRES (H: It is
active.) and PRESB (L: It is active.) becomes active. OFFB becomes H about 8mS in that (debounce time) rest.
OFFB becomes H after it was reset inside and debounce time passed when a card is being inserted before a VDD power
supply stands up and internal resetting is released. PRESS is being pull-down to GND by 2MΩ, and PRESSB is being
pull-up to VDD by 2MΩ.
6/11
3-3) Rising sequence
When a CMDVCCB signal from the controller becomes H->L under the OFFB = H, a rising sequence is started, and each
function block starts in the following order.
RSTIN is enabled after I/O TRANS ON and passes 300ns.
After I/O TRANS turns it on, TIN input becomes effective in about 300ns.
CLK signal is outputted when RSTIN becomes Lo before RST output is canceled after RSTIN becomes effective. In case
of RSTIN is High when RST is released, CLK output correspond to RST release. (See Fig.4、Fig.5、Fig.6)
CHARGE PUMP ON
(VCH voltage output)
↓
CARDREG ON
(VREG output)
↓
I/O TRANS ON
(All I/O Bus: Pull-up)
↓__________________________________________________
↓
↓RSTIN to RST release during High
↓(RSTIN ≠ Always High)
↓(RSTIN = Always High)
↓
↓
CLK BUF ON
(CLK output)
CLK,RST BUF ON (CLK output, RST release)
↓
RST BUF ON
(RST release)
【Rising sequence by the difference in the RSTIN input timing】
CMDVCCB
CMDVCCB
VCH
VCH
VREFG
VREFG
ART
I/O
ART
I/O
CLK
CLK
Min:200ns
RSTIN
RSTIN
RST
RST
IOUC
IOUC
t0 t1
t2
t3 t4
t5= tact
t0 t1
Fig.6-1 Rising sequence1
t2
t3
t4
t5= tact
Fig.6-2 Rising sequence2
CMDVCCB
VCH
VREFG
ART
I/O
t1: VCH rise startup time
= typ. 21.4μs
t2: VREG rise startup time
= typ. 57μs
t3: I/O ON time
= typ. 116.2μs
= Min. 200μs
t4: CLK output release time
(t4-t3)
t5: RST release time
(Activation time)
CLK
RSTIN
RST
IOUC
t0 t1
t2
t3 t4
t5= tact
Fig.6-3 Rising sequence 3
7/11
= typ. 187.4μs
3-4) Falling sequence
When CMDVCCB input becomes L->H or Alarm signal (mentioning later) is detected, falling sequence start in the
following order and a sequence shifts to the standby mode.
RST BUF OFF
↓
CLK BUF OFF
↓
I/O TRANS OFF
↓
↓
CARDREG OFF
↓
CHARGE PUMP OFF
(RST: Lo)
(CLK: Lo)
(Controller side I/O Bus: Pull-up)
(Card side I/O Bus: Lo)
(VREG: Lo)
CMDVCCB
RST
CLK
t11: CLK OFF time
= typ. 11.9μs
t12: I/O OFF time
= typ. 23.7μs
t13: VREG shutdown time
= typ. 35.6μs
t14: VCH shutdown time
= typ. 118.5μs
tde: finishing sequence complete time
= Max. 100μs
I/O
VREG
VCH
t11
t12
t13
tde
t10
t14
Fig.7 Falling sequence
4) CHARGE PUMP
Charge circuit is the power supply of the CARD REG output. It starts operation when CMDVCCB input becomes H->L.
Then, it operates as double boost circuit or voltage follower by VDDP voltage.
VCH output becomes the power supply of the CARDREG circuit.
Arrange two flying capacitance ( S1-S2 space and the VCH-PGND space) in the neighborhood of the IC as much as
possible so that ESR may become less than 100mΩ so that charge pump circuit may wash away big charge electric
current. Arrange capacitor in VDDP and the space of PGND as well in the neighborhood of the IC as much as possible
again so that ESR may become less than 100mΩ.
5) CARD REG
CARD REG does the power supply from the VREG terminal to the IC card.
VREG output voltage is changed to 3V or 5V by the setup of the VSEL.
Table2 VSEL pin setting
VSEL
VREG output voltage
VDDP voltage
0
3V
3.0V ~ 5.5V
1
5V
3.0V ~ 4.5V
1
5V
4.5V ~ 5.5V
MAX current
65mA
20mA
60mA
This regulator built-in an over current limit circuit. Internal Alarm signal is taken out at the load current of about 140m A
and more. And it goes into shutdown sequence. When VREG output voltage falls below 0.6V for 3V mode and 1.0V for 5V
mode, detect fault, cutoff output current, output internal alarm and being shutdown sequence.
To suppress output voltage fluctuation, install capacitance (100nF, 200nF, 330nF) as near as possible between VREG and
CGND. And ESR is less than 100mΩ.
CARD REG output is power supply of CLK and RST output. Therefore, CLK and RST output level become VREG output
levels.
8/11
6) I/O data conversion
Three data lines IOC - IO, AUX1C - AUX1 and AUX2C - AUX2 transmit and receive data bi-directionally and independently.
Until it becomes I/O TRANS ON by rising sequence, controller side pin IOC, AUX1C and AUX2C are done pull-up to High
(VDD level) by 11KΩ, and IOC, AUX1C and AUX2C of card contact pin are Lo.
When I/O TRANS it becomes On, IC becomes idol state, IOC, AUX1C and AUX2C pin are VDD electric potential (High),
and IO, AUX1 and AUX2 pin are VREG electric potential (High). I/O pins are pull-up by 11KΩ to VDD level (IOC, AUX1C
and AUX2C) or VREG level (IO, AUX1, AUX2).
The one that data transited in H->L first as to either becomes muster, and output on the opposition side becomes slave
with the controller side terminal and the card contact terminal. Then, data are transmitted on slave side from muster side.
It takes a drive to High the data by active Pull-up (less than 100ns) to do a data transition at high speed at the moment
when it got over threshold when a signal transits in H from L. Pull-up is done by the resistance of 11KΩ with a terminal
after the active Pull-up end. Transmitter and receiver make a signal to 1MHz possible by this function. And over current
limit of 15mA is given to IO, AUX1 and AUX2 of the card contact terminal.
7) Card clock supply
Clock supply to the card has an input signal from the XTAL1 terminal by 1 by the setup of CLKDIV1 and the CLKDIV2
terminal, and it is outputted more than a CLK terminal. Divider changeover time is within 8 clock of the XTAL1 signal.
(See; Table1)
XTAL1 terminal input signal inputs a pulse signal from the signal by crystal frequency (2MHz to 26MHz) between XTAL1
and the XTAL2 terminal or the outside. The one within 48%-52% at duty with a XTAL1 terminal must do transition time in
the signal period within 5% to set duty in the CLK terminal at 45%-55 %.
Use it by 1/2, 1/4 and a 1/ 8-minute lap setup though it depends to draw a circuit board to assure duty 45%-55 %.
Table3 Clock frequency selection list
(fXTAL:XTAL1 in frequency)
CLKDIV1
CLKDIV2
0
0
0
1
1
1
1
0
fclk
f XTAL
8
f XTAL
4
f XTAL
2
f XTAL
1
8) RSTIN input, RST output
CMDVCCB signal: RSTIN input becomes effective in about 300ns after I/O TRANS turns it on after H->L is inputted and
rising sequence starts. After a CMDVCCB signal becomes H->L again, it is canceled in about 200μsec, and it follows
RSTIN input, and RST output outputs a signal.
9) Fault detection
When the following fault condition is detected, internal alarm signal is taken out, and it stands up, and lowered, and a
sequence is shifted to the action, the standing by condition. Still it is standing by condition when a card hasn't been
inserted from the beginning.
・When a VREG terminal lowered more than 1V (when VSEL=H) or 0.6V (when VSEL=L) or over current (TYP: 150mA)
flowed to the terminal.
・When VDD electric potential is lower than a detect voltage. (When power supply voltage detector is detected.)
・When it was detected in the high temperature by the thermal shutdown circuit.
・When a VCH terminal voltage unusually fell down.
・When a card was removed during the movement or when a card hasn't been inserted from the beginning. (When
PRES=L and PRESB=H)
9/11
10) OFFB output
OFFB output is the output terminal which shows that it is in the condition that IC can work. Pull-up is being raised by the
resistance of 20KΩ in VDD.
OFFB is High when it is in the condition that it can work. When fault condition is detected, OFFB output outputs off
condition (Lo).
Internal alarm signal is canceled, and OFFB output becomes High when a card is being inserted and fault condition is
canceled and CMDVCCB becomes High.
PRES
OFFB
tdebounce
tdebounce
VREG
stopping poperation by the card removal
stopping operation by pin short
Fig.8 OFFB, CMDVCCB, PRES, VREG Operation
10/11
tdebounce = typ 8ms
●Caution in use
1) Put two capacitor for charge pump on in the space between S1 in the neighborhood of the IC and S2 and in VCH and the
space of PGND as much as possible so that ESR may become less than 100mΩ.
2) Put capacitor of the VREG terminal on VREG in the neighborhood of the IC and the space of CGND as much as possible
so that ESR may become less than 100mΩ.
3) Put a capacitor beyond 10μF+0.1μF between GND's in the neighborhood of the IC in VDD and VDDP as much as
possible because of the power supply noise decrease so that ESR may become less than 100mΩ. Using the capacitor of
the big capacity as much as possible is recommended.
●Application
100nF
+5.0V
100nF
100nF
CLKDIV1
CLKDIV2
VSEL
PGND
S2
VDDP
S1
VCH
PRESB
PRES
IO
AUX2
AUX1
CGND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
BD890XF
10μF
+3.3V
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AUX2C
AUX1C
IOC
15pF
XTAL2
XTAL1
15pF
OFFB
GND
VDD 100nF
RSTIN
+3.3V
CMDVCCB
PORADJ (NC with BD8906F/FV)
VREG
VDD
RST
CLK
58.1KΩ
100nF
41.9KΩ
CARD
CONNECTION
0.22uF
VDD
C5
C1
C6
C2
C7
C3
C8
C4
100KΩ
K1
K2
Fig.9
11/11
CONTROLLER