BD8918FV-E2

IC Card Interface ICs IC Card Interface ICs with Built-in Low Noise LDO Regulator BD8918F,BD8918FV,BD8919F,BD8919FV No.09056EDT01 ●Overview This is an interface IC for a 5V smart card. It works as a bidirectional signal buffer between a smart card and a controller. Also, it supplies 5V power to a smart card. With an electrostatic breakdown voltage of more than HBM; ±6000V, it protects the card contact pins. ●Features 1) 1 half duplex bidirectional buffers 2) Protection against short-circuit for all the card contact pins 3) 5V power source for the card (VCC) 4) Over-current protection for card power source 5) Built-in thermal shutdown circuit 6) Built-in supply voltage detector 7) Automatic activation/deactivation sequence function for card contact pin Activation sequence: driven by a signal from controller (CMDVCCB) Deactivation sequence: driven by a signal from controller (CMDVCCB) and fault detection (card removal, short circuit of card power, IC overheat detection, VDD or VDDP drop) 8) Card contact pin ESD voltage ≧ ±6000V 9) Recommend frequency of crystal oscillator: 8MHz (BD8918F/FV), 16MHz (BD8919F/FV) 10) Programmable for card clock division of output signal: 1/1 and 1/2(BD8918F/FV), 1/2 and 1/4(BD8919F/FV). 11) RST output control by RSTIN input signal (positive output) 12) One multiplexed card status output by OFFB signal ●Applications Interface for CLASS A smart cards Interface for B-CAS cards ●Line up matrix Part No BD8918F BD8918FV BD8919F BD8919FV Card clock Ratio of dividing frequency 1/1f, 1/2f 1/2f, 1/4f Package SOP16 SSOP-B16 SOP16 SSOP-B16 www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 1/15 2010.4 - Rev.D BD8918F,BD8918FV,BD8919F,BD8919FV ●Absolute maximum ratings (Ta=25°C) Parameter Symbol VDD Input Voltage VDDP Input Voltage I/O Pin Voltage Card Contact Pin Voltage Junction Temperature Storage Temperature Power Dissipation VDD VDDP VMIN VMOUT VCD Tjmax Tstg Ptot Technical Note Ratings -0.3 ~ 6.5 -0.3 ~ 6.5 -0.3 ~ +6.5 -0.3 ~ +6.5 +150 -55 ~ +150 0.375 *2 0.500 *1 Unit V V V V °C °C W Notes Pin: XTAL1, XTAL2, CLKSEL, RSTIN, IO_U CMDVCCB, OFFB Pin: PRES, CLK, RST, IO_C T = -20 ~ +85°C (Refer to the following package power dissipation) *1 BD8918F/BD8919F, *2 BD8918FV/BD8919FV • This product is not designed to be radiation tolerant. • Absolute maximum ratings are not meant for guarantee of operation. ●Operating Conditions (Ta=25°C) Parameter VDD Input Voltage VDDP Input Voltage Operating Temperature ●Package Power Dissipation The power dissipation of a simple package in case of a boadless will be as follows. Use of this device beyond the following the power dissipation may cause permanent damage. BD8918F/BD8919F BD8918FV/BD8919FV Pd=375mW; however, reduce 3mW per 1°C when used at Ta ≥ 25°C. Pd=500mW; however, reduce 4mW per 1°C when used at Ta ≥ 25°C. Symb ol VDD VDDP Topr Ratings MIN 2.7 4.75 -40 TYP MAX 5.5 5.5 +85 V V °C VCC ≥ 4.55V Unit Notes Package power 0.4 Package power 0.6 0.5 0.3 0.4 Pd (W) Pd (W) 0.2 0.3 0.2 0.1 0.1 0.0 0 25 50 75 Temp (℃) 100 125 150 0.0 0 25 50 75 Temp (℃) 100 125 150 Fig. 1.1 BD8918F/BD8919F Power Dissipation Fig. 1.2 BD8918FV/BD8919FV Power Dissipation www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 2/15 2010.4 - Rev.D BD8918F,BD8918FV,BD8919F,BD8919FV ●Block Diagram Technical Note 2.7V-5.5V VDD 0.1uF 4.75V-5.5V VDDP 10µF VIREF VDET LVS POWER _ON VDD VREF TSD TSD ALARM LVS 20k ALARM VCCEN VCC 5V 1µF OFFB RSTIN LDO CGND 50k VDD 50k SEQUENCER VCC ALARM LS V RSTEN RST BUF RST CMDVCCB LVS DIVEN CLKEN CLKSEL 50k CLK DIV CLK BUF VDD CLK DIVCLK VDD 50k 22pF XTAL1 F 220Ω XT OSC MAX 1MHz I OEN PRES VCC 22pF VDD XTAL 2 LVS 11k 11k IO_U IO TRANS IO_C GND Fig. 2 BD8918F/FV BD8919F/FV F=8MHz F=16MHz www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 3/15 2010.4 - Rev.D BD8918F,BD8918FV,BD8919F,BD8919FV ●Pin Description Pin No. Pin Name 1 2 3 XTAL1 XTAL2 VDD I/O I O S Signal Level VDD VDD VDD Pin Function Crystal connection or input for external clock Technical Note Crystal connection (leave open pin when external clock source is used) 3.3 V power source pin for host interface. Connect 0.1µF capacitor between the VDD and GND pins. Input for clock frequency BD8918F/FV H: 1/1 division; L: 1/2 division. division setting. Pulled down to GND BD8919F/FV H: 1/2 division; L: 1/4 division. with a 50k resistor. Card reset signal input. Pulled down to GND with a 50k resistor. Host data I/O line; Pulled up to VDD with an 11k resistor GND I/O data line on the card side. Pulled up to VCC with an 11kresistor. Card reset output Card clock output Card supply voltage. Connect 1µF capacitor between VCC and the CGND pins. 5V power source pin for card power feed. Connect 10µF capacitor between the VDDP and CGND pins. Card presence contact input (“H” active). Pulled up to VDD with a 50k resistor. Connected to a switch where GND level is inputted when no card is inserted and OPEN is inputted when a card is inserted. When “H” level is detected, a card is assumed to be inserted and waits for the CMDVCCB input for the confirmation, after the debounce time of typ. 8ms. Alarm output pin (“L” active). NMOS open drain output. Pulled up to VDD with a 20k resistor. Activation sequence command input; The activation sequence starts by signal input (HL) from the host GND 4 CLKSEL I VDD 5 6 7 8 9 10 11 12 RSTIN IO_U CGND IO_C RST CLK VCC VDDP I I/O S I/O O O O S VDD VDD GND VCC VCC VCC VCC VDDP 13 PRES I VDD 14 15 16 OFFB CMDVCCB GND O I S VDD VDD GND *Capacitors to be connected to VDD, VDDP and VCC should be placed immediately next to the pins (ESR