BD9040FV_09

Large Current External FET Controller Type Switching Regulators Step-down,High-efficiency Switching Regulators (Controller type) BD9040FV,BD9045FV No.09028EAT03 ●Over View BD9040FV(output type of 1ch) and BD9045FV(output type of 2ch) are switching controllers that can be used within the wide range of the input.Highly effective can be achieved by the synchronous rectification method and it is possible to contribute to the eco-design of all electronic equipment (energy-saving). ●Feature(BD9040FV，BD 9045FV) 1) Wide input voltage range：4.5V～18V 2) Reference voltage 0.9V±1% 3) The overcurrent of timer latch type, excess voltage, short, and RTO/S protection are built-in 4) The switching frequency is changeable.(200kHz～750kHz) 5) A ceramic capacitor can be used for the output. ●Applications For thin television, DVD･HDD recorder , STB, amusement and others. ●Absolute maximum rating (Ta=25℃) Parameter Power-supply voltage EN input voltage SW voltage Voltage between BOOT-SW Permissible loss 1 Permissible loss 2 Range of operating temperature Storage temperature range Junction temperature ** *** Ta=25℃ or more is reduced with 6.5mW/℃. Ta=25℃ or more is reduced with 7.5mW/℃. Symbol Vcc VEN VSW VBOOT Pd1 Pd2 Topr Tstg Tjmax Rating 20 20 Vcc 6 0.81** (BD9040FV) 0.94*** (BD9045FV) -40～+85 -55～+150 150 Unit V V V V W W ℃ ℃ ℃ ●Operation condition (Ta=-40℃～+85℃) Parameter Power supply voltage*** Timing resistance Frequency of oscillator *** ○ Symbol Vcc RT Fosc Min 4.5 39 200 Limit Typ 12 － － Max 18 130 750 Unit V kΩ kHz Please be short-circuited to use VREG5 and VCC when the Vcc is 6V or less. The radiation design is not done. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 1/18 2009.05 - Rev.A BD9040FV, BD9045FV ●Electric characteristics (Unless otherwise specified Ta=25℃ VCC=12V EN=5V) (BD9040FV) Parameter VCC Current of bias Standby current ［VREG5］ Standard voltage output voltage Technical Note Symbol ICC ISTB Limit Min Typ 3 430 Max 6 860 Unit mA µA VEN=0V Condition VREG5 VREG5_L 5 - 5.5 20 6 50 V mV IVREG5=0 to 6mA Load stability level ［VREG3 part] Standard voltage Load stability level VREG3 VREG3_L 2.85 - 3.0 10 3.15 20 V mV IVREG3=0 to 1mA ［prevention part for mis-operation of low input］ VREG5 Threshold voltage VREG3 Threshold voltage ［Oscillator］ Oscillation frequency ［Error amplifier］ VO input bias current Source current Sink current Return standard voltage Output short detection voltage Hysteresis voltage ［Soft start part］ Charge current Discharge current 1 Discharge current 2 Maximum voltage Standby current ISS IDIS IDIS2 Vss_MAX Vss_STB -14 0.6 2.35 1.75 -10 1.7 3.3 1.95 -6 5 4.62 2.15 0.3 V V µA mA Vss=1V Vss=1V Vss=1V, VEN_SS=0V Ivo+ Isource Isink VOB Vosh ΔVosh -12 0.75 0.891 0.37 22 -6.5 1.5 0.900 0.45 45 1 -2 5 0.909 0.53 90 µA mA mA V V mV VFB=1.1V VFB=0.7V FB-COMP Short VFB:Sweep down VFB:Sweep up FOSC 240 300 360 kHz RT=91 kΩ VREG5_UVLO VREG3_UVLO 3.4 2.4 3.8 2.5 4.2 2.6 V V VREG5:Sweep down VREG3:Sweep down ［overcurrent protection Division］ CL inflow current ［Overvoltage protection Division］ Detection voltage ［Timer latch circuit Division］ Source current Threshold voltage OFF Sink current ［Each ch control part］ EN pull-up resistor REN REN_SS 150 150 300 300 450 450 kΩ kΩ ITM Vth_TM IOFFS -14 0.9 0.6 -10 1 1.7 -6 1.1 5 µA V mA VTM=0.5V VTM=1V Vovp 1.06 1.1 1.14 V Iswin 9 10 11 µA VCL=Vcc-0.2V EN_SS pull-up resistor www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 2/18 2009.05 - Rev.A BD9040FV, BD9045FV ●Reference data (Unless otherwise specified Ta=25℃) 100 90 80 EFFICIENCY[%] EFFICIENCY[%] 70 60 50 40 30 20 10 0 0 1 2 OUTPUT CURRENT：Io[A] 3 VIN =12V 1.8V 1.2V 2.6V 3.3V 5.0V 100 90 80 70 60 50 40 30 20 10 0 6 9 12 15 INPUT VOLTAGE ： VIN [V] 18 Io=2A INPUT CURRENT ： IIN[mA] 3.3V 5.0V 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 2 Technical Note BD9045FV BD9040FV 4 6 8 10 12 14 16 18 20 OUTPUT VOLTAGE ： Vo[V] Fig.1 Efficiency 1 Fig.2 Efficiency 2 Fig.3 Circuit current 0.9 950 REFERENCE VOLTAGE ： VOB[V] OSILATING FREQUENCY ： FOSC[kHz] 330 320 310 300 290 280 270 -40 -15 10 35 60 85 AMBIENT TEMPERATURE ： Ta[℃] STANDBY CURRENT ： ISTB[uA] 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 2 4 6 8 10 12 14 16 18 20 INPUT VOLTAGE ： VIN [V] BD9040FV BD9045FV 940 930 920 910 900 890 880 870 860 850 -40 -15 10 35 60 85 AMBIENT TEMPERATURE ： Ta[℃] Fig.4 Standby current Fig.5 Reference voltage temperature characteristic 4.0 Fig.6 Frequency temperature characteristic 3.5 OUTPUT　VOLTAGE ： Vo[V] 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 1 2 3 4 5 INPUT VOLTAGE：VEN[V] 85℃ 25℃ -40℃ 7 OUTPUT CURRENT ： Io[A] OUTPUT VOLTAGE ： Vo[V] 6 5 4 3 2 1 0 -20 BD9045FV RCL=12kΩ Use SP8K2 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 Latch OFF BD9040FV RCL=10kΩ Use SP8K2 RCL=10kΩ 0 20 40 60 80 0 1 2 3 4 AMBIENT TEMPERATURE ： Ta[℃] OUTPUT CURRENT ： Io[A] Fig.7 Overcurrent protection temperature characteristic 3.5 OUTPUT　VOLTAGE ： Vo[V] 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 1 2 3 4 5 INPUT VOLTAGE：VEN_SS[V] 85℃ 25℃ -40℃ Fig.8 Load regulation Fig9. EN Threshold voltage 20mV/div VOUT VOUT 20mV/div IOUT 1A/div 1A/div IOUT Fig.10 EN_SS Threshold voltage Fig.11 Load response 1 Fig.12 Load response 2 www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 3/18 2009.05 - Rev.A BD9040FV, BD9045FV ●Pin configuration (BD9040FV) Technical Note EN_SS RT TM SS COMP FB EN N.C. VREG3 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 CL BOOT OUTH SW DGND OUTL VREG5 N.C. N.C. VCC ●Pin function table (BD9040FV) Terminal number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 terminal name EN_SS RT TM SS COMP FB EN N.C VREG3 GND VCC N.C N.C VREG5 OUTL DGND SW OUTH BOOT CL Function SS discharge Delay ON/OFF terminal Oscillation frequency setting terminal Output OCP and OVP timer latch setting terminal Soft start time setting terminal Error amplifier output Error amplifier input Output ON/OFF terminal Unconnected terminal REG output for standard power supply GND Input power supply terminal Unconnected terminal Unconnected terminal REG output for FET drive drive terminal at low side of FET gate Source terminal at low side of FET High side FET source terminal Terminal of drive at high side in FET gate OUTH driver power supply terminal Overcurrent detection setting terminal www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 4/18 2009.05 - Rev.A BD9040FV, BD9045FV ●Block diagram Technical Note (BD9040FV) VCC 5.5V Reg B.G RT 3.0V Reg O/S Check VREG5 VREG3 3.8V UVLO TSD TSD OSC UVLO 2.5V TM OCP CL Set Reset DRV DRV BOOT OUTH SW VREG5 TSD UVLO Slope Set Q Reset OUTL OVP ErrAmp PWM UVLO COMP DGND FB SS 0.9V Q Set EN_SS COMP Sequence DET Reset 0.45V EN GND www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 5/18 2009.05 - Rev.A BD9040FV, BD9045FV ●Pin configuration Technical Note (BD9045FV) GND TM1 SS1 COMP1 FB1 EN1 VCC EN2 VREG3 RT FB2 COMP2 SS2 TM2 15 14 16 13 17 12 18 11 19 10 20 9 21 8 22 7 23 6 24 5 25 4 26 3 27 2 28 1 14 OUTL1 13 DGND1 12 SW1 11 OUTH1 10 BOOT1 9 8 7 6 5 4 3 2 1 CL1 VREG5 N.C. CL2 BOOT2 OUTH2 SW2 DGND2 OUTL2 ●Pin function table (BD9045FV) Terminal number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 terminal name OUTL2 DGND2 SW2 OUTH2 BOOT2 CL2 N.C. VREG5 CL1 BOOT1 OUTH1 SW1 DGND1 OUTL1 GND TM1 SS1 COMP1 FB1 EN1 VCC EN2 VREG3 RT FB2 COMP2 SS2 TM2 Functions Terminal 2 of drive at low side FET gate Low side FET source terminal2 High side FET source terminal2 Terminal 2of drive at high side of FET gate OUTH2 driver power supply terminal Overcurrent detection setting terminal Unconnected terminal REG output for FET drive Overcurrent detection setting terminal OUTH1 driver power supply terminal Terminal 1of drive at high side of FET gate High side FET source terminal 1 Low side FET source terminal 1 Terminal 1of drive at low side of FET gate GND terminal Output 1 OCP and OVP timer latch setting terminal Soft start time setting terminal 1 Error amplifier output 1 Error amplifier input1 Outpt1ON/OFF terminal Input power supply terminal Output2ON/OFFterminal REG output for standard power supply Oscillation frequency setting terminal Error amplifier input 2 Error amplifier output 2 Soft start time setting terminal 2 Output 2 OCP and OVP timer latch setting terminal 1 2 www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 6/18 2009.05 - Rev.A BD9040FV, BD9045FV ●Block diagram Technical Note (BD9045FV) VCC 5V Reg UVLO B.G RT O/S Check OSC UVLO 3V Reg VREG5 VREG3 3.8V TSD TSD TM2 OCP TM1 OCP CL2 BOOT2 OUTH2 SW2 VREG5 DRV DRV Set Reset Set Reset DRV DRV CL1 BOOT1 OUTH1 SW1 VREG5 TSD UVLO TSD UVLO OUTL2 DGND2 FB2 SS2 COMP OVP － ＋ ＋ 0.9V ErrAmp Q Reset Set PWM COMP Slope Slope PWM COMP Q Set Reset OUTL1 OVP ErrAmp UVLO 0.9V DGND1 FB1 SS1 COMP1 Set Q Reset Q Set Sequence DET Sequence DET Reset 0.45V 0.45V EN2 EN1 GND www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 7/18 2009.05 - Rev.A BD9040FV, BD9045FV Technical Note ●Block functional descriptions ・Error amplifier(ErrAmp) It is a circuit to compare the 0.9V reference voltage and the output voltage’s feedback voltage. Switching Duty is determined by the COMP voltage that is the result of the comparison. In addition, due to the SS terminal voltage on start-up, the Soft Start begins operating, and so the COMP voltage is limited by the SS voltage. ・Oscillator(OSC) It is a block, the oscillating frequency of which is decided by RT and can be set up to 200kHz～750kHz. ・SLOPE It is a block in which triangular wave is created from the clock generated by the OSC. And the generated triangular wave is transmitted to the PWM comparator. ・PWM Comparator(PWM COMP) The error amplifier’s output COMP voltage and the SLOPE block’s triangular wave are compared, and the switching Duty is determined. The switching duty is limited by the maximum Duty ratio internally decided and can not become 100%. ・Reference voltage(5V Reg, 3V Reg) It is a block to generate 5.5V and 3V internal reference voltage. ・Overcurrent protection circuit(OCP) At the time of OUTH=H, if SW voltage becomes not more than CL voltage, the overcurrent protection circuit operates. When the overcurrent protection operates, the Duty is limited, and so the output voltage is lowered. Moreover, when an overcurrent is detected by the overcurrent protection circuit, the charging of the external capacitor on TM terminal is started. When the voltage on TM terminal exceeds 1V, the output becomes OFF state and then is latched. Once EN is made to be L, the latch is released. ・Overvoltage protection circuit(OVP) When FB voltage becomes more than 1.1 V, the overvoltage protection operates. When the overvoltage protection operates, the charging of the external capacitor on TM terminal is started. When the voltage on TM terminal exceeds 1V, the output becomes OFF state and then is latched. Once EN is made to be L, the latch is released. ・Output short circuit protection circuit If FB voltage becomes not more than 0.4V, the output short circuit protection circuit operates. When the output short circuit protection operates, the charging of the external capacitor on TM terminal is started. When the voltage on TM terminal exceeds 1V, the output becomes OFF state and then is latched. Once EN is made to be L, the latch is released. ・O/S Check When RT terminals become open or short circuit states, RT OPEN and SHORT circuit protections operate respectively. When RT terminals’ open or short circuit state is detected, the charging of the external capacitor on TM terminal is started. When the voltage on TM terminal exceeds 1V, the output becomes OFF state and then is latched. Once EN is made to be L, the latch is released. ・Under Voltage Lockout (UVLO) / Thermal Shutdown(TSD) When VREG5 becomes no more than around 3.8V or VREG3 no more than around 2.5, the output of the under voltage lockout is turned off. Then, When VREG5 becomes more than around 4.2V or VREG3 more than around 2.6, the output of the under voltage lockout is reset. Moreover, when the temperature of chip becomes more than around 150℃, the output of the thermal shutdown (TSD) is turned off, and when it is returned to a certain temperature, the output is reset. When UVLO and TSD operate, the capacitors of TM and SS are discharged. ・Function of EN EN is pulled down in regard to GND and pulled up in regard to VCC, and normally EN=H. At the time of EN=L, the capacitors of OFF, TM and SS of output are discharged, and become the standby state. (As for BD9045, due to EN1 and EN2, the capacitors of OFF, TM and SS of each ch output are discharged. In addition it becomes the standby state when both EN1 and EN2 are made to be L). ・Function of EN_SS(BD9040 alone) EN_SS is pulled down in regard to GND and pulled up in regard to VCC, and normally EN_SS=H. At the time of EN_SS=L, the capacitors of OFF, TM and SS of output are discharged.At the time of EN_SS=L, the capacitor of SS is constant-current discharged, so it can be made delayed during output’s OFF. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 8/18 2009.05 - Rev.A BD9040FV, BD9045FV ●Application circuit example BD9040FV VIN 12V Technical Note 30uF EN_SS 82kΩ 0.1uF 4.7nF 0.1uF 47pF RT TM SS COMP FB EN N.C. 0.1uF VREG3 GND CL BOOT OUTH SW DGND OUTL VREG5 N.C. N.C. VCC 0.1uF 0.1uF 10kΩ 10uH Vo 3.3V 27kΩ 2.2nF 150Ω 10kΩ 3kΩ 30uF 1uF ※ There are many factors (The PCB board layout, output current, etc.) that can affect the DCDC characteristics, please Verify and confirm using practical applications. BD9045FV VIN 12V 30uF GND 0.1uF 10nF 3.3kΩ OUTL1 DGND1 SW1 OUTH1 0.1uF BOOT1 CL1 VREG5 N.C. CL2 BOOT2 OUTH2 0.1uF SW2 DGND2 OUTL2 15kΩ 30uF 3.3nF 100Ω 39kΩ 12kΩ 12kΩ 1uF 0.1uF 0.1uF 10kΩ 30uF 2.2nF 120Ω 10kΩ 10uH Vo 1.8V TM1 SS1 COMP1 0.1uF 22pF FB1 EN1 VCC EN2 VREG3 0.1uF 82kΩ 10nF 2kΩ RT FB2 100pF COMP2 SS2 TM2 0.1uF 10uH Vo 1.2V 0.1uF ※There are many factors (The PCB board layout, output current, etc.) that can affect the DCDC characteristics, please Verify and confirm using practical applications. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 9/18 2009.05 - Rev.A BD9040FV, BD9045FV ●Application components selection (1) Setting of output L constant value Technical Note The coil value significantly influences the output ripple current. Thus, as seen in equation (1), the bigger the coil, and the higher the switching frequency, the lower the drop in ripple current. ΔIL ΔIL = VCC IL VOUT L Co (VCC-VOUT)×VOUT L×VCC×f [A]・・・ 1） （ The optimal output ripple current setting is 30% of maximum current. ΔIL = 0.3×IOUTmax.[A]・・・(2) [H]・・・ 3） （ ΔIL×VCC×f (ΔIL：output ripple current, f：switching frequency) L= (VCC-VOUT)×VOUT O utput ripple current ※ Outputting a current in excess of the coil current rating will cause magnetic saturation of the coil and decrease efficiency. Please establish sufficient margin to ensure that peak current does not exceed the coil current rating. Use low resistance (DCR, ACR) coils to minimize coil loss and increase efficiency. ※ (2) Setting of output constant Co Select the output capacitor with the highest value for ripple voltage (VPP) tolerance and maximum drop voltage (at rapid load change). The following equation is used to determine the output ripple voltage. Step down ΔVPP = ΔIL × RESR + ΔIL Co × Vo Vcc × 1 f [V]･･･(4) provided that f： switching frequency Be sure to keep the output Co setting within the allowable ripple voltage range. ※Please allow sufficient output voltage margin in establishing the capacitor rating. Note that low-ESR capacitors enable lower output ripple voltage. Also, to meet the requirement for setting the output startup time parameter within the soft start time range, please factor in the conditions described in the capacitance equation (5) for output capacitors, below. Tss：soft start time Tss × (ILimit – IOUT) IOUT：load current ・・・ （5） Co ≦ VOUT：output voltage VOUT ILimit：over current detection value reference Note: less than optimal capacitance values may cause problems at startup. (3) Input capacitor(Cin)selection The input capacitor serves to lower the output impedance of the power source connected to the input pin (VCC). Increased power supply output impedance can cause input voltage (VCC) instability, and may negatively impact oscillation and ripple rejection characteristics. Therefore, be certain to establish an input capacitor in close proximity to the VCC and GND pins. Select a low-ESR capacitor with the required ripple current capacity and the capability to withstand temperature changes without wide tolerance fluctuations. The ripple current IRMS is determined using equation (6). VIN Cin VOUT L Co IRMS = IOUT × VOUT（VCC - VOUT） VCC [A]・・・(6) Input capacitor Also, be certain to ascertain the operating temperature, load range and MOSFET conditions for the application in which the capacitor will be used, since capacitor performance is heavily dependent on the application’s input power characteristics, substrate wiring and MOSFET gate drain capacity. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 10/18 2009.05 - Rev.A BD9040FV, BD9045FV Technical Note (4) Feedback resistor design Please refer to the following equation in determining the proper feedback resistance. The recommended setting is in a range between 1kΩ and 330kΩ. Resistance less than 1kΩ risks decreased power efficiency, while setting the resistance value higher than 330kΩ will result in an internal error amp input bias current of 0.4uA increasing the offset voltage. Vo Internal reference 0.9V R1 +R2 R2 R1 FB Vo = × 0.9 [V] ・・・(7) R2 (5) Setting switching frequency The triangular wave switching frequency can be set by connecting a resistor to the RT pin. The RT sets the frequency by adjusting the charge/discharge current in relation to the internal capacitor. Refer to the figure below in determining proper RT resistance. Settings outside this range may render the switching function inoperable, and proper operation of the controller overall cannot be guaranteed when unsupported resistance values are used. 750 700 650 600 550 500 450 400 350 300 250 200 0 20 40 60 80 R T [ kΩ] f [kHz] 100 120 140 160 (6) Setting the soft start delay The soft start function is necessary to prevent an inrush of coil current and output voltage overshoot at startup. The figure below shows the relation between soft start delay time and capacitance, which can be calculated using equation (8) at right. [sec]・・・ 8） （ Iss（10µA typ） Vcc If the capacitance value is reduced (to no more than 0.01 uF or so), the overshoot in output may be caused. Please use high accuracy components (such as X5R) when implementing sequential startups involving other power sources. Be sure to test the actual devices and applications to be used, since the soft start time varies, depending on input voltage, output voltage, load, coil, output capacitance and phase compensation constant etc. Iss（10µA typ） × TSL = 0.8 × Css Vo [sec] TSH = 0.7 × Css (7) Setting the EN_SS (output delay function)(in the case of BD9040FV) If EN_SS is made to be L, the output voltage’s OFF time can be made delayed. The calculating formula for delay time is shown in the following equation. Vo Vcc Css Idis(3.3uA,Typ) TDIS= Vss_MAX(1.95VTyp)-(0.8+0.7× VCC EN_SS VO )× [sec]・・・(9) TSL TSH Tdis www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 11/18 2009.05 - Rev.A BD9040FV, BD9045FV Technical Note (8) Overcurrent protection Current limit value (ILimit) is determined by the resistance RCL established between VCC and CL. (refer to the following diagram)The current limit is self-feedback type, when overcurrent is detected, the output Duty is reduced, and the current is limited. When load returns to normal state, the output voltage returns to its former state. overcurrent protection 6 5 4 Io [A] Io [A] 3 2 1 0 12 13 14 15 16 R CL [k Ω] 17 18 6 5 4 3 2 1 0 12 overcurrent protection In case of SP8K2 In case of SP8K2 13 14 15 16 R CL [k Ω] 17 18 BD9040FV measurement value of our company’s substrate BD9045FV measurement value of our company’s substrate ※There are many factors (the layout and service condition) that can affect the characteristics, please verify and confirm using practical applications.Overcurrent protection detection value is dependent on the ON resistance of external FET and so varies with temperature. (Refer to Fig.7 on page 3) Please determine it in such a way that a good margin is left while setting it. Moreover, in case of different layout of substrate or large gate capacitance of external FET, sufficient voltage between gate and source of external FET can not be provided, the ON resistance becomes high, and so the overcurrent protection value may be greatly changed. Please use a FET, the gate capacitance of which is no more than1500pF, as external FET. (the recommended: SP8K2， SP8K1)However, There are many factors (the layout and service condition) that can affect the characteristics, please verify and confirm using practical applications. Compare the VCL that is set by RCL and the ΔVsw that is generated by ON resistance of loxFET. VCC RCL CL 10u A OUTH Overcurrent protection SW OUTL VCL ΔVsw Io (9) Setting of OFF latch timer time ・OFF latch timer is charged if one of the following conditions is met. ・Current limit is operating. ・Overvoltage protection(FB≧1.1V)is operating. ・Output short circuit protection(FB≦0.45V)is operating. ・Resistor connected on RT terminal becomes open. ・RT terminal is shorted with GND. ・Resistor connected on CL terminal becomes open. If the charging is started and continued until the fully-charged, the output is OFF latched. The time from start-up of charging till output OFF is determined by the following formula. CTM TTM = [sec] ・・・(10) ITM(10uA typ) This OFF latch is released once EN is made to be「L」or if VCC is once lowered and then rises again. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 12/18 2009.05 - Rev.A BD9040FV, BD9045FV Technical Note (10) Method for determining phase compensation Conditions for application stability Feedback stability conditions are as follows: ・When gain is 1 (0dB) and phase shift is 150° or less (i.e., phase margin is at least 30°): a dual-output high-frequency step-down switching regulator is required Additionally, in DC/DC applications, sampling is based on the switching frequency; therefore, overall GBW may be set at no more than 1/10 the switching frequency. In summary, target characteristics for application stability are: ・Phase shift of 150° or less (i.e., phase margin of 30° or more) with gain of 1 (0dB) ・GBW (i.e., gain 0dB frequency) no more than 1/10 the switching frequency. Stability conditions mandate a relatively higher switching frequency, in order to limit GBW enough to increase response. The key to achieving successful stabilization using phase compensation is to cancel the secondary phase margin/delay (-180°) generated by LC resonance, by employing a dual phase lead. In short, adding two phase leads stabilizes the application.GBW (the frequency at gain 1) is determined by the phase compensation capacitor connected to the error amp. Thus, a larger capacitor will serve to lower GBW if desired. ① General use integrator (low-pass filter) ② Integrator open loop characteristics A (a) -20dB/decade GBW(b) - 90° Phase margin Feedback R FB A COMP Gain [dB] 180 C Phase 0 [deg] -90 -90 0 -180 -180 0 90 Point(a) fa = 1 1.25[Hz]・ ・1 ） ・（1 2πRCA 1 2πRC [Hz] ・ ・12） ・（ Point(b) fa = GBW -180° The error amp is provided with phase compensation similar to that depicted in figures ① and ② above and thus serves as the system’s low-pass filter.In DC/DC converter applications, R is established parallel to the feedback resistance. When electrolytic or other high-ESR output capacitors are used Phase compensation is relatively simple for applications employing high-ESR output capacitors (on the order of several Ω). In DC/DC converter applications, where LC resonance circuits are always incorporated, the phase margin at these locations is -180°. However, wherever ESR is present, a 90° phase lead is generated, limiting the net phase margin to -90° in the presence of ESR. Since the desired phase margin is in a range less than 150°, this is a highly advantageous approach in terms of the phase margin. However, it also has the drawback of increasing output voltage ripple components. ③ LC resonance circuit ④ ESR connected Vcc 1 fr = 2π√LC Vo [Hz]・ ・13） ・ （ fr = fESR = 1 [Hz]: 2π√LC resonance point ・ 14） ・ （ 1 [Hz]: Zero （15） 2πRESRC L Resonance point phase margin -180º C -90°:Pole Since ESR changes the phase characteristics, only one phase lead need be provided for high-ESR applications. Please choose one of the following methods to add the phase lead. ⑤ Add C to feedback resistance ⑥ Add R3 to aggregator Vo C1 R1 FB R2 A COMP R2 C2 R1 FB A COMP Vo R3 C2 Phase lead fz = 1 2πC1R1 [Hz]・・・(16) Phase lead fz = 1 [Hz]・・・(17) 2πC2R3 www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 13/18 2009.05 - Rev.A BD9040FV, BD9045FV Technical Note Set the phase lead frequency close to the LC resonance frequency in order to cancel the LC resonance. ・When using ceramic, OS-CON, or other low-ESR capacitors for the output capacitor: Where low-ESR (on the order of tens of mΩ) output capacitors are employed, a two phase-lead insertion scheme is required, but this is different from the approach described in figure ③～⑥, since in this case the LC resonance gives rise to a 180° phase margin/delay. Here, a phase compensation method such as that shown in figure ⑦ below can be implemented. ⑦Phase compensation provided by secondary (dual) phase lead Vo R1 C1 R3 FB A R2 COMP C2 Phase lead fz1 = 1 2πR1C1 1 2πR3C2 1 2π√LC [Hz]・・・(18) Phase lead fz2 = [Hz] ・・・(19) LC resonance frequency fr = [Hz] ・・・(20) Once the phase-lead frequency is determined, it should be set close to the LC resonance frequency. This technique simplifies the phase topology of the DCDC Converter. Therefore,it might need a certain amount of trial-and-error process. There are many factors(The PCB board layout, Output Current, etc.)that can affect the DCDC characteristics. Please verify and confirm using practical applications. (9)MOS FET selection VCC VDS VGSM1 FET uses Nch MOS ・VDS＞Vcc ・VGSM1＞BOOT-SW interval voltage ・VGSM2＞VREG5 ・allowable current＞output current + ripple current ※Should be at least the over current protection value ※Select a low ON-resistance MOSFET for highest efficiency ※Attention If the input capacitance of FET is extremely large or it is used with Duty no more than 10%, it is possible that output FETs on both upper side and under side are simultaneously turned on and so the efficiency deteriorates. The input capacitance of output FET is recommended to be no more than 1000pF. But these characteristics vary with substrates’ layouts or varieties of parts etc, so please confirm them thoroughly with actual devices when it is put into mass production. IL Vo VGSM2 VDS (10)Schottky barrier diode selection VCC ・Reverse voltage VR＞Vcc ・Allowable current ＞ output current + ripple current ※Should be at least the over current protection value ※Select a low forward voltage, fast recovery diode for highest efficiency Vo VR www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 14/18 2009.05 - Rev.A BD9040FV, BD9045FV ●Timing chart Technical Note EN=L VCC SS EN=L EN=L UVLO EN1 Vreg3 Vreg5 3.8V 1V 1.1V 1V 4.2V TM FB OVP 検出 OVP detection SCP detection SCP 検出 on latch condition ラッチ状態で output OFF 出力 OFF 0.45V onッチ状態で ラ latch condition 出力 OFF output OFF www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 15/18 2009.05 - Rev.A BD9040FV, BD9045FV ● Input & output equivalent circuits Technical Note 2(24)PIN [RT] VREG3 ７PIN [EN] (20,22)PIN [EN1, EN2] VCC VCC VCC VCC VREG3 EN RT 300kΩ 20kΩ EN 377kΩ 20kΩ 367kΩ 20kΩ 315kΩ 20kΩ 184kΩ 150Ω 200kΩ 20PIN (9,6)PIN [CL] [CL1, CL2] VCC 2kΩ 15PIN [OUTL] (14, 1)PIN [OUTL1, OUTL2] 5PIN [COMP] (18,26)PIN [COMP1, COMP2] VCC VREG5 VREG5 VREG3 CL 3kΩ 20kΩ VREG3 OUTL COMP 5kΩ 6PIN [FB] (19, 25)IN [FB1, FB2] 1PIN [EN_SS] 3PIN [TM] (6，28)PIN [TM1, TM2] VREG3 VREG3 VCC VREG3 1kΩ EN_SS FB 1kΩ VCC VCC VREG3 300kΩ 2kΩ 200kΩ 100kΩ 20kΩ TM 55Ω 4PIN (7, 27)PIN [SS] [SS1, SS2] 9PIN (23)PIN [VREG3] [VREG3] 9,17,18PIN (10, 5)PIN (12, 3)PIN (11, 4)PIN VCC BOOT [BOOT, SW, OUTH] [BOOT1, BOOT2] [SW1, SW2] [OUTH1, OUTH2] VCC VREG3 VCC VCC 2k Ω SS 50 Ω 100kΩ VREG3 100kΩ 150kΩ OUTH SW 300kΩ ※ The inside of ( ) is of BD9045FV www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 16/18 2009.05 - Rev.A BD9040FV, BD9045FV Technical Note ●Notes for use 1. Absolute maximum ratings Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may result in IC deterioration or damage. Assumptions should not be made regarding the state of the IC (short mode or open mode) when such damage is suffered. A physical safety measure such as a fuse should be implemented when use of the IC in a special mode where the absolute maximum ratings may be exceeded is anticipated. 2. GND potential Ensure a minimum GND pin potential in all operating conditions. In addition, ensure that no pins other than the GND pin carry a voltage lower than or equal to the GND pin, including during actual transient phenomena. if there is a terminal, electric potential of which is lower than that of GND, please take such measures as provide a bypass route etc. 3. Permissible dissipation Pd If by any chance you use it in such a way that the permissible dissipation is exceeded, occurs the deterioration of original performances of IC such as reduction of current capacity caused by an increase in temperature of chip, which will lead to a decline in reliability, therefore please use it in such a way that its dissipation is within the permissible one and allows for a sufficient margin. 4. Input power supply Please wire and arrange in such a way that, in the wiring pattern and pattern layout, the wiring to the input pin VIN is sufficiently short and furthermore electrical interference is not caused. The electrical characteristics included in this specification may vary with such conditions as temperature, power supply voltage and external circuits etc., so please confirm them thoroughly including transient characteristic. 6. Thermal shutdown circuit Thermal shutdown circuit is built-in in order to prevent the thermal destruction of IC. Please use it within its permissible dissipation range, but if by any chance the state of exceeding the permissible dissipation continues, the temperature of chip rises, as a result the thermal shutdown circuit operates and so the output is turned off. If after that the temperature Tj of chip falls, the circuit resets automatically. Furthermore, the thermal shutdown circuit leads to the state of exceeding the absolute maximum rating, so please absolutely avoid such set design as uses the thermal shutdown circuit. 7. nter-pin shorts and mounting errors Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in damage to the IC. Shorts between output pins or between output pins and the power supply and GND pin caused by the presence of a foreign object may result in damage to the IC. 8. Applications with modes that reverse VCC and pin potentials may cause damage to internal IC circuits. For example, such damage might occur when VCC is shorted with the GND pin while an external capacitor is charged. Please use 1μF and 0.1μF respectively as the capacitor of VREG5’s output terminal and the capacitor of VREG3’s output terminal. Moreover, it is recommended to insert a diode for preventing back current flow in series with VCC or bypass diodes between VCC and each pin. 9.Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction. 10. Please insert the protective diode when it is conceivable that the back electromotive force is produced at the time of start-up or output OFF because a load that has a large inductance component is connected on output terminal. 11. Testing on application boards When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always discharge capacitors after each process or step. Ground the IC during assembly steps as an antistatic measure, and use similar caution when transporting or storing the IC. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process. 12. GND wiring pattern If there are both small-signal GND and large-current GND, then large-current GND pattern and small-signal GND pattern are separated, and in order that the pattern wiring and the voltage change caused by large current do not change the voltage of small-signal GND, it is recommended to carry out the one-point grounding at the reference point of set. Please be careful of not changing the GND wiring pattern of external parts. 13. SW terminal In case of connecting of application, SW terminal may become a negative electric potential due to the back electromotive force of coil. Please take such measures as provide a bypas route between SW terminal and GND at the time of setting of application. 14. Output At the time of EN=L， UVLO, and timer latch, the current flows out from SW terminal. If the service condition is such that the output load becomes no more than 1mA, then please insert a 1kΩ resistor between output and GND. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 17/18 2009.05 - Rev.A BD9040FV, BD9045FV ●Ordering part number Technical Note B D 9 Part No. 9040 9045 0 4 0 F V - E 2 Part No. Package FV : SSOP-B20 SSOP-B28 Packaging and forming specification E2: Embossed tape and reel (SSOP-B20, SSOP-B28) SSOP-B20 6.5 ± 0.2 20 11 Tape Quantity 0.3Min. Embossed carrier tape 2500pcs E2 The direction is the 1pin of product is at the upper left when you hold 6.4 ± 0.3 4.4 ± 0.2 Direction of feed ( reel on the left hand and you pull out the tape on the right hand ) 1 10 0.15 ± 0.1 1.15 ± 0.1 0.1± 0.1 0.1 0.65 0.22 ± 0.1 1pin (Unit : mm) Direction of feed Reel ∗ Order quantity needs to be multiple of the minimum quantity. SSOP-B28 10 ± 0.2 (MAX 10.35 include BURR) 28 15 Tape Quantity Direction of feed 0.3Min. Embossed carrier tape 2000pcs E2 The direction is the 1pin of product is at the upper left when you hold 7.6 ± 0.3 5.6 ± 0.2 ( reel on the left hand and you pull out the tape on the right hand ) 1 14 1.15 ± 0.1 0.15 ± 0.1 0.1 0.1 0.65 0.22 ± 0.1 1pin (Unit : mm) Direction of feed Reel ∗ Order quantity needs to be multiple of the minimum quantity. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 18/18 2009.05 - Rev.A Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law. Thank you for your accessing to ROHM product informations. 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