Single-chip built-in FET type Switching Regulator Series
Output 1.5A or Less High Efficiency Step-down Switching Regulators with Built-in Power MOSFET
BD9102FVM, BD9104FVM, BD9106FVM
No.09027EAT34
●Description ROHM’s high efficiency step-down switching regulator (BD9102FVM, BD9104FVM, BD9106FVM) is a power supply designed to produce a low voltage including 1.24 volts from 5 volts power supply line. Offers high efficiency with our original pulse skip control technology and synchronous rectifier. Employs a current mode control system to provide faster transient response to sudden change in load. ●Features 1) Offers fast transient response with current mode PWM control system. 2) Offers highly efficiency for all load range with synchronous rectifier (Nch/Pch FET) TM and SLLM (Simple Light Load Mode) 3) Incorporates soft-start function. 4) Incorporates thermal protection and ULVO functions. 5) Incorporates short-current protection circuit with time delay function. 6) Incorporates shutdown function 7) Employs small surface mount package MSOP8 ●Use Power supply for HDD, power supply for portable electronic devices like PDA, and power supply for LSI including CPU and ASIC ●Lineup Parameter Vcc voltage Output voltage Output current UVLO Threshold voltage Short-current protection with time delay function Soft start function Standby current Operating temperature range Package ●Absolute Maximum Rating (Ta=25℃) Parameter VCC voltage PVCC voltage EN voltage SW,ITH voltage Power dissipation 1 Power dissipation 2 Operating temperature range Storage temperature range Maximum junction temperature
*1 *2 *3
BD9102FVM 4.0~5.5V 1.24V±2% 0.8A Max. 2.7V Typ. built-in built-in 0μA Typ. -25~+85℃ MSOP8
BD9104FVM 4.5~5.5V 3.30V±2% 0.9A Max. 4.1V Typ. built-in built-in 0μA Typ. -25~+85℃ MSOP8
BD9106FVM 4.0~5.5V Adjustable(1.0~2.5V) 0.8A Max. 3.4V Typ. built-in built-in 0μA Typ. -25~+85℃ MSOP8
Symbol VCC PVCC EN SW,ITH Pd1 Pd2 Topr Tstg Tjmax
Limits -0.3~+7 *1 -0.3~+7 *1 -0.3~+7 -0.3~+7 387.5*2 587.4*3 -25~+85 -55~+150 +150
Unit V V V V mW mW ℃ ℃ ℃
Pd should not be exceeded. Derating in done 3.1mW/℃ for temperatures above Ta=25℃. Derating in done 4.7mW/℃ for temperatures above Ta=25℃,Mounted on 70mm×70mm×1.6mm Glass Epoxy PCB
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1/17
2009.05 - Rev.A
BD9102FVM, BD9104FVM, BD9106FVM
●Recommended Operating Conditions (Ta=25℃) BD9102FVM Parameter Symbol Min. Max. VCC voltage PVCC voltage EN voltage SW average output current
*4 Pd should not be exceeded.
Technical Note
BD9104FVM Min. 4.5 4.5 0 Max. 5.5 5.5 VCC 0.8
BD9106FVM Min. 4.0 4.0 0 Max. 5.5 5.5 VCC 0.8
Unit V V V A
VCC PVCC EN Isw*4
*4
4.0 4.0 0 -
5.5 5.5 VCC 0.8
●Electrical Characteristics ◎BD9102FVM(Ta=25℃,VCC=5V,EN=VCC unless otherwise specified.) Parameter Symbol Min. Typ. Standby current Bias current EN Low voltage EN High voltage EN input current Oscillation frequency Pch FET ON resistance *5 Nch FET ON resistance Output voltage ITH SInk current ITH Source Current UVLO threshold voltage UVLO hysteresis voltage Soft start time Timer latch time
*5
Max. 10 400 0.8 10 1.2 0.60 0.50 1.265 2.8 200 2 2
Unit μA μA V V μA MHz Ω Ω V μA μA V mV ms ms
Conditions EN=GND Standby mode Active mode VEN=5V PVCC=5V PVCC=5V VOUT=H VOUT=L VCC=H→L
ISTB ICC VENL VENH IEN FOSC RONP RONN VOUT ITHSI ITHSO VUVLOTh VUVLOHys TSS TLATCH
2.0 0.8 1.215 10 10 2.6 50 0.5 0.5
0 250 GND VCC 1 1 0.35 0.25 1.24 20 20 2.7 100 1 1
*5 Design Guarantee(Outgoing inspection is not done on all products)
◎BD9104FVM(Ta=25℃,VCC=5V,EN=VCC unless otherwise specified.) Parameter Symbol Min. Typ. Standby current Bias current EN Low voltage EN High voltage EN input current Oscillation frequency Pch FET ON resistance *5 Nch FET ON resistance Output voltage ITH SInk current ITH Source Current UVLO threshold voltage UVLO hysteresis voltage Soft start time Timer latch time
*5
Max. 10 400 0.8 10 1.2 0.60 0.50 3.366 4.3 200 2 2
Unit μA μA V V μA MHz Ω Ω V μA μA V mV ms ms
Conditions EN=GND Standby mode Active mode VEN=5V PVCC=5V PVCC=5V VOUT=H VOUT=L VCC=H→L
ISTB ICC VENL VENH IEN FOSC RONP RONN VOUT ITHSI ITHSO VUVLOTh VUVLOHys TSS TLATCH
2.0 0.8 3.234 10 10 3.9 50 0.5 0.5
0 250 GND VCC 1 1 0.35 0.25 3.300 20 20 4.1 100 1 1
*5 Design Guarantee(Outgoing inspection is not done on all products)
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2/17
2009.05 - Rev.A
BD9102FVM, BD9104FVM, BD9106FVM
◎BD9106FVM(Ta=25℃,VCC=5V,EN=VCC,R1=20kΩ,R2=10kΩunless otherwise specified.) Parameter Symbol Min. Typ. Max. Standby current Bias current EN Low voltage EN High voltage EN input current Oscillation frequency Pch FET ON resistance *5 Nch FET ON resistance ADJ reference voltage Output voltage ITH SInk current ITH Source Current UVLO threshold voltage UVLO hysteresis voltage Soft start time Timer latch time
*5
Technical Note
Unit μA μA V V μA MHz Ω Ω V V μA μA V mV ms ms
Conditions EN=GND Standby mode Active mode VEN=5V PVCC=5V PVCC=5V
ISTB ICC VENL VENH IEN FOSC RONP RONN VADJ VOUT ITHSI ITHSO VUVLOTh VUVLOHys TSS TLATCH
2.0 0.8 0.780 10 10 3.2 50 1.5 0.5
0 250 GND VCC 1 1 0.35 0.25 0.800 1.200 20 20 3.4 100 3 1
10 400 0.8 10 1.2 0.60 0.50 0.820 3.6 200 6 2
ADJ=H ADJ=L VCC=H→L
*5 Design Guarantee(Outgoing inspection is not done on all products)
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3/17
2009.05 - Rev.A
BD9102FVM, BD9104FVM, BD9106FVM
●Characteristics data ■VCC-VOUT
2 Ta=25℃
OUTPUT VOLTAGE:VOUT[V]
Technical Note
[BD9102FVM]
OUTPUT VOLTAGE:VOUT[V]
4
Ta=25℃
[BD9104FVM]
OUTPUT VOLTAGE:VOUT[V]
2
Ta=25℃
[BD9106FVM]
1.5
3
1.5
1
2
1
0.5
1
0.5
0 0 1 2 3 4 INPUT VOLTAGE:VCC[V] 5
0 0 1 2 3 4 INPUT VOLTAGE:VCC[V] 5
0 0 1 2 3 4 INPUT VOLTAGE:VCC[V] 5
Fig.1 Vcc-Vout ■VEN-VOUT
2
OUTPUT VOLTAGE:VOUT[V] OUTPUT VOLTAGE:VOUT[V]
Fig.2 Vcc-Vout
4
Fig.3 Vcc-Vout
1.5
3
OUTPUT VOLTAGE:VOUT[V]
VCC=5V Ta=25℃
[BD9102FVM]
VCC=5V Ta=25℃
[BD9104FVM]
2
VCC=5V Ta=25℃
[BD9106FVM]
1.5
1
2
1
0.5
1
0.5
0 0 1 2 3 4 EN VOLTAGE:VEN[V] 5
0 0 1 2 3 4 EN VOLTAGE:VEN[V] 5
0 0 1 2 3 4 EN VOLTAGE:VEN[V] 5
Fig.4 Ven-Vout ■IOUT-VOUT
2 OUTPUT VOLTAGE:VOUT[V]
OUTPUT VOLTAGE:VOUT[V] 4
Fig.5 Ven-Vout
2
Fig.6 Ven-Vout
OUTPUT VOLTAGE:VOUT[V]
VCC=5V Ta=25℃
1.5
[BD9102FVM]
3
VCC=5V Ta=25℃
[BD9104FVM]
1.5
[BD9106FVM]
1
2
1
0.5
1
0.5
VCC=5V Ta=25℃
0 0 1 2 OUTPUT CURRENT:IOUT[A] 3
0 0 1 2 OUTPUT CURRENT:IOUT[A] 3
0 0 1 2 OUTPUT CURRENT:IOUT[A] 3
Fig.7 Iout-Vout ■Soft start
[BD9102FVM]
Fig.8 Iout-Vout
Fig.9 Iout-Vout
[BD9104FVM]
[BD9106FVM]
VCC=PVCC=EN
VCC=PVCC=EN
VCC=PVCC=EN
VOUT
Ta=25℃
VOUT
Ta=25℃
VOUT
Ta=25℃
Fig.10 Soft start waveform
Fig.11 Soft start waveform
Fig.12 Soft start waveform
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4/17
2009.05 - Rev.A
BD9102FVM, BD9104FVM, BD9106FVM
■SW waveform IO=10mA
[BD9102FVM] [BD9104FVM]
Technical Note
[BD9106FVM]
SW
SW
SW
VOUT
VCC=5V Ta=25℃
VOUT
VCC=5V Ta=25℃
VOUT
VCC=5V Ta=25℃
Fig.13 SW waveform TM Io=10mA(SLLM control) ■SW waveform IO=200mA
[BD9102FVM]
Fig.14 SW waveform Io=10mA(SLLMTM control)
Fig.15 SW waveform Io=10mA(SLLMTM control
[BD9104FVM]
[BD9106FVM]
SW
SW
SW
VOUT
VCC=5V Ta=25℃
VOUT
VCC=5V Ta=25℃
VOUT
VCC=5V Ta=25℃
Fig.16 SW waveform Io=200mA(PWM control) ■Transient response IO=100mA → 600mA
[BD9102FVM]
Fig.17 SW waveform Io=200mA(PWM control)
Fig.18 SW waveform Io=200mA(PWM control VOUT=1.8V)
[BD9104FVM]
[BD9106FVM]
VOUT
VOUT
VOUT
IOUT
VCC=5V Ta=25℃
IOUT
VCC=5V Ta=25℃
IOUT
VCC=5V Ta=25℃
Fig.19 Transient response Io=100→600mA(10μs) ■Transient response IO=600mA → 100mA
[BD9102FVM]
Fig.20 Transient response Io=100→600mA(10μs)
Fig.21 Transient response Io=100→600mA(10μs) (VOUT=1.8V)
[BD9106FVM]
[BD9104FVM]
VOUT
VOUT
VOUT
IOUT
IOUT
VCC=5V Ta=25℃ VCC=5V Ta=25℃
IOUT
VCC=5V Ta=25℃
Fig.22 Transient response Io=600→100mA(10μs)
Fig.23 Transient response Io=600→100mA(10μs)
Fig.24 Transient response Io=600→100mA(10μs) (VOUT=1.8V)
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5/17
2009.05 - Rev.A
BD9102FVM, BD9104FVM, BD9106FVM
■Ta-VOUT
Technical Note
1.28 OUTPUT VOLTAGE:VOUT[V]
OUTPUT VOLTAGE:VOUT[V]
3.5
1.85
OUTPUT VOLTAGE:VOUT[V]
1.27 1.26 1.25 1.24 1.23 1.22 1.21 1.2
VCC=5V
[BD9102FVM]
3.45 3.4 3.35 3.3 3.25 3.2 3.15 3.1 3.05 3
VCC=5V
[BD9104FVM]
1.84 1.83 1.82 1.81 1.8 1.79 1.78 1.77 1.76 1.75
VCC=5V
[BD9106FVM]
-25 -15 -5
5
15 25 35 45 55 65 75 85
-25 -15 -5
5
15 25 35 45 55 65 75 85
-25 -15 -5
5
15 25 35 45 55 65 75 85
TEMPERATURE:Ta[℃]
TEMPERATURE:Ta[℃]
TEMPERATURE:Ta[℃]
Fig.25 Ta-VOUT ■Efficiency
100 90 80 EFFICIENCY:η[%] EFFICIENCY:η[%] 70 60 50 40 30 20 10 0 1 10 100 OUTPUT CURRENT:IOUT[mA] 1000
Fig.26 Ta-VOUT
Fig.27 Ta-VOUT
Ta=25℃
100 90 80 70 60 50 40 30 20 [BD9102FVM] 10 0 1
Ta=25℃
100 90 80 EFFICIENCY:η[%] 70 60 50 40 30 20 10 0
Ta=25℃
[BD9104FVM] 10 100 OUTPUT CURRENT:IOUT[mA] 1000
[BD9106FVM]
1
10 100 OUTPUT CURRENT:IOUT[mA]
1000
Fig.28 Efficiency (VCC=EN=5V VOUT=1 24V) ■Reference characteristics
1.2
NMOS ON RESISTANCE:RONN[Ω]
Fig.29 Efficiency (VCC=EN=5V,VOUT=3.3V)
Fig.30 Efficiency (VCC=EN=5V,VOUT=1.8V)
0.4 VCC=5V 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0
-25 -15 -5 5 15 25 35 45 55 65 75 85
-25 -15 -5 5 15 25 35 45 55 65 75 85
0.4
VCC=5V
PMOS ON RESISTANCE:R ONP[Ω]
1.15 FREQUENCY:FOSC[MHz] 1.1 1.05 1 0.95 0.9 0.85 0.8
0.35 0.3 0.25 0.2 0.15 0.1 0.05 0
VCC=5V
BD9102FVM BD9104FVM BD9106FVM
BD9102FVM BD9104FVM BD9106FVM
BD9102FVM BD9104FVM BD9106FVM
-25 -15 -5
5
15 25 35 45 55 65 75 85
TEMPERATURE:Ta[℃]
TEMPERATURE:Ta[℃]
TEMPERATURE:Ta[℃]
Fig.31 Ta-FOSC
2 1.8 EN VOLTAGE:VEN[V] 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0
-25 -15 -5 5 15 25 35 45 55 65 75 85
Fig.32 Ta-RONN
350
Fig.33Ta-RONP
1.2
VCC=5V
CIRCUIT CURRENT:ICC[μA] 300
VCC=5V
FREQUENCY:FOSC[MHz]
Ta=25℃ 1.1
250 200 150 100 50 0
-25 -15 -5 5 15 25 35 45 55 65 75 85
1
BD9102FVM BD9104FVM BD9106FVM
BD9102FVM BD9104FVM BD9106FVM
0.9
BD9102FVM BD9104FVM BD9106FVM
0.8 4
TEMPERATURE:Ta[℃]
TEMPERATURE:Ta[℃]
4.5 5 INPUT VOLTAGE:VCC[V]
5.5
Fig.34 Ta-VEN
Fig.35 Ta-ICC
Fig.36 Vcc-Fosc
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6/17
2009.05 - Rev.A
BD9102FVM, BD9104FVM, BD9106FVM
●Block diagram, Application circuit 【BD9102FVM,BD9104FVM】
VCC EN 3 VREF 1 2 3 4 VOUT ITH EN GND VCC PVCC SW PGND 8 7 6 5 Gm Amp. SLOPE VCC Soft Start OSC Current Comp. RQ S CLK Driver Logic
Technical Note
8 7 Current Sense/ Protect + 6
VCC 5V Input PVCC 10μF
4.7μH SW 10μF 5 4
Output
TOP View
UVLO TSD
PGND GND
1
VOUT
2
ITH
Fig.37 BD9102FVM BD9104FVM TOP View
EN BD9106FVM 1 2 3 4 ADJ ITH EN GND VCC PVCC SW PGND 8 7 6
Fig.38 BD9102FVM BD9104FVM Block diagram
VCC 3 VREF Current Comp. RQ Gm Amp. S SLOPE VCC OSC CLK Driver Logic 5 4 8 7 Current Sense/ Protect + 6 SW 10μF VCC 5V Input PVCC 10μF
5
4.7μH
Output
TOP View Soft Start
UVLO TSD
PGND GND
1
ADJ
2
ITH
Fig.39 BD9106FVM TOP View ●Pin No. & function table Pin No. 1 2 3 4 5 6 7 8
Fig.40 BD9106FVM Block diagram
Pin name VOUT/ADJ ITH EN GND PGND SW PVCC VCC
PIN function Output voltage detect pin/ ADJ for BD9106FVM GmAmp output pin/Connected phase compensation capacitor Enable pin(Active High) Ground Nch FET source pin Pch/Nch FET drain output pin Pch FET source pin VCC power supply input pin
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7/17
2009.05 - Rev.A
BD9102FVM, BD9104FVM, BD9106FVM
Technical Note
●Information on advantages Advantage 1:Offers fast transient response with current mode control system. Conventional product (VOUT of which is 3.3 volts) BD9104FVM(Load response IO=100mA→600mA)
VOUT 228mV VOUT 110mV
IOUT
IOUT
Voltage drop due to sudden change in load was reduced by 50%. Fig.41 Comparison of transient response Advantage 2: Offers high efficiency for all load range. ・For lighter load: Utilizes the current mode control mode called SLLM for lighter load, which reduces various dissipation such as switching dissipation (PSW), gate charge/discharge dissipation, ESR dissipation of output capacitor (PESR) and on-resistance dissipation (PRON) that may otherwise cause degradation in efficiency for lighter load.
Achieves efficiency improvement for lighter load.
Efficiency η[%]
100
SLLMTM ②
・For heavier load: Utilizes the synchronous rectifying mode and the low on-resistance MOS FETs incorporated as power transistor. ON resistance of P-channel MOS FET: 0.35 Ω (Typ.) ON resistance of N-channel MOS FET: 0.25 Ω (Typ.)
50
①
PWM
①inprovement by SLLM system ②improvement by synchronous rectifier
0 0.001
0.01 0.1 Output current Io[A]
1
Fig.42 Efficiency
Achieves efficiency improvement for heavier load. Offers high efficiency for all load range with the improvements mentioned above. Advantage 3:・Supplied in smaller package like MOSP8 due to small-sized power MOS FET incorporated. ・Allows reduction in size of application products ・Output capacitor Co required for current mode control: 10 μF ceramic capacitor ・Inductance L required for the operating frequency of 1 MHz: 4.7 μH inductor Reduces a mounting area required.
VCC 15mm Cin CIN DC/DC Convertor Controller RITH L VOUT Co 10mm CITH CO L
RITH CITH
Fig.43 Example application
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8/17
2009.05 - Rev.A
BD9102FVM, BD9104FVM, BD9106FVM
Technical Note
●Operation BD9102FVM, BD9104FVM, BD9106FVM are the synchronous rectifying step-down switching regulator that achieves faster transient response by employing current mode PWM control system. It utilizes switching operation in PWM (Pulse Width TM Modulation) mode for heavier load, while it utilizes SLLM (Simple Light Load Mode) operation for lighter load to improve efficiency. ○Synchronous rectifier It does not require the power to be dissipated by a rectifier externally connected to a conventional DC/DC converter IC, and its P.N junction shoot-through protection circuit limits the shoot-through current during operation, by which the power dissipation of the set is reduced. ○Current mode PWM control Synthesizes a PWM control signal with a inductor current feedback loop added to the voltage feedback. ・PWM (Pulse Width Modulation) control The oscillation frequency for PWM is 1 MHz. SET signal form OSC turns ON a P-channel MOS FET (while a N-channel MOS FET is turned OFF), and an inductor current IL increases. The current comparator (Current Comp) receives two signals, a current feedback control signal (SENSE: Voltage converted from IL) and a voltage feedback control signal (FB), and issues a RESET signal if both input signals are identical to each other, and turns OFF the P-channel MOS FET (while a N-channel MOS FET is turned ON) for the rest of the fixed period. The PWM control repeat this operation.
TM ・SLLM (Simple Light Load Mode) control When the control mode is shifted from PWM for heavier load to the one for lighter load or vise versa, the switching pulse is designed to turn OFF with the device held operated in normal PWM control loop, which allows linear operation without voltage drop or deterioration in transient response during the mode switching from light load to heavy load or vise versa. Although the PWM control loop continues to operate with a SET signal from OSC and a RESET signal from Current Comp, it is so designed that the RESET signal is held issued if shifted to the light load mode, with which the switching is tuned OFF and the switching pulses are thinned out under control. Activating the switching intermittently reduces the switching dissipation and improves the efficiency.
SENSE Current Comp Level Shift Gm Amp. ITH FB RESET RQ Driver Logic SW Load IL VOUT
VOUT
SET S OSC
Fig.44 Diagram of current mode PWM control
PVCC SENSE FB SET GND GND GND IL(AVE) SET PVCC SENSE FB GND GND
Current Comp
Current Comp
RESET SW IL
RESET SW
GND IL 0A
VOUT
VOUT(AVE)
VOUT
VOUT(AVE)
Not switching
Fig.45 PWM switching timing chart
Fig.46 SLLMTM switching timing chart
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9/17
2009.05 - Rev.A
BD9102FVM, BD9104FVM, BD9106FVM
Technical Note
●Description of operations ・Soft-start function EN terminal shifted to “High” activates a soft-starter to gradually establish the output voltage with the current limited during startup, by which it is possible to prevent an overshoot of output voltage and an inrush current. ・Shutdown function With EN terminal shifted to “Low”, the device turns to Standby Mode, and all the function blocks including reference voltage circuit, internal oscillator and drivers are turned to OFF. Circuit current during standby is 0 μF (Typ.). ・UVLO function Detects whether the input voltage sufficient to secure the output voltage of this IC is supplied. And the hysteresis width of 100 mV (Typ.) is provided to prevent output chattering. ・BD9102FVM BD9104FVM TSS=1msec(typ.) ・BD9106FVM TSS=3msec(typ.)
Hysteresis 100mV
VCC
EN
VOUT
Tss Soft start Standby mode Operating mode Standby mode UVLO
Tss
Tss
Operating mode
Standby mode EN
Operating mode
Standby mode
UVLO
Fig.47 Soft start, Shutdown, UVLO timing chart
UVLO
・Short-current protection circuit with time delay function Turns OFF the output to protect the IC from breakdown when the incorporated current limiter is activated continuously for at least 1 ms. The output thus held tuned OFF may be recovered by restarting EN or by re-unlocking UVLO.
EN
Output OFF latch VOUT Limit IL 1msec Standby mode EN Standby mode Timer latch EN
Operating mode
Operating mode
Fig.48 Short-current protection circuit with time delay timing chart
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10/17
2009.05 - Rev.A
BD9102FVM, BD9104FVM, BD9106FVM
●Switching regulator efficiency Efficiency ŋ may be expressed by the equation shown below: VOUT×IOUT POUT POUT η= ×100[%]= ×100[%]= Vin×Iin Pin POUT+PDα
Technical Note
×100[%]
Efficiency may be improved by reducing the switching regulator power dissipation factors PDα as follows: Dissipation factors: 2 1) ON resistance dissipation of inductor and FET:PD(I R) 2) Gate charge/discharge dissipation:PD(Gate) 3) Switching dissipation:PD(SW) 4) ESR dissipation of capacitor:PD(ESR) 5) Operating current dissipation of IC:PD(IC)
2 2 1)PD(I R)=IOUT ×(RCOIL×RON) (RCOIL[Ω]:DC resistance of inductor, RON[Ω]:ON resistance of FET IOUT[A]:Output current.) 2)PD(Gate)=Cgs×f×V (Cgs[F]:Gate capacitance of FET,f[H]:Switching frequency,V[V]:Gate driving voltage of FET)
3)PD(SW)=
Vin2×CRSS×IOUT×f IDRIVE
(CRSS[F]:Reverse transfer capacitance of FET,IDRIVE[A]:Peak current of gate.)
2 4)PD(ESR)=IRMS ×ESR (IRMS[A]:Ripple current of capacitor,ESR[Ω]:Equivalent series resistance.) 5)PD(IC)=Vin×ICC (ICC[A]:Circuit current.)
●Consideration on permissible dissipation and heat generation As this IC functions with high efficiency without significant heat generation in most applications, no special consideration is needed on permissible dissipation or heat generation. In case of extreme conditions, however, including lower input voltage, higher output voltage, heavier load, and/or higher temperature, the permissible dissipation and/or heat generation must be carefully considered. For dissipation, only conduction losses due to DC resistance of inductor and ON resistance of FET are considered. Because the conduction losses are considered to play the leading role among other dissipation mentioned above including gate charge/discharge dissipation and switching dissipation.
2 P=IOUT ×(RCOIL+RON) RON=D×RONP+(1-D)RONN
1000
①using an IC alone
Power dissipation:Pd [mW]
D:ON duty (=VOUT/VCC) RCOIL:DC resistance of coil RONP:ON resistance of P-channel MOS FET RONN:ON resistance of N-channel MOS FET IOUT:Output current If VCC=5V, VOUT=3.3V, RCOIL=0.15Ω, RONP=0.35Ω, RONN=0.25Ω IOUT=0.8A, for example, D=VOUT/VCC=3.3/5=0.66 RON=0.66×0.35+(1-0.66)×0.25 =0.231+0.085 =0.316[Ω] P=0.8 ×(0.15+0.316) ≒298[mV]
2
800 ①587.4mW
θj-a=322.6℃/W
②mounted on glass epoxy PCB
θj-a=212.8℃/W
600
400
②387.5mW
200
0 0
Fig.49 Thermal derating curves
Ambient temperature:Ta [℃] 25 50 75 85 100 125
150
As RONP is greater than RONN in this IC, the dissipation increases as the ON duty becomes greater. With the consideration on the dissipation as above, thermal design must be carried out with sufficient margin allowed.
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11/17
2009.05 - Rev.A
BD9102FVM, BD9104FVM, BD9106FVM
●Selection of components externally connected 1. Selection of inductor (L)
IL ΔIL VCC
Technical Note
IL VOUT L Co
The inductance significantly depends on output ripple current. As seen in the equation (1), the ripple current decreases as the inductor and/or switching frequency increases. (VCC-VOUT)×VOUT ΔIL= [A]・・・(1) L×VCC×f Appropriate ripple current at output should be 30% more or less of the maximum output current. ΔIL=0.3×IOUTmax. [A]・・・(2) (VCC-VOUT)×VOUT [H]・・・(3) L= ΔIL×VCC×f (ΔIL: Output ripple current, and f: Switching frequency)
Fig.50 Output ripple current
* Current exceeding the current rating of the inductor results in magnetic saturation of the inductor, which decreases efficiency. The inductor must be selected allowing sufficient margin with which the peak current may not exceed its current rating.
If VCC=5V, VOUT=3.3V, f=1MHz, ΔIL=0.3×0.8A=0.24A, for example, L= (5-3.3)×3.3 0.24×5×1M =4.675μ → 4.7[μH]
*Select the inductor of low resistance component (such as DCR and ACR) to minimize dissipation in the inductor for better efficiency.
2. Selection of output capacitor (CO)
VCC
Output capacitor should be selected with the consideration on the stability region and the equivalent series resistance required to smooth ripple voltage. Output ripple voltage is determined by the equation (4):
VOUT ESR Co
L
ΔVOUT=ΔIL×ESR [V]・・・(4) (ΔIL: Output ripple current, ESR: Equivalent series resistance of output capacitor) *Rating of the capacitor should be determined allowing sufficient margin against output voltage. Less ESR allows reduction in output ripple voltage.
Fig.51 Output capacitor
As the output rise time must be designed to fall within the soft-start time, the capacitance of output capacitor should be determined with consideration on the requirements of equation (5): TSS×(Ilimit-IOUT) Tss: Soft-start time ・・・(5) Ilimit: Over current detection level, 2A(Typ) VOUT In case of BD9104FVM, for instance, and if VOUT=3.3V, IOUT=0.8A, and TSS=1ms, 1m×(2-0.8) Co≦ ≒364 [μF] 3.3 Inappropriate capacitance may cause problem in startup. A 10 μF to 100 μF ceramic capacitor is recommended. Co≦ 3. Selection of input capacitor (Cin)
VCC Cin
Input capacitor to select must be a low ESR capacitor of the capacitance sufficient to cope with high ripple current to prevent high transient voltage. ripple current IRMS is given by the equation (6): √ CC(VCC-VOUT) V VCC < Worst case > IRMS(max.) IRMS=IOUT× [A]・・・(6) IOUT 2
The
VOUT L Co
When VCC is twice the Vout, IRMS= Fig.52 Input capacitor IRMS=0.8×
If VCC=5V, VOUT=3.3V, and IOUTmax.=0.8A, √ (5-3.3) 5 5 =0.46[ARMS]
A low ESR 10μF/10V ceramic capacitor is recommended to reduce ESR dissipation of input capacitor for better efficiency.
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12/17
2009.05 - Rev.A
BD9102FVM, BD9104FVM, BD9106FVM
Technical Note
4. Determination of RITH, CITH that works as a phase compensator As the Current Mode Control is designed to limit a inductor current, a pole (phase lag) appears in the low frequency area due to a CR filter consisting of a output capacitor and a load resistance, while a zero (phase lead) appears in the high frequency area due to the output capacitor and its ESR. So, the phases are easily compensated by adding a zero to the power amplifier output with C and R as described below to cancel a pole at the power amplifier.
fp(Min.) A Gain [dB] fp(Max.) 0 IOUTMin. 0 IOUTMax. fz(ESR)
fp=
1 2π×RO×CO 1 fz(ESR)= 2π×ESR×CO Pole at power amplifier When the output current decreases, the load resistance Ro increases and the pole frequency lowers. fp(Min.)= 1 2π×ROMax.×CO 1 2π×ROMin.×CO [Hz]←with lighter load [Hz]←with heavier load
Phase [deg]
-90
Fig.53 Open loop gain characteristics fp(Max.)=
A Gain [dB] 0 0 fz(Amp.)
Zero at power amplifier Increasing capacitance of the output capacitor lowers the pole frequency while the zero frequency does not change. (This is because when the capacitance is doubled, the capacitor ESR reduces to half.) fz(Amp.)= 1 2π×RITH.×CITH
Phase [deg]
-90
Fig.54 Error amp phase compensation characteristics
VCC
Cin EN VOUT VOUT ITH RITH CITH
VCC,PVCC
L SW ESR RO VOUT
GND,PGND
CO
Fig.55 Typical application Stable feedback loop may be achieved by canceling the pole fp (Min.) produced by the output capacitor and the load resistance with CR zero correction by the error amplifier. fz(Amp.)= fp(Min.) 1 2π×RITH×CITH = 1 2π×ROMax.×CO
5. Determination of output voltage (for BD9106FVM only) The output voltage VOUT is determined by the equation (7): VOUT=(R2/R1+1)×VADJ・・・(7) VADJ: Voltage at ADJ terminal (0.8V Typ.) With R1 and R2 adjusted, the output voltage may be determined as required.(Adjustable output voltage range: 1.0V~2.5V) Use 1 kΩ~100 kΩ resistor for R1. If a resistor of the resistance higher than100 kΩ is used, check the assembled set carefully for ripple voltage etc.
4.7μH 6 SW 1 ADJ R1 10μF R2 Output
Fig.56 Determination of output voltage
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13/17
2009.05 - Rev.A
BD9102FVM, BD9104FVM, BD9106FVM
●BD9102FVM, BD9104FVM, BD9106FVM Cautions on PC Board layout
Technical Note
1 2 RITH EN CITH 4 ③ 3
VOUT/ADJ ITH EN GND
VCC PVCC SW PGND
8 7 CIN 6 5 CO ② L VCC ① VOUT GND
Fig.57 Layout diagram ① For the sections drawn with heavy line, use thick conductor pattern as short as possible. ② Lay out the input ceramic capacitor CIN closer to the pins PVCC and PGND, and the output capacitor Co closer to the pin PGND. ③ Lay out CITH and RITH between the pins ITH and GND as neat as possible with least necessary wiring. Table1.Recommended parts list of application [BD9102FVM] symbol part value manufacturer L Inductor 4.7μH Sumida CIN CO CITH RITH Ceramic capacitor Ceramic capacitor Ceramic capacitor Resistor 10μF 10μF 330pF 30kΩ Kyocera Kyocera murata ROHM
series CMD6D11B CM316X5R106M10A CM316X5R106M10A GRM18series MCR10 3002
Table2. Recommended parts list of application [BD9104FVM] symbol part value manufacturer L Inductor 4.7μH Sumida CIN CO CITH RITH Ceramic capacitor Ceramic capacitor Ceramic capacitor Resistor 10μF 10μF 330pF 51kΩ Kyocera Kyocera murata ROHM
series CMD6D11B CM316X5R106M10A CM316X5R106M10A GRM18series MCR10 5102
Table3.Recommended parts list of application [BD9106FVM] symbol part value manufacturer L Inductor 4.7μH Sumida CIN CO CITH Ceramic capacitor Ceramic capacitor Ceramic capacitor 10μF 10μF 750pF Kyocera Kyocera murata
series CMD6D11B CM316X5R106M10A CM316X5R106M10A GRM18series
Table4.BD9106FVM RITH recommended value Vout[V] RITH 1.0 18kΩ 1.2 22kΩ 1.5 22kΩ *BD9106FVM: As the resistance recommended for RITH depends on the output voltage, check the output voltage for determination of resistance. 1.8 27kΩ 2.5 36kΩ
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14/17
2009.05 - Rev.A
BD9102FVM, BD9104FVM, BD9106FVM
●I/O equivalence circuit
1pin(VOUT) VCC ※BD9106FVM 1pin(ADJ) VCC
Technical Note
10kΩ VOUT ADJ
10kΩ
2pin(ITH) VCC VCC
3pin(EN) VCC
2.8MΩ ITH EN
10kΩ
2.2kΩ
6pin(SW) PVCC PVCC PVCC
SW
Fig.58 I/O equivalence circuit
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15/17
2009.05 - Rev.A
BD9102FVM, BD9104FVM, BD9106FVM
Technical Note
●Notes for use 1. Absolute Maximum Ratings While utmost care is taken to quality control of this product, any application that may exceed some of the absolute maximum ratings including the voltage applied and the operating temperature range may result in breakage. If broken, short-mode or open-mode may not be identified. So if it is expected to encounter with special mode that may exceed the absolute maximum ratings, it is requested to take necessary safety measures physically including insertion of fuses. 2. Electrical potential at GND GND must be designed to have the lowest electrical potential In any operating conditions. 3. Short-circuiting between terminals, and mismounting When mounting to pc board, care must be taken to avoid mistake in its orientation and alignment. Failure to do so may result in IC breakdown. Short-circuiting due to foreign matters entered between output terminals, or between output and power supply or GND may also cause breakdown. 4.Operation in Strong electromagnetic field Be noted that using the IC in the strong electromagnetic radiation can cause operation failures. 5. Thermal shutdown protection circuit Thermal shutdown protection circuit is the circuit designed to isolate the IC from thermal runaway, and not intended to protect and guarantee the IC. So, the IC the thermal shutdown protection circuit of which is once activated should not be used thereafter for any operation originally intended. 6. Inspection with the IC set to a pc board If a capacitor must be connected to the pin of lower impedance during inspection with the IC set to a pc board, the capacitor must be discharged after each process to avoid stress to the IC. For electrostatic protection, provide proper grounding to assembling processes with special care taken in handling and storage. When connecting to jigs in the inspection process, be sure to turn OFF the power supply before it is connected and removed. 7. Input to IC terminals + This is a monolithic IC with P isolation between P-substrate and each element as illustrated below. This P-layer and the N-layer of each element form a P-N junction, and various parasitic element are formed. If a resistor is joined to a transistor terminal as shown in Fig 59: ○P-N junction works as a parasitic diode if the following relationship is satisfied; GND>Terminal A (at resistor side), or GND>Terminal B (at transistor side); and ○if GND>Terminal B (at NPN transistor side), a parasitic NPN transistor is activated by N-layer of other element adjacent to the above-mentioned parasitic diode. The structure of the IC inevitably forms parasitic elements, the activation of which may cause interference among circuits, and/or malfunctions contributing to breakdown. It is therefore requested to take care not to use the device in such manner that the voltage lower than GND (at P-substrate) may be applied to the input terminal, which may result in activation of parasitic elements.
Resistance (Pin A) (Pin B) C Transistor (NPN) B E GND N P+ N N P substrate N Parasitic diode GND Parasitic diode or transistor N P substrate GND P P+ P+ N N B E GND Parasitic diode or transistor P P+ (Pin B) C GND (Pin A) Parasitic diode
Fig.59 Simplified structure of monorisic IC 8. Ground wiring pattern If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well.
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16/17
2009.05 - Rev.A
BD9102FVM, BD9104FVM, BD9106FVM
●Ordering part number
Technical Note
B
D
9
1
0
2
F
V
M
-
T
R
Part No.
Part No. 9102,9104,9106
Package FVM: MSOP8
Packaging and forming specification TR: Embossed tape and reel (MSOP8)
MSOP8
2.9±0.1 (MAX 3.25 include BURR)
8765
Tape
0.29±0.15 0.6±0.2
+6° 4° −4°
Embossed carrier tape 3000pcs TR
The direction is the 1pin of product is at the upper right when you hold
Quantity Direction of feed
4.0±0.2
2.8±0.1
( reel on the left hand and you pull out the tape on the right hand
1pin
)
1 234
1PIN MARK 0.475 S +0.05 0.22 –0.04 0.08 S 0.65
+0.05 0.145 –0.03
0.9MAX 0.75±0.05
0.08±0.05
Direction of feed
(Unit : mm)
Reel
∗ Order quantity needs to be multiple of the minimum quantity.
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17/17
2009.05 - Rev.A
Notice
Notes
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