BD9109FVM-EVK-101

ROHM Switching Regulator Solutions Evaluation Board: Synchronous Buck Converter Integrated FET BD9109FVMEVK-101 (3.3V | 0.8A Output)     No.000000000 Introduction This application note will provide the steps necessary to operate and evaluate ROHM’s synchronous buck DC/DC converter using the BD9109FVM evaluation boards. Component selection, board layout recommendations, operation procedures and application data is provided. Description This evaluation board has been developed for ROHM’s synchronous buck DC/DC converter customers evaluating BD9109FVM. While accepting a power supply of 4.5-5.5V, an output of 3.3V can be produced. The IC has internal 350mohm Pch MOSFET and 250mohm Nch MOSFET and a fixed synchronization frequency of 1 MHz. A Soft Start circuit prevents in-rush current during startup along with UVLO (low voltage error prevention circuit) and TSD (thermal shutdown detection) protection circuits. An EN pin allows for simple ON/OFF control of the IC to reduce standby current consumption. Employs a current mode control system to provide faster transient response to sudden change in load. Applications Power supply for LSI including DSP, Microcomputer and ASIC Evaluation Board Operating Limits and Absolute Maximum Ratings Parameter Limit Symbol Unit MIN TYP MAX VCC 4.5 5 5.5 V VOUT 3.234 3.300 3.366 V IOUT - - 0.8 A Conditions Supply Voltage BD9109FVM Output Voltage / Current BD9109FVM  Evaluation Board Below is evaluation board with the BD9109FVM. Fig 1: BD9109FVM Evaluation Board 1 Application Note  Evaluation Board Schematic Below is evaluation board schematic for BD9109FVM. Fig 2: BD9109FVM Evaluation Board Schematic  Evaluation Board I/O Below is reference application circuit that shows the inputs (V IN, EN) and the output (V OUT). Fig 3: BD9109FVM Evaluation Board I/O  Evaluation Board Operation Procedures Below is the procedure to operate the evaluation board. 1. Connect power supply’s GND terminal to GND test point TP4 on the evaluation board. 2. Connect power supply’s VCC terminal to VIN test point TP3 on the evaluation board. This will provide VIN to the IC U1. Please note that the VCC should be in range of 4.5V to 5.5V. 3. Check if shunt jumper of J1 is at position ON (Pin2 connect to Pin3, EN pin of IC U1 is pulled high as default). 4. Now the output voltage VOUT (+3.3V) can be measured at the test point TP1 on the evaluation board with a load attached. The load can be increased up to 0.8A MAX. Page 2 of 8 Application Note  Reference Application Data for BD9109FVMEVK-101 Following graphs show hot plugging test, quiescent current, efficiency, load response, output voltage ripple response of the BD9109FVM evaluation board. Fig 4: Hot Plug-in Test with Zener Diode Fig 5: Circuit Current vs. Power supply o SMAJ5.0A, VIN=5.5V, VOUT=3.3V, Voltage Characteristics (Temp=25 C) IOUT=0.8A Fig 6: Electric Power Conversion Rate (VOUT=3.3V) Fig 7: Load Response Characteristics (VIN=5V, VOUT=3.3V, L=4.7uH, COUT=10uF, IOUT=0A0.8A) Fig 8: Load Response Characteristics (VIN=5V, VOUT=3.3V, L=4.7uH, COUT=10uF, IOUT=0.8A0A) Fig 9: Output Voltage Ripple Response Characteristics (VIN=5V, VOUT=3.3V, L=4.7uH, COUT=10uF, IOUT=0A) Fig 10: Output Voltage Ripple Response Characteristics (VIN=5V, VOUT=3.3V, L=4.7uH, COUT=10uF, IOUT=0.8A) Page 3 of 8 Application Note  Evaluation Board Layout Guidelines Below are the guidelines that have been followed and recommended for BD9109FVM designs. Layout is a critical portion of good power supply design. There are several signals path that conduct fast changing currents or voltage that can interact with stray inductance or parasitic capacitance to generate nose or degrade the powe r supplies performance. To help eliminate these problems, the V CC pin should be bypassed to ground with a low ESR ceramic bypass capacitor with B dielectric. Fig 11: BD9109FVM Layout diagram ① ② ③ For the sections drawn with heavy line, use thick conductor pattern as short as possible. Lay out the input ceramic capacitor C IN closer to the pins PVCC and PGND, and the output capacitor C O closer to the pin PGND. Layout CITH and RITH between the pins ITH and GND as neat as possible with least necessary wiring. Fig 12: BD9109FVMEVK-101 PCB layout Page 4 of 8 Application Note  Calculation of Application Circuit Components 1. Selection of inductor (L) The inductance significantly depends on output ripple current. As seen in the equation (1), the ripple current decreases as the inductor and/or switching frequency increases. ∆𝐈𝐋 = (𝐕𝐂𝐂 −𝐕𝐎𝐔𝐓 )×𝐕𝐎𝐔𝐓 𝐋×𝐕𝐂𝐂 ×𝐟 [𝐀] (1) Appropriate ripple current at output should be 30% more or less of the maximum output current. ∆𝐈𝐋 = 𝟎. 𝟑 × 𝐈𝐎𝐔𝐓 𝐌𝐀𝐗 [𝐀] 𝐋= (𝐕𝐂𝐂 −𝐕𝐎𝐔𝐓 )×𝐕𝐎𝐔𝐓 ∆𝐈𝐋 ×𝐕𝐂𝐂 ×𝐟 (2) [𝐇] (3) (ΔIL: Output ripple current, and f: Switching frequency) Fig 13: Output ripple current * Current exceeding the current rating of the inductor results in magnetic saturation of the inductor, which decreases efficiency. The inductor must be selected allowing sufficient margin with which the peak current may not exceed its current rating. If VCC=5V, VOUT=3.3V, f=1MHz, ΔIL=0.3×0.8A=0.24A, for example 𝐋= (𝟓−𝟑.𝟑)×𝟑.𝟑 𝟎.𝟐𝟒×𝟓×𝟏𝐌 = 4.675[uH]  4.7[uH] * Select the inductor of low resistance component (such as DCR and ACR) to minimize dissipation in the inductor for better efficiency. 2. Selection of output capacitor (CO) Output capacitor should be selected with the consideration on the stability region and the equivalent series resistance required to smooth ripple voltage. Output ripple voltage is determined by the equation (4): ∆𝐕𝐎𝐔𝐓 = ∆𝐈𝐋 × 𝐄𝐒𝐑 [𝐕] (4) (ΔIL: Output ripple current, and ESR: Equivalent series resistance of output capacitor) * Rating of the capacitor should be determined allowing sufficient margin against output voltage. Less ESR allows reduction in output ripple voltage. As the output rise time must be designed to fall within the soft-start time, the capacitance of output capacitor should be determined with consideration on the requirements of equation (5) 𝐂𝐎 ≤ 𝐓𝐒𝐒 ×(𝐈𝐋𝐈𝐌𝐈𝐓 −𝐈𝐎𝐔𝐓 ) Fig 14: Output capacitor 𝐕𝐎𝐔𝐓 [𝑭] (5) (TSS: Soft-start time, ILIMIT: Over current detection level, 2A [Typ]) For instance, and if V OUT=3.3V, IOUT=0.8A, and TSS=1ms 𝐂𝐎 ≤ 𝟏𝐦×(𝟐−𝟎.𝟖) 𝟑.𝟑 = 364[uF] Inappropriate capacitance may cause problem in startup. A 10uF to 100uF ceramic capacitor is recommended. 3. Selection of input capacitor (C IN) Input capacitor to select must be a low ESR capacitor of the capacitance sufficient to cope with high ripple current to prevent high transient voltage. The ripple current IRMS is given by the equation (6): 𝐈𝐑𝐌𝐒 = 𝐈𝐎𝐔𝐓 × √𝐕𝐎𝐔𝐓 (𝐕𝐂𝐂 −𝐕𝐎𝐔𝐓 ) 𝐕𝐂𝐂 [𝐀] < Worst case > IRMS(max.) When VCC is twice the VOUT, 𝐈𝐑𝐌𝐒 = (6) 𝐈𝐎𝐔𝐓 𝟐 If VCC=5V, VOUT=3.3V, and IOUT max=0.8A, Fig 15: Input capacitor 𝐈𝐑𝐌𝐒 = 𝟎. 𝟖 × √𝟑.𝟑(𝟓−𝟑.𝟑) 𝟓 = 0.38[A] A low ESR 10uF/10V ceramic capacitor is recommended to reduce ESR dissipation of input capacitor for better efficiency. Page 5 of 8 Application Note 4. Determination of RITH, C ITH that works as a phase compensator As the Current Mode Control is designed to limit a inductor current, a pole (phase lag) appears in the low frequency area due to a CR filter consisting of a output capacitor and a load resistance, while a zero (phase lead) appears in the high frequency area due to the output capacitor and its ESR. So, the phases are easily compensated by adding a zero to the power amplifier output with C and R as described below to cancel a pole at the power amplifier. 𝐟𝐩 = 𝟏 𝟐𝛑×𝐑𝐨×𝐂𝐨 𝐟𝐳(𝐄𝐒𝐑) = Fig 16: Open loop gain characteristics 𝟏 𝟐𝛑×𝐄𝐒𝐑×𝐂𝐨 Pole at power amplifier When the output current decreases, the load resistance RO increases and the pole frequency lowers. 𝐟𝐩(𝐌𝐢𝐧. ) = 𝐟𝐩(𝐌𝐚𝐱. ) = 𝟏 𝟐𝛑×𝐑𝐨𝐦𝐚𝐱×𝐂𝐨 𝟏 𝟐𝛑×𝐑𝐨𝐦𝐢𝐧×𝐂𝐨 [Hz]  with lighter load [Hz] with heavier load Zero at power amplifier Increasing capacitance of the output capacitor lowers the pole frequency while the zero frequency does not change. (This is because when the capacitance is doubled, the capacitor ESR reduces to half.) 𝐟𝐳(𝐀𝐦𝐩) = 𝟏 𝟐𝛑×𝐑 𝐈𝐓𝐇 ×𝐂𝐈𝐓𝐇 Stable feedback loop may be achieved by canceling the pole fp (Min.) produced by the output capacitor and the load resistance with CR zero correction by the error amplifier. Fig 17: Error amp phase compensation characteristics fx(Amp) = fp(Min)  𝟏 𝟐𝛑×𝐑 𝐈𝐓𝐇 ×𝐂𝐈𝐓𝐇 = 𝟏 𝟐𝛑×𝐑𝐨𝐦𝐚𝐱×𝐂𝐨 Fig 18: Typical application Page 6 of 8 Application Note  Evaluation Board BOM Below is a table with the build of materials. Part numbers and supplier references are provided. Item Qty. Ref Description Manufacturer Part Number 1 2 C1,C2 CAP CER 10UF 25V 20% X5R 1206 Murata GRM31CR61E106MA12L 2 1 C3 CAP CER 330PF 50V 10% X7R 0603 Murata GRM188R71H331KA01D 3 1 D1 DIODE TVS 400W 6.8V UNI 5% SMD P4SMA6.8A 4 1 J1 CONN HEADER VERT .100 3POS 15AU 5 1 L1 INDUCTOR POWER 4.7UF 1.1A SMD Littelfuse TE Connectivity TDK Corporation 6 1 R1 RES 30K OHM 1/10W 1% 0603 SMD MCR03ERTF3002 7 2 TP1,TP3 TEST POINT PC MULTI PURPOSE RED 8 2 TP2,TP4 TEST POINT PC MULTI PURPOSE BLK Rohm Keystone Electronics Keystone Electronics 9 1 U1 1 ROHM TE Connectivity BD9109FVM-TR 10 IC REG BUCK SYNC 3.3V 0.8A 8MSOP Shunt jumper for header J1 (item #4), CONN SHUNT 2POS GOLD W/HANDLE 87224-3 VLF5014AT-4R7M1R1 5010 5011 881545-1 Page 7 of 8 Application Note Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. 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