BD9275F

1/4 STRUCTURE Silicon Monolithic Integrated Circuit NAME OF PRODUCT DC-AC Inverter Control IC TYPE FUNCTION ＢＤ９２７５Ｆ ・Using 20V process / 1ch control with Push-Pull ・Accuracy of drive output frequency：3.5%（IC Only/Built-in CT Capacitor） ・High accuracy timer latch current(±15%) ・Built-in FAIL function ・Adjustable latch timing ・Adjustable slow start time ・Lamp current and voltage sense feedback control ・Mode-selectable the operating or stand-by mode by STB pin (Typ.=0uA ) ○Absolute Maximum Ratings（Ta = 25℃） Parameter Supply Voltage OUTPUT PIN Voltage Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Power Dissipation *1 Symbol VCC N1, N2 Topr Tstg Tjmax Pd Limits 20 20 -40～+85 -55～+150 +150 SOP18:562* Unit V V ℃ ℃ ℃ mW Pd derate at -4.5mW/℃ for temperature above Ta = 25℃ (When mounted on a PCB 70.0mm×70.0mm×1.6mm) 〇動作範囲 項目 Supply voltage Input Frequency Ratio PWM_IN PIN DRIVER frequency 記号 範囲 単位 VCC F_PWM_IN F_OUT 8.0 ～ 18.0 0.060～0.5 20 ～ 90 V kHz kHz REV. B 2/4 ○Electric Characteristics（Ta=25℃、VCC=12V、STB=3.0V） LIMIT Item (（WHOLE DEVICE）) Operating current Stand-by current Icc1 Icc2 － － 2.0 0 4.0 20 mA μA RT=100kΩ, FB=GND, IS=1.5V VSTB=0V SYMBOL MIN. TYP. MAX. UNIT CONDITION ((STAND BY CONTROL） ） Stand-by voltage H Stand-by voltage L STB PIN pull down resistor VSTBH VSTBL RSTB 2 -0.3 180 375 VCC 0.8 750 V V kΩ System ＯＮ System ＯＦＦ VSTB=2V （ （VCC UVLO BLOCK）） ） Operating voltage Hesteresis width VCC_UVLO ⊿UVLO_HYS 7.2 0.3 7.5 0.5 7.8 0.7 V V VCC=6V→8V sweep VCC=8V→6V sweep （ （OSC BLOCK） ） RT pin Voltage SRT ON resistance VRT RSRT 1.300 － 1.500 75 1.700 150 V Ω RT=100kΩ VSRT=0.1V ((PWM Dimming Block)) PWM_IN PIN voltage H PWM_IN PIN voltage L PWM_IN PIN pull down resistor VPWMIN_H VPWMIN_L R_PWMIN 2.4 -0.3 1000 2000 5 0.8 4000 V V kΩ VPWM_IN=0V⇒3.0V VPWM_IN=3.0V⇒0V VPWM_I=5V （ （FEED BACK BLOCK） ） IS threshold voltage VS threshold voltage IS source current IS COMP detect voltage VIS VVS IIS VISCOMP 1.225 1.200 16 0.565 1.250 1.250 20 0.625 1.275 1.300 24 0.685 V V μA V IS=1.0V IS=1.3V→0.5V （ （SLOW START BLOCK） ） SS term END Voltage Soft start current VSS ISS 2.400 1.7 2.500 2.0 2.600 2.3 V μA VSS=0V⇒3V VSS=1.0V IS=1.5V （ （COMP BLOCK） ） COMP over voltage detect voltage Hysterisis width (COMP) COMP PIN pull down resistor FAIL ON resistance VCOMPH ⊿VCOMPH RCOMP RFAIL 1.900 0.100 1000 － 2.000 0.200 2000 75 2.100 0.300 4000 150 V V kΩ Ω VSS＞2.5V VCOMP=1.5V→2.5V VSS＜2.0V VCOMP=2.5V→1.5V COMP=5V VFAIL=0.1V （ （OUTPUT BLOCK） ） N1,N2 PIN output sink resistance N1,N2 PIN output source resistance MAX DUTY Drive output frequency RsinkN RsourceN MAX DUTY FOUT 1.5 4.5 45 48.25 3.0 9 47.0 50 6.0 18 49.5 51.75 Ω Ω % kHz IIN=100mA IIN=-100mA FOUT=50kHz RT=100kΩ （ （TIMER BLOCK） ） Timer Latch setting voltage Timer Latch setting current VCP ICP 2.900 1.7 3.000 2.0 3.100 2.3 V μA VCP=0V⇒3.2V CP=1.0V IS=1.5V COMP=3.0V （This product is not designed to be radiation-resistant.） REV. B 3/4 〇Package Dimensions MAX11.55 (include. BURR) MAX11.55 (include. BURR) Device Name BD9275F Lot No. SOP-16 (Unit:mm) 〇PIN No.・PIN NAME・FUNCTION BD9275F No. 1 2 PIN STB Stand-by switch Function No. 16 15 PIN N1 N2 NMOS FET driver NMOS FET driver Function VCC Supply voltage input External resistor from SRT to RT for adjusting 3 SRT the triangle oscillator External resistor from SRT to RT for adjusting 14 PGND Ground for FET drivers 4 5 6 7 8 RT the triangle oscillator 13 12 11 10 9 PWM_IN Dimming pulse signal input pin SS CP External capacitor from SS to GND for Soft Start Control External capacitor from CP to GND for Timer Latch GND GROUND FB IS VS Error amplifier output Error amplifier input Error amplifier input FAIL Error signal output pin COMP Over voltage detect pin REV. B 4/4 〇NOTE FOR USE 1. This product is produced with strict quality control, but might be destroyed if used beyond its absolute maximum ratings. Once IC is destroyed, failure mode will be difficult to determine, like short mode or open mode. Therefore, physical protection countermeasure, like fuse is recommended in case operating conditions go beyond the expected absolute maximum ratings. 2. The circuit functionality is guaranteed within of ambient temperature operation range as long as it is within recommended operating range. The standard electrical characteristic values cannot be guaranteed at other voltages in the operating ranges, however the variation will be small. 3. Mounting failures, such as misdirection or miscounts, may harm the device. 4. A strong electromagnetic field may cause the IC to malfunction. 5. The GND pin should be the location within ±0.3V compared with the PGND pin. ALL voltage should be under VCC voltage +0.3V 6. BD9275F incorporate a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is designed only to shut the IC off to prevent runaway thermal operation. It is not designed to protect the IC or guarantee its operation of the thermal shutdown circuit is assumed. 7. When modifying the external circuit components, make sure to leave an adequate margin for external components actual value and tolerance as well as dispersion of the IC. 8. About the external FET, the parasitic Capacitor may cause the gate voltage to change, when the drain voltage is switching. Make sure to leave adequate margin for this IC variation. 9. Under operating CP charge (under error mode) analog dimming and burst dimming are not operate. 10. Under operating Slow Start Control (SS is less than 2.5V), It does not operate Timer Latch. 11. By STB voltage is changed to 2 states. Therefore, do not input STB pin voltage between one state and the other state (0.8～2.0V). 12. The pin connected a connector need to connect to the resistor for electrical surge destruction. 13. This IC is a monolithic IC which (as shown is Fig-1) has P+ substrate and between the various pins. A P-N junction is formed from this P layer of each pin. For example, the relation between each potential is as follows, ○(When GND > PinB and GND > PinA, the P-N junction operates as a parasitic diode.) ○(When PinB > GND > PinA, the P-N junction operates as a parasitic transistor.) Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits as well as operation faults and physical damage. Accordingly you must not use methods by which parasitic diodes operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin. Transistor (NPN) Resistance (PinA) (PinB) B C Ｃ N E GND P＋ P N P＋ P substrate GND Parasitic diode (PinB) Ｎ P substrate GND Parasitic diode Ｎ N N (PinA) B Parasitic diode GND Ｂ CＣ EＥ GND Parasitic diode Other adjacent components Fig-1 Simplified structure of a Bipolar IC REV. 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