BD9353MWV

1/4 STRUCTURE PRODUCT SERIES TYPE PIN ASSIGNMENT BLOCK DIAGRAM PACKAGE Functions ● Silicon Monolithic Integrated Circuit 7-Channel Switching Regulator Controller for Digital Camera ＢＤ９３５３ＭＷＶ Fig.1 Fig.1 Fig.2 Power supply voltage 2.2～5.5V(at start-up), 2.05～5.5V(after start-up) ● CH1step-down converter, CH2cross converter, CH3 step-down converter, CH4 step-up converter CH5 inverting converter for CCD, CH6 boost converter for CCD, CH7 boost converter for LED ● All Internal Power MOSFETs ● Built-In MOSFETs for synchronous rectifying action mode on CH1～4 ● Built-In feedback resistors on CH2 ● All channels contain internal compensation between inputs outputs of error amps ● Contains sequence control circuit for CH1～4 ● Operating frequency 1.5MHz(CH1,3,4)､750KHz（CH2,5,6,7） ● Built-In Short-circuit Protection (SCP) ● CH6 have high side switches with soft start function ● Built-In Over voltage Protection (OVP) ● Thermally enhanced UQFN036V5050 package（5mm×5mm, 0.4mm pitch） ○Absolute maximum ratings（Ta＝25℃） Parameter Symbol VCC,Hx13,Hx2, Hx4,Hx567,VO2,HS6L STB1234,56 PWM7 Hx5 - Lx5 Lx6 Lx7,VO7 IomaxLx1 IomaxHx2 IomaxHx3 IomaxHx4,Lx4 IomaxHx5 IomaxHS6L IomaxLx6～7 Pd Topr Tstg Tjmax Limit －0.3～7 －0.3～7 －0.3～7 -0.3～15 －0.3～20 -0.3～21 ±0.8 ±1.5 ±0.8 ±2.2 ±1.5 ±1.2 ±1.2 0.88 *1 －25～+85 －55～+150 +150 Unit V V V V V V A A A A A A A W ℃ ℃ ℃ Power Input Voltage Output current P O S J ower Dissipatio perating Temperatur torage Temperatur unction Temperatur n e e e *1 Should be derated by 7.04mW/℃ at Ta=25℃ or more. When mounted on a glass epoxy PCB of 74.2mm×74.2 mm×1.6 mm ○Recommended operating conditions Parameter Power Supply Voltage (at start-up) Power Supply Voltage (after start-up) VREF Pin Connecting Catacitor VREGA Pin Connecting Capacitor PWM7 freqency 【Oscillator】 Oscillator (CH1,3,4) OSC Timing Resistor Symbol VCC1 VCC2 CVREF CVREGA fpwm fosc RT MIN 2.2 2.05 0.047 0.47 20 0.8 47 Limit TYP 0.1 1.0 1.5 62 MAX 5.5 5.5 0.47 4.7 100 1.8 120 Unit V V μF μF kHz MHz kΩ REV. A 2/4 ○Electrical characteristics（Ta=25℃, VCC=3V, RT=62kΩ, STB1～6=3V,PWM7=2.5V） Standard Value Parameter Symbol MIN TYP MAX Unit Condition Parameter 【Soft Start】 Symbol MIN Standard Value TYP MAX Unit Condition 【 Internal Regulator VREGA】 Output Voltage VREG A 2.125 2.2 2.275 V Io=5mA CH1,2,4 Soft Start time CH3 Soft Start time CH5 Soft Start time Tss1,2,4 Tss3 Tss5 Tss6 TDTC 1.5 0.5 1.8 2.5 1.3 2.5 1.5 2.8 3.5 2.6 3.5 2.5 3.8 4.5 5.2 msec msec msec msec msec RT=62kΩ RT=62kΩ RT=62kΩ RT=62kΩ L=6.4μH, Co=4.7μF LED 3pcs (※3) RT=62kΩ RT=62kΩ, STB1234=H 【Under Voltage Lockout】 VCC startup voltage Threshold VCC minimum operating voltage Vuv1 - 1.95 2.05 2.05 2.15 V V CH6 Soft Start time CH7 Soft Start time VCC=2.2V Vuv2 after Turn-On VREGA startup voltage Vuv3 Threshold VREGA minimum operating voltage Vuv4 after Turn-On 【 Short Circuit Protection】 Timer Startup Threshold Delay time for SCP 1 Delay time for SCP 2 - - 2.025 V - - 2.15 V VCC=2.2V CH1～4 Delay time for Soft Start CH 5,6 Delay time for Soft Start 【 Output Driver】 CH1 Highside resisitance SW ON Td1 Td56 9 0.23 15 0.42 21 0.61 msec msec Vtcinv Tscp Tscp4 0.42 50 7 0.48 70 10 0.54 90 13 V msec msec INV pin monitor CH4 RON1P RON1N RON21P RON21N RON22P RON22N RON3P RON3N RON4P RON4N RON5P RON6N RON67P - 300 230 120 120 150 120 300 230 150 110 600 500 200 450 350 180 180 230 180 450 350 230 170 900 800 300 mΩ mΩ mΩ mΩ mΩ mΩ mΩ mΩ mΩ mΩ mΩ mΩ mΩ Hx1=3.6V Hx1=3.6V Hx2=3.6V Hx2=3.6V, VO2=3.4V Hx2=3.6V Hx3=3.6V Hx3=3.6V Hx4=5V Hx4=5V Hx56=3.6V Hx56=3.6V Hx56=3.6V CH1～3,5～7 CH4 CH1 Lowside SW ON resistance CH2 Lx21 Highside SW ON resistance CH2 Lx21 Lowside SW ON resisitance CH2 Lx22 Highside SW ON resistance CH2 Lx22 Lowside SW ON resistance CH3 Highside SW ON resistance 【 Oscillator】 F requency CH1,3,4 R requency CH2,5,6,7 Max duty 1,3 Max duty 4 Max duty 5,6,7 Max duty CH2 Lx21 Max duty CH2 Lx22 fosc1 fosc2 Dmax1 d Dmax1 u Dmax2 Dmax3 Dmax4 1.3 0.65 86 86 86 1.5 0.75 92 92 92 1.7 0.85 100 96 96 100 96 MHz MHz % % % % % RT=62kΩ RT=62kΩ Vscp=0V (※1) CH3 Lowside SW ON resistace CH4 Highside SW ON resistace CH4 Lowside SW ON resistance CH5 PMOS SW ON resistace CH6,7 NMOS SW ON resistance 【Error AMP】 Input Bias Current INV Threshold INV7 Threshold 1 INV7 Threshold 2 INV7 Threshold 3 INV7 Threshold 4 CH6 Load SW ON resistace IINV VINV VINV7 1 VINV7 2 VINV7 3 VINV7 4 0.79 598 449 234 17 0 0.80 630 473 252 32 50 0.81 662 497 270 47 nA V mV mV mV mV INV1,3～6=3.0V CH1,3～6 PWM7 Duty=100% PWM7 Duty=75% PWM7 Duty=40% PWM7 Duty=5% 【STB1～6】 STB Control Voltage Active Non Active VSTBH1 VSTBL1 RSTB1 1.5 -0.3 250 400 5.5 0.3 700 V V kΩ STB1234, STB56 Pull Down Resistance 【PWM7】 PWM7 Control Voltage H Level L Level VPWMH VPWML RPWM 2.05 0 250 200 400 300 4.00 0.40 700 - V V kΩ μsec RT=62kΩ 【CH2 Feedback】 CH2 Output Voltage VO2S Input Current Pull Down Resistance VO2 IVO2S VOUT 5 DVLi Ios 3.332 4.7 3.4 6.7 3.46 8 8.7 V uA VO2S= 3.4V CH7 Delay time for shutdown 【LEDSW】 L ED PIN SW ON resistance Toff7 【 Reference Voltage Vref for CH5】 CH5 Output Voltage Line Regulation Output Current When shorted RLED - 2 3 Ω V CC=3.6V -6.09 0.2 -6.00 4.0 1.0 -5.91 12.5 - V mV mA INV5 1M//200kΩ, 1MΩ(※2) VCC= 2.2～5V VREF5=0V 【 OVP】 O VP Threshold 【Circuit Current】 VCC terminal Stand-by Current C ircuit Current （VCC PIN Current） V OVP7 18 19 20 V V O7 monitor ISTB1 ISTB2 ISTB3 Icc - 5.0 5 5 5 11.0 μA μA μA mA INV1-7=1.2V INV5=-0.2V VCC= 3.0V Hｘ terminal Lx terminal (※1) When circuit is operated by 100% duty at CH1 and CH3, SCP timer start. So it is possible to use only for transition time shorter than Tscp. (※2) Recommend resistor value over 20kΩ between VREF to INV5, because VREF current is under 100uA. And, Please set resistor value considered phase compensation for coil and output capacitor. (※3) Related to LED quantity , LED forward voltage and Input voltage. ◎ This product is not designed for normal operation with in a radioactive environment.. REV. A 3/4 ○PIN Assignment ・Block Diagram VREF5 VREGA INV4 INV5 GND INV1 INV3 27 26 25 24 23 22 21 20 2.5V REG OSC 19 + - INV7 29 30 + - LED VO7 31 PRE DRIVER PWM7 32 HS6L 33 HX567 34 PRE DRIVER PRE DRIVER LX5 STB56 35 PRE DRIVER PRE DRIVER PRE DRIVER PRE DRIVER 36 PGND567 PGND4 STB1234 HX13 LX7 HX4 LX6 LX4 LX1 ○Package BD9353 LOT No. 図-2 + - INV6 28 SCP RT + + + - - + - FILTER - 1.0V VREF 18 VO2S 17 VCC 16 VO2 15 LX22 OVP PWM & LOGIC BLOCK 14 PGND2 13 LX21 HX2 12 11 LX3 10 PGND13 B.G CTL 1 2 3 4 5 6 7 8 9 Fig .1 ○PIN Description 端子名 VCC GND VREGA VREF5 Hx13,2,567 Hx4 Lx1,3,4,5,6,7 Lx21 Lx22 VO2 HS6L INV1,3,4,5,6,7 VO2S RT SCP STB1234,56 PWM7 LED VO7 Ground VREGA Output CH5 Reference Output CH1～3,5,6 Pch FET Source Terminal , FET Driver Power Supply CH4 DC/DC Output Terminal for Connecting Inductor Terminal for Connecting Inductor For CH2 Input Terminal for Connecting Inductor For CH2 Output CH2 DC/DC Output Output Terminal for Internal Load Switch Error Amp Inverted Input CH2 Output Feedback Terminal Terminal for Connecting a Resister To Set the OSC Frequency SCP Timer Flag Terminal CH1～CH6 ON/OFF Control Terminal CH7 ON/OFF Control, PWM Dimming Input Terminal for connecting LED Cathode CH7 DC/DC Output 機 IC Power Supply Input 能 PGND13,2,4,567 Ground for Internal FET REV. A 4/4 ○Operation Notes １.) Absolute maximum ratings This product is produced with strict quality control. However, the IC may be destroyed if operated beyond its absolute maximum ratings. If the device is destroyed by exceeding the recommended maximum ratings, the failure mode will be difficult to determine. (E.g. short mode, open mode) Therefore, physical protection counter-measures (like fuse) should be implemented when operating conditions beyond the absolute maximum ratings anticipated. ２.) GND potential Make sure GND is connected at lowest potential. All pins except NON5, must not have voltage below GND. Also, NON5 pin must not have voltage below - 0.3V on start up. ３.) Setting of heat Make sure that power dissipation does not exceed maximum ratings. ４.) Pin short and mistake fitting Avoid placing the IC near hot part of the PCB. This may cause damage to IC. Also make sure that the output-to-output and output to GND condition will not happen because this may damage the IC. ５.) Actions in strong magnetic field Exposing the IC within a strong magnetic field area may cause malfunction. ６.) Mutual impedance Use short and wide wiring tracks for the main supply and ground to keep the mutual impedance as small as possible. Use inductor and capacitor network to keep the ripple voltage minimum. ７.) Thermal shutdown circuit (TSD circuit) The IC incorporates a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is designed only to shut the IC off to prevent runaway thermal operation. It is not designed to protect the IC or guarantee its operation. Do not continue to use the IC after operating this circuit or use the IC in an environment where the operation of this circuit is assumed. ８.) Rush current at the time of power supply injection. An IC which has plural power supplies, or CMOS IC could have momentary rush current at the time of power supply injection. Please take care about power supply coupling capacity and width of power Supply and GND pattern wiring. ９.) IC Terminal Input This IC is a monolithic IC that has a P- board and P+ isolation for the purpose of keeping distance between elements. A P-N junction is formed between the P-layer and the N-layer of each element, and various types of parasitic elements are then formed. For example, an application where a resistor and a transistor are connected to a terminal (shown in Fig.15): ○When GND > (terminal A) at the resistor and GND > (terminal B) at the transistor (NPN), the P-N junction operates as a parasitic diode. ○When GND > (terminal B) at the transistor (NPN), a parasitic NPN transistor operates as a result of the NHayers of other elements in the proximity of the aforementioned parasitic diode. Parasitic elements are structurally inevitable in the IC due to electric potential relationships. The operation of parasitic elements Induces the interference of circuit operations, causing malfunctions and possibly the destruction of the IC. Please be careful not to use the IC in a way that would cause parasitic elements to operate. For example, by applying a voltage that is lower than the GND (P-board) to the input terminal. Resistor （Terminal A） Transistor (NPN) B E （Terminal BC ） GND N （TerminalＡ） Parasitic element N GND P＋ N N P P＋ N Parasitic element Ｎ P＋ N P P-board P＋ P-board Parasitic l t GND Fig - 3 Simplified structure of a Bipolar IC REV. A ～ ～ Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). 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