TECHNICAL NOTE
System Power Supply LSIs for use in automotive electronics
Power Supply for system
With built-in for system
Communication functions
BD9401FM/BD9403FV
zDescription
The BD9401FM/BD9403FV can be combined with the BD9400BFP to create application-specific, system power supplies.
The BD9401FM features 3 built-in channels: a 1 A LDO channel, a switching regulator controller channel, and a 500 mA
high-side switch channel. The BD9403FV features one built-in switching regulator controller channel. The combination of a
switching regulator with an LDO enables the IC to deliver reduced voltage consumption.
zFeatures
1. The IC can be combined with the BD9400BFP, providing design flexibility.
2. Broad input voltage range: 7 V to 36 V
3. Built-in 1 A variable LDO (BD9401FM)
4. Output voltage accuracy of ± 2% (BD9401FM LDO)
5. Built-in 500 mA high-side switch (BD9401FM)
6. Built-in open collector type PWM controller channel for design flexibility
7. Maximum frequency: 500 kHz
8. Built-in short protection circuit (SCP)
9. Built-in thermal shutdown circuit
10. HSOP-M28/SSOP-B14 package
zApplications
Car audio, satellite navigation systems, etc.
zAbsolute maximum ratings (Ta = 25°C)
Parameter
Symbol
Limit
Unit
Power supply voltage 1
VCC
36*1
V
Power supply voltage 2
VLDOVcc
12*1
V
Power supply voltage 3
VREG, VREF
7
V
PWM output current
IoMAX
100
mA
Power dissipation 1 (HSOPM28)
P01
1.8*2
W
*3
Power dissipation 2 (HSOPM28)
P02
2.2
W
Power dissipation 3 (SSOPB14)
P03
0.35*4
W
Power dissipation 4 (SSOPB14)
P04
0.4*5
W
Operating temperature range
TOPR
-40 to +85
°C
Storage temperature range
TSTG
+150
°C
Maximum junction temperature
TJMAX
+150
°C
*1 Not to exceed Pd.
*2 Reduced by 14.4 mW/°C over 25°C during IC without heat sink operation.
*3 Reduced by 17.6 mW/°C over 25°C, when mounted on a glass epoxy board (70 mm × 70 mm × 1.6 mm).
*4 Reduced by 2.8 mW/°C over 25°C during IC without heat sink operation.
*5 Reduced by 3.2 mW/°C over 25°C, when mounted on a glass epoxy board (70 mm × 70 mm × 1.6 mm).
Ver.B Oct.2005
zRecommended operating ranges (Ta = 25°C) (Not to exceed Pd.)
Parameter
Symbol
Min.
Max.
Unit
Power supply voltage 1
VCC
8
26
V
Power supply voltage 2
VLDOVcc
3
11
V
Oscillating frequency
FOSC
30
500
KHz
zElectrical characteristics 1:BD9401FM (Unless otherwise specified, Ta = 25°C; VCC = 13.5 V; VREF = 3.0 V; VREG = 5.0 V)
Parameter
Symbol
Limit
Min.
Typ.
Max.
Unit
Conditions
[Total supply current]
ICC
—
200
400
µA
PWMCTL = HSDCTL = 2 V, Io = 0 mA
Total supply current VREG
IVREG
—
0.68
—
mA
VREG = 5.0 V
Total supply current VREF
IVREF
—
0.96
—
mA
VREF = 3.0 V
ISTBY
—
1
10
µA
VREF = VREG = PWMCTL = HSDCTL = 0 V
—
3.3
—
V
Io = 10 mA
NF voltage
VNF
1.225
1.250
1.275
V
Output maximum current
IPEAK
1.0
—
—
A
Line regulation
∆VOLI
—
10
20
mV
VLDOVcc = 5 V to 11 V
Load regulation
∆VOLO
—
50
100
mV
Io = 0 mA to 800 mA
Minimum I/O voltage
∆VOLDO
—
0.5
1.0
V
Io = 800 mA
R.R.
50
60
—
dB
Io = 10 mA, VIN = 0.1 Vp.p
VDH
—
0.5
1.0
V
Io = 500 mA
IPEAKH
0.5
—
—
A
Total supply current VCC
Total supply current during
standby operation
[Variable LDO regulator: 1 A]
Output voltage
difference
Ripple rejection
[High-side switch: 500 mA]
Dropout voltage
Output maximum current
[High-side switch control pin]
Off voltage input range
VHSDOFF
0
—
1.0
V
On voltage input range
VHSDON
2.0
—
VREF
V
INV pin threshold voltage
VINV
1.225
1.250
1.275
V
VFB = 3.0 V
INV pin input current
IBIAS
-1
—
1
uA
VINV = 0 V
AV
—
60
—
dB
Max. output voltage
VFBM
2.0
2.4
2.8
V
VINV = 2.0 V
Min. output voltage
VFBL
—
—
0.1
V
VINV = 2.0 V
Output sinking current
IFBSI
1
2.5
4
mA
VFB = 3 V, VINV = 0 V
Output source current
IFBSO
50
100
200
uA
VFB = 0 V, VINV = 2 V
[Error amp]
DC voltage gain
[PWM comparator]
0% duty cycle
VTH0D
0.90
1.00
1.10
V
FB voltage, OSCIN = 1.0 V
VTH100D
1.80
2.00
2.20
V
FB voltage, OSCIN = 2.0 V
VSINV
0.8
0.9
1.0
V
Voltage when SCP is off
VSSCP
—
50
100
mV
Threshold voltage 1
VT1SCP
0.85
1.05
1.2
V
Threshold voltage 2
VT2SCP
1.80
2.00
2.2
V
SCP voltage, PWM: OFF
ISCP
1.5
2.5
4.0
µA
VSCP = 0 V
100% duty cycle
[Short protection circuit (SCP)]
INV pin short detection
voltage
SCP pin source current
INV voltage
SCP voltage
SCP voltage, SCD, OUT: HIGH
[Undervoltage protection circuit (UVLO)]
Threshold voltage
VUVLO
—
5.70
—
V
Vcc = 13.5 V→5 V
Hysteresis voltage
VHYS
—
0.07
—
V
Vcc = 5 V→13.5 V ∆VUVLO
2/16
zElectrical Characteristics 2:BD9401FM (Unless otherwise specified, Ta = 25°C, Vcc = 13.5 V, STDY = 3.3 V, VREF = 3.0 V,
VREG = 5.0 V)
Parameter
Symbol
Limit
Min.
Typ.
Max.
Unit
Conditions
[PWM driver output block]
Output saturation voltage
VSAT
—
0.8
1.4
V
Io = 75 mA, VFB = 3.0 V
VDOFF
—
—
10
uA
VPWMOUT = 30 V, VPNMCTL = 0 V
Off voltage input range
VPNMOFF
0
—
1.0
V
On voltage input range
VPWMON
2.0
—
VREF
V
Output current when DWM is off
[Switching regulator control pin]
[SCD (short protection detection) signal output pin]
SCD low output voltage
VSCPL
0.0
—
1.0
V
VSCP = 0 V
SCD high output voltage
VSCOH
2.0
—
VREF
V
VSCP = 2 V
zElectrical Characteristics 3:BD9403FV (Unless otherwise specified, Ta = 25°C, Vcc = 13.5 V, STDY = 3.3 V, VREF = 3.0 V,
VREG = 5.0 V)
Min.
Limit
Typ.
Max.
IVREG
IVREF
—
—
—
200
0.68
0.96
400
—
—
µA
mA
ｍA
Io = 10 mA
VREG = 5.0 V
VREF = 3.0 V
ISTBY
—
1
10
µA
VREF = VREG = PWMCTL = 0 V
VINV
IBIAS
AV
VFBM
VFBL
IFBSI
IFBSO
1.225
-1
—
2.0
—
1
50
1.250
—
60
2.4
—
2.5
100
1.275
1
—
2.8
0.1
4
200
V
uA
dB
V
V
mA
uA
VFB = 3.0 V
VINV = 0 V
VTH0D
VTH100D
0.90
1.80
1.00
2.00
1.10
2.20
V
V
VSINV
VSSCP
0.8
—
0.9
50
1.0
100
V
mV
VT1SCP
0.85
1.05
1.2
V
Threshold voltage 2
VT2SCP
1.80
SCP pin source current
ISCP
1.5
[Undervoltage protection circuit (UVLO)]
Threshold voltage
VUVLO
—
Hysteresis voltage
VHYS
—
[PWM driver output block]
Output saturation voltage
VSAT
—
Output current when DWM is off
VOFF
—
[Switching regulator control pin]
Off voltage input range
VPWMOFF
0
On voltage input range
VPWMON
2.0
[CD (short protection detection) signal output pin]
SCD low output voltage
VSCDL
0.0
SCD high output voltage
VSCDH
2.0
2.00
2.5
2.2
4.0
V
µA
INV voltage
SCP voltage
SCP voltage, SCD,
OUT: HIGH
SCP voltage, PWM OFF
VSCP = 0 V
5.70
0.07
—
—
V
V
Vcc = 13.5 V→5 V
Vcc = 5 V→13.5 V ∆VdVLO
1.0
—
2.0
20
V
uA
Io = 75 mA
VPWMOUT = 30 V, VPWMCTL = 0 V
—
—
1.0
VREF
V
V
—
—
1.0
VREF
V
V
Parameter
[Total supply current]
Total supply current VCC
Total supply current VREG
Total supply current VREF
Total supply current during
standby operation
[Error amp]
INV pin threshold voltage
INV pin input current
DC voltage gain
Maximum output voltage
Minimum output voltage
Output sinking current
Output source current
[PWM comparator]
0% duty cycle
100% duty cycle
[Short protection circuit (SCP)]
INV pin short detection voltage
Voltage when SCP is off
Threshold voltage 1
Symbol
ICC
3/16
Unit
Conditions
VINV = 2.0 V
VINV = 2.0 V
VFB = 3 V, VINV = 0 V
VFB = 0 V, VINV = 2 V
FB voltage, OSCIN = 1.0 V
FB voltage, OSCIN = 2.0 V
VSCP = 0 V
VSCP = 2 V
zReference Data (Unless otherwise specified, Ta = 25°C, Vcc = 13.5 V, VLDOVCC = 5 V, VREF = 3.0 V, VREG = 5.0 V)
2
1.5
1
0.5
400
300
200
100
0
5
10
15
20
25
30
1
0.8
0.6
0.4
0.2
2
4
6
8
10
0
12
Fig.2 VLDOVcc Total Supply Current
（BD9401FM）
0.8
0.6
0.4
0.2
500
400
300
200
100
0
1
2
3
4
5
0.6
0.4
0.2
0
0
INPUT VOLTAGE ： VREG [V]
5
10
15
20
25
30
35
0
40
Fig.5 Total Supply Current
When CTL Is Off
(BD9401FM)
Fig.4 VREG Total Supply Current
(BD9401FM)
2
1.2
1
0.8
0.6
0.4
0.2
1
0.8
0.6
0.4
0.2
0
0
1
2
3
0
4
1
2
3
4
5
1
0
0
2
4
6
8
10
INPUT VOLTAGE ： VLDOVCC [V]
Fig.10 LDO Input Stability (2)
(When VOUT setting = 3.3 V;
Io = 200 mA)
12
40
1
0
3
2
1
0
0
0.5
1
1.5
2
2.5
OUTPUT CURRENT ： ILDOvcc [A]
Fig.11 LDO Load Stability
(When VOUT setting = 3.3 V)
4/16
2
4
6
8
10
12
INPUT VOLTAGE ： VLDOVCC [V]
Fig.9 LDO Input Stability (1)
(Io = 0 mA)
DROPOUT VOLTAGE ： VLDROPOUT[V]
OUTPUT VOLTAGE ： VLDO[V]
2
35
2
6
4
3
30
3
Fig.8 VREG Total Supply Current
(BD9403FV)
4
25
4
INPUT VOLTAGE ： VREG [V]
5
20
0
0
INPUT VOLTAGE ： VREF [V]
Fig.7 VREF Total Supply Current
(BD9403FV)
15
5
OUTPUT VOLTAGE ： VLDOO [V]
INPUT CURRENT ： I_VREG[mA]
1.4
10
Fig.6 VCC Total Supply Current
(BD9403FV)
1.2
1.6
5
INPUT VOLTAGE ： VCC [V]
INPUT VOLTAGE ： VCC [V]
1.8
4
0.8
0
6
3
1
INPUT CURRENT ： ICC[mA]
INPUT CURRENT ： ISTBY[µA]
1
2
Fig.3 VREF Total Supply Current
(BD9401FM)
600
1.2
0
1
OUTPUT VOLTAGE:Vref [V]
INPUT VOLTAGE：VLDOVCC [V]
INPUT VOLTAGE：VCC [V]
INPUT CURRENT ： I_VREG[mA]
1.2
0
0
35
Fig.1 VCC Total Supply Current
(BD9401FM)
INPUT CURRENT ： I_VREF [mA]
1.4
0
0
OUTPUT VOLTAGE ： VLDOO[V]
1.6
OUTPUT:CURRENT:IREF[mA]
INPUT CURRENT ： ILDOVCC[µA]
INPUT CURRENT ： ICC [mA]
1.8
500
2.5
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0
0.2
0.4
0.6
0.8
1
1.2
OUTPUT CURRENT ： ILDO [A]
Fig.12 LDO I/O Voltage Differential
3.4
3.3
3.2
OUTPUT VOLTAGE:VHSDSW[V]
80
RIPPLE REJECTION:RR[dB]
OUTPUT VOLTAGE:VLDOUT [V]
2
90
3.5
70
60
50
40
30
20
10
0
-10
-40 -30 -20 -10 0
10
10 20 30 40 50 60 70 80
100
1000
10000
0
100000
0
25
15
10
5
20
5
10
15
20
15
10
5
5
10
15
20
8
6
4
2
0
40
30
20
10
0
2.5
2
1.5
1
0.5
-10
-20
100
1000
10000
0
Frequency：f [Hz]
Fig.19 ERRAMP Frequency
100
4
80
DUTY:DUTY[%]
5
0.5
1
1.5
2
100
2.5
0
0.5
1
1.5
2
2.5
3
OUTPUT VOLTAGE:VPWMOUT [V]
Fig.21 PWM Output Current
VOUT
60
40
SCP
20
0
1.4
200
Fig.20 Error Amp I/O
(VINV vs VFB)
1
1.2
300
INPUT VOLTAGE:VINV [V]
2
1
0
100000
3
0.8
400
0
10
0.6
500
OUTPT CURRENT:IPWMOUT[mA]
OUTPUT VOLTAGE:VFB[V]
50
0.4
Fig.18 High-Side Switch Load Current
3
60
0.2
OUTPUT CURRENT:IHSDSW [A]
80
70
35
10
25
Fig.17 High-Side Switch I/O
(OutputVCCLoad:
50 Ω)
[V]
90
30
12
INPUT VOLTAGE:VCC [V]
INPUT VOLTAGE:VCC [V]
Fig.16 High-Side Switch I/O
(Output Load: ∞)
25
0
0
25
20
14
0
0
15
16
OUTPUT VOLTAGE:VHSDSW[V
OUTPUTVOLTAGE:VHSDSW[V]
20
10
Fig.15 High-Side Switch
Output When Off
25
0
5
INPUT VOLTAGE:VCC [V]
Fig.14 LDO Ripple Rejection
Fig.13 LDO Output Voltage
vs Temperature
OUTPUT VOLTAGE:VHSDSW[V
0.5
Frequency:f[Hz]
TEMPERATURE:Ta [℃]
Gain：G[dB]
1
-20
3.1
OUTPUT CURRENT:I_PWMLeak[µA]
1.5
SCPOUT
0
0
5
10
15
20
25
30
INPUT VOLTAGE:VCC [V]
Fig.22 Leak When PWM
Output Is Off
35
1
1.2
1.4
1.6
1.8
2
INPUT VOLTAGE:VFB [V]
Fig.23 PWM Output FB vs Duty
5/16
0
1
2
3
4
5
Time:t[msec]
6
7
8
Fig.24 Short Protection Timer
zBlock Diagram (BD9401FM)
VCC
zPin function descriptions (BD9401FM)
UVLO
THD
VREF
GROUND
OSCIN
SCDOUT
DTC
SCP
Err AMP.
FB
OSCIN
PWM
COMP.
PNP DRIVER
PWMCTL
PWMOUT
VCC
GND
PWMGND
HSDVCC
HSDSW
LDOVCC
N.C
VREG
PMWOUT
PWMGND
RICTL
LDOVCC
VTGATE
LDOOUT
NF
HSDCTL
FB
DTC
SCP
VREF
VREG
INV
SCD_OUT
PWMCTL
INV
HIGH-SIDE
HSD VCC
SWITCH CTL
HSD SW
N.C
HSDCTL
N.C
N.C
N.C
NF
RICTL
VTGATE
N.C
N.C
LDOOUT
Fig.26 BD9401FM Pin Function Descriptions
Fig.25 BD9401FM Block Diagram
zPin Descriptions (BD9401FM)
Pin No.
Pin name
1
OSCIN
2
SCDOUT
3
SCP
4
VREF
5
VREG
6
VCC
7
GND
8
HSDVCC
9
HSDSW
10
N.C.
11
HSDCTL
12
N.C.
13
N.C.
14
N.C.
15
LDOOUT
16
N.C.
17
N.C.
18
VTGATE
19
RICTL
20
NF
21
LDOVCC
22
N.C.
23
PWMGND
24
PWMOUT
25
DTC
26
FB
27
INV
28
PWMCTL
FIN
FIN
Function
Triangular waveform input pin
Output short detection signal output pin (to BD9400BFP)
Output short detection delay time setting capacitor connection pin
Reference input VREF (3.0 V) input pin
Reference input VREF (5.0 V) input pin
Power supply input pin
Ground pin
High-side switch power supply input pin
High-side switch output pin
NC pin
High-side switch On/off control pin
NC pin
NC pin
NC pin
LDO regulator output pin
NC pin
NC pin
LDO regulator output PMOS gate pin
LDO regulator overcurrent protection adjustment resistance connection pin (connect to GND when not using)
LDO regulator output voltage setting resistance connection pin (reset input)
LDO regulator power supply input pin
NC pin
PWM ground
PWM output pin
Dead time control pin
Error amp output pin
Error amp inverted input pin
DC/DC control
On/off switching pin
Heat dissipation fin; connect to ground.
6/16
zBlock Diagram (BD9403FV)
VCC
UVLO
THD
VREF
0
GROUND
DTC
SCP
DISCHARGE
1.25V
Err AMP.
INV
SCD_OUT
FB
2.0V
1.0V
OSCIN
PWM
VREG
OFF
PNP
PMWOUT
PWMCTL
PWMGND
Fig.27 BD9403FV Block Diagram
zPin assignment diagram (BD9403FV)
PWMGND
GND
PWMOUT
DTC
N.C
VCC
FB
INV
PWMCTL
VREG
OSCIN
VREF
SCDOUT
SCP
Fig.28 BD9403FV Pin Assignment Diagram
zPin function descriptions (BD9403FV)
Pin No.
Pin name
1
PWMGND
2
PWMOUT
3
DTC
4
FB
5
INV
6
OSCIN
7
SCDOUT
8
SCP
9
VREF
10
VREG
11
PWMCTL
12
VCC
13
N.C
14
GND
Function
PWM ground
PMW output pin
Dead time control pin
Error amp output pin
Error amp inverted input pin
Triangular waveform input pin
Output short detection signal output pin (to BD9400BFP)
Output short detection delay time setting capacitor connection pin
Reference input VREF (3.0 V) input pin
Reference input VREF (5.0 V) input pin
DC/DC control
On/off switching pin
Power supply input pin
NC pin
Ground pin
7/16
zApplication example
1μF
VCC
VREF
GROUND
100pF
CT
56kΩ
RT
0.033μF
DELAY
RESET
BD9400BFP
SYNC+
SYNCSYBY
100kΩ
3.3V 250mA
VOUT
10
μF
100kΩ
STATUS_FLAG
（MASTER）
SDA
VREG
SCL
DC/DC CTL2
10μF
HSD CTL2
DGND
SCP2
DC/DC
DC/DC CTL3
HSD CTL1
HSD CTL3
SCP1
0.1μF
SCP3
VCC
VREF
GND
VREG
SCP
SCDOUT
BD9401FM
PWMCTL
OSCIN
SLAVE
PWMOUT
LDOOUT
HSDSW
50Ω
0.033μF
25kΩ
33μH
200Ω
75kΩ
220
μF
10μF
NF
10μF
20kΩ
100Ω
220ｐF
LDOVcc
RICTL
HSDVCC
HSD_1
INV
FB
HSDCTL
10kΩ
1μF
DTC
DC/DC1
30kΩ
LDO1
30kΩ
10kΩ
1μF
0.1μF
BD9401FM
50Ω
0.033μF
75kΩ
220
μF
10μF
HSD_2
25kΩ
33μH
200Ω
SLAVE
20kΩ
100Ω
220ｐF
DC/DC2
30kΩ
10μF
LDO2
30kΩ
1μF
0.1μF
BD9401FM
220ｐF
25kΩ
50Ω
200Ω
SLAVE
20kΩ
100Ω
0.033μF
33μH
220
μF
HSD_3
30kΩ
10μF
LDO3
10μF
Fig.29 Application Example
8/16
50kΩ
10kΩ
35kΩ
DC/DC3
zBlock operation descriptions
•LDO block
The LDO block consists of an output-stage PMOS 1 A LDO with variable output voltage.
The feedback voltage pin carries 1.25 V at a precision of ± 2%. The input LDO voltage range is 3 V to 11 V. This range is
independent of Vcc and assumes the connection of DC/DC output.
•High-side switch block
The high-side switch block consists of a high-side switch with a current capacity of 500 mA.
The HSD CTL pin provides on/off control.
The block incorporates a built-in overcurrent protection circuit.
•Error amp block
The error amp block connects the output feedback voltage to the INV pin. The reference voltage is connected internally to
the inverted input pin. The switching duty is controlled with output feedback to control the output voltage. Phase
compensation can be performed by connecting a capacitor or resistor between the INV and FB pins.
•PNM comparator
The triangular waveform from the BD9400BFP is input to the OSCIN pin. This triangular waveform and the FB voltage are
used to output a switching pulse to create the duty. A capacitor can be connected to the DTC pin to set the Soft-start.
•PNP driver
The duty output by the PWM comparator drives the output NPN open collector. The PNP base current can be set by
connecting a resistor to the PWM output.
•SCP block
The SCP block detects DC/DC converter output shorts and latches all output off after the set delay time elapses. The circuit
is cleared by setting DC/DC CTL from low to high. Detection is performed using the INV pin, and the timer starts when the
pin reaches 0.9 V. BD9401FM/BD9403FV short detection consists of 2 mode settings, with the short detection signal being
output to SCD-OUT after 1/2 the timer latch delay time. The timer time can be set with the capacitor connected to the SCP
pin.
•UVLO block
The IC incorporates a built-in UVLO (undervoltage lockout) circuit to prevent J output malfunctions, during periods of low
Vcc input. When Vcc falls to 5.7 V or lower, this circuit operates and turns off PWM output. When Vcc rises above the 5.7 V
hysteresis voltage (0.70 mA TYP), output is reset.
zTiming chart (DC/DC controller)
1) At startup
VIN
DCDC CTL
FB
OSCIN
DTC
PWMOUT
Fig.30 Timing Chart At Startup Time
9/16
2) During short protection
VINV
0.9 V
2.0 V
1.0 V
SCP
SCD OUT
PWMOUT
PMWCTL
DTC
Fig.31 Timing Chart During Short Protection
zSelecting application components
Block name
LDO
output voltage
DC/DC
output voltage
Setting procedure
VOUT = ((R1 + R2)/R2) × VNF
(VNF = 1.25 V)
Use a ceramic capacitor with a
capacitance of 1 µF or higher for
the output capacitor.
An electrolytic capacitor may also be
used. Use a capacitance value of
1,000 µF or lower.
Calculation example
VOUT = 1.8 V
VOUT
(R1 + R2)/R2 = VNF
R1 = 0.439 × R2
R2 = 20 kΩ
R1 = 8.70 kΩ
VOUT = ((R1 + R2)/R2) × VINV
(VINV = 1.25 V)
VOUT = 3.3 V
VOUT
(R1 + R2)/R2 = VINV
R1 = 1.64 × R2
R2 = 10 kΩ
R1 = 16.4 kΩ
10/16
= 1.439 V
LDOOUT
VOUT
R1
NF
R2
=2.64 V
VINV
R2
R1
VOUT
zSelecting application components
Block name
MAX DUTY (DTC)
Setting procedure
VDTC = (R2/ (R1 + R2)) × VREF
Max DUTY =
(VDTC - VDD)/(VD100 - VDO) × 100 [%]
(VREF = 3.0 V, VD0 = 1.0 V,
VD100 = 2.0 V) (typ.)
Calculation example
R2 = 20 kΩ, R1 = 10 kΩ
VOTL = 2.0 V
Max DUTY =
(1.0/1.1) × 100 = 90.9%
VREF
R1
VDTC
R1
C
Soft start
(DTC)
Short protection
circuit
(SLP)
VFB =
(VOUT/VIN) × (VD100 - VDD) + VDO
t
))
VDTC = VREF × (1 - exp (CR
VFB = VDTC
t = -C × R × IN (1 - VFB/VREF)
(VREF = 3.0 V, VD100 = 2.1 V,
VD0 = 1.0 V)
C = 10 µF1 R1 = 10 kΩ
VOUT = 3.3 V, Vcc= 13.5 V
t = 55 ms
T1 = (CSCP × VSCP1) /ISCP
(ISCP = 2.5 µA, VSCP1 = 1 V,
VSCP2 = 2 V)
t1 = 50 ms
t2 = 100 ms
CCSCP = 0.125 µF
VDTC
VFB
VOUT
t
VSCP2
VSCP
VSCP1
SCPOUT
2
( to I CBUS)
VOUT
t1
t2
zSetting phase compensation
1. Application stability conditions
The following conditions are required in order to ensure the stability of the negative feedback circuit.
Because DC/DC converter applications use a switching frequency, the overall gain (BW) should be set to 1/10th the
switching frequency or lower. The target application characteristics can be summarized as follows:
•Phase lag should not exceed 150° at gain 1 (0 dB). (A minimum phase margin of 30°)
•BW (frequency with gain of 0 dB) should not exceed 1/10th the switching frequency.
Because the response is determined by the GBW limitation, it is necessary to use higher switching frequencies for quick
response.
One way to maintain stability through phase compensation involves canceling the secondary phase lag (-180°) caused by
LC resonance with a secondary phase advance (by inserting 2 phase advances).
Because the GMB is determined by the phase compensation capacitor, attached between the error amp output and INV
input, capacitance must be increased in order to lower the GBW.
11/16
(1) Standard integrator (low-pass filter)
(2) Integrator's open loop characteristics
(a)
A
C
Gain
[dB]
Feedback
R
-20 dB/decade
FB
A
GBW (b)
0
+
1
Phase 0
[ ]
-90°C
-90
Phase margin
-180°C
-180
1
1
At point (a), fa =
(Hz)
2πRCA
Fig. 32
At point (b), fbGWB =
Fig. 33
1
(Hz)
2πRC
The error amp performs phase compensation of types (1) and (2), making it act as a low-pass filter.
For DC/DC converter applications, R refers to feedback resistors connected in parallel.
2. When the output capacitor is an electrolytic capacitor or other capacitor with a large ESR
When the output capacitor's ESR is large (> 1 Ω), phase compensation is reasonably simple. Because LC resonant circuits
always exist in the output of DC/DC converter applications, the phase lag for those circuits is -180°. However, when an ESR
component is present, a +90° phase advance occurs, reducing the phase lag to -90°. This is an extremely effective way of
keeping the phase lag to within 150°C. However, it has the disadvantage of increasing the ripple component of the output
voltage.
(1) LC resonant circuit
(2) With ESR
Vcc
Vcc
L
L
Vo
Vo
RESR
C
C
Resonance point and phase lag of -180° at
1
fr =
2π
Fig. 35
1
Resonance point at fr = 2 π
1
[Hz]
LC
(Hz)
LC
Phase advance at Fesr = 2 π
Fig. 34
R ESR C
(Hz)
Phase lag = -90°
One phase advance should be inserted due to variations in phase characteristics caused by ESR. This phase advance can
be accomplished by either of the following methods:
(3) Insert C1 into the feedback resistors
Vo
(4) Insert R3 into the integrator
Vo
R1
R3
R1
INV
A
C2
FB
INV
R2
A
R2
Fig. 36
Phase advance fz =
FB
1
2 ππC1R
(Hz)
Fig. 37
Phase advance fz =
1
2 ππC2R
(Hz)
To cancel LC resonance, set the phase advance frequency to the LC resonant frequency. This setting has been obtained in a
simple fashion and does not reflect a rigorous calculation, so adjustment may be required for the actual implementation.
These characteristics vary with board layout, load conditions, and other factors. They should be confirmed in the actual
implementation during the mass production design process.
12/16
zI/O Equivalent circuits
1. OSCIN
2. SCDOUT
VREG
3. SCP
VREF
VREF
Vcc
VCC
VCC
9. HSDSW
Vcc
HSDVcc
Vcc
HSDVcc
11. 28. HSDCTL
PWMCTL
15. LDOOUT
VREF
Vcc
SCP
18. VTGATE
LDOVcc
LDOVcc
19. RICTL
LDOVcc
20. NF
VREG
VCC
LDOVCC
10k
LDOOG
25. DTC
24. PWMOUT
26. FB
VCC
VREG
VCC
VREG
27. INV
Vcc
VREF
1k
Fig.38 I/O Equivalent Circuits
13/16
VCC
VREG
VREF
zOperation Notes
1. Absolute maximum ratings
Use of the IC in excess of absolute maximum ratings, such as the applied voltage or operating temperature range
(Topr), may result in IC damage. Assumptions should not be made regarding the state of the IC (short mode or open
mode) when such damage is suffered. A physical safety measure, such as a fuse, should be implemented when using
the IC at times where the absolute maximum ratings may be exceeded.
2.
GND potential
Ensure a minimum GND pin potential in all operating conditions. Make sure that no pins are at a voltage below the
GND at any time, regardless of whether it is a transient signal or not.
3.
Thermal design
Perform thermal design, in which there are adequate margins, by taking into account the permissible dissipation (Pd)
in actual states of use.
4.
Short circuit between terminals and erroneous mounting
Pay attention to the assembly direction of the ICs. Wrong mounting direction or shorts between terminals, GND, or other
components on the circuits, can damage the IC.
5.
Operation in strong electromagnetic field
Using the ICs in a strong electromagnetic field can cause operation malfunction.
6. Testing on application boards
When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to
stress. Always discharge capacitors after each process or step. Always turn the IC's power supply off before
connecting it to, or removing it from a jig or fixture, during the inspection process. Ground the IC during assembly
steps as an antistatic measure. Use similar precaution when transporting and storing the IC.
7. Regarding input pin of the IC (Fig. 40)
+
This monolithic IC contains P isolation and P substrate layers between adjacent elements to keep them isolated.
P–N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic
diode or transistor. For example, the relation between each potential is as follows:
When GND > Pin A and GND > Pin B, the P–N junction operates as a parasitic diode.
When Pin B > GND > Pin A, the P–N junction operates as a parasitic transistor.
Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Accordingly, methods by which parasitic diodes
operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin, should not be
used.
8.
Ground wiring patterns
The power supply and ground lines must be as short and thick as possible to reduce line impedance. Fluctuating
voltage on the power ground line may damage the device.
9. Thermal Shutdown Circuit (TSD)
The IC incorporates a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is
designed only to shut the IC off to prevent runaway thermal operation. It is not designed to protect the IC or guarantee
its operation. Do not continue to use the IC after operating this circuit or use the IC in an environment where the
operation of this circuit is assumed.
10. Over current protection circuit
The IC incorporates a built-in overcurrent protection circuit that operates according to the output current capacity. This
circuit serves to protect the IC from damage when the load is shorted. The protection circuit is designed to limit
current flow by not latching in the event of a large and instantaneous current flow originating from a large capacitor or
other component. These protection circuits are effective in preventing damage due to sudden and unexpected
accidents. However, the IC should not be used in applications characterized by the continuous operation or
transitioning of the protection circuits. At the time of thermal designing, keep in mind that the current capability has
negative characteristics to temperatures.
14/16
11. When the Vcc pin is opposite in voltage to each pin in the application, the internal circuit or element may be damaged.
For example, such damage might occur when VCC is shorted with the GND pin while an external capacitor is charged.
Use the output pin capacity with a maximum capacitance of 1000 µF. It is recommended to insert a diode in order to
prevent back current flow in series with VCC or bypass diodes between VCC and each pin.
抵抗
Resistor
Transistor (NPN)
トランジスタ(NPN)
B
（端子
（Pin B）
B） C
C
B
～
～
Diode for preventing back current flow
(Pin B)
E
～
～
（端子A）
A）
（Pin
～
～
Bypass diode
GND
VCC
N
P
P＋
N
N
Parasitic
elements
P 基板
P＋
Parasitic elements or
Transistor
N
Ｎ
N
Output pin
GND
Ｐ
P
P＋
N
Ｎ
N
(Pin A)
～
～
P＋
P substrate
P 基板
寄生素子
GND
E
Parasitic elements
GND
GND
Fig. 39 Bypass diode
Fig. 40 Example of Simple Bipolar IC Architecture
[W]
[W]
2.5
2.2 W (1)
1.8 W (2)
2.0
0.5
(1) 70 mm × 70 mm × 1.6 mm PCB
(Glass epoxy resin)
(2) Without heat sink
θJ-A = 36.76°C/W
0.4
1.5
0.3
1.0
0.2
0.5
0.1
0
0
25
50
75
100
0
Ambient Temperature [Ta]
125
0
150
[°C ]
(1) 70 mm × 70 mm × 1.6 mm PCB
(Glass epoxy resin)
(2) Without heat sink
θJ-A = 36.76°C/W
0.4 W (1)
0.35 W (2)
0
25
50
75
100
0
Ambient Temperature [Ta]
15/16
125
150
[°C ]
zSelecting a model name when ordering
B D
9 4 0 1
F M
Part number
ROHM
model name
E 2
Packaging
FM: HSOP-M28
(BD9401FN)
FV: SSOP-B14
(BD9403FV)
Packaging specifications
E2: Emboss taping
(BD9403FV)
No: Tube container
(BD9401FM)
HSOP-M28
Embossed carrier tape
Tape
18.5 ± 0.2
0.5 ± 0.2
9.9 ± 0.3
15
7.5 ± 0.2
28
0.8
14
E2
(The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand)
0.25 ± 0.1
1234
1234
1234
Direction of feed
1Pin
Reel
(Unit:mm)
1234
0.1 S
1234
0.35 ± 0.1
0.08 M
16.0 ± 0.2
1234
0.11
5.15 ± 0.1
1500pcs
Direction
of feed
1234
2.2 ± 0.1
1
Quantity
※When you order , please order in times the amount of package quantity.
SSOP-B14
8
1
7
0.3Min.
14
Quantity
2500pcs
Direction
of feed
E2
(The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand)
0.15 ± 0.1
1234
1234
1234
1pin
1234
1234
（Unit:mm)
Reel
1234
0.1
0.22 ± 0.1
1234
0.65
Embossed carrier tape
1234
1.15 ± 0.1
0.1
6.4 ± 0.3
4.4 ± 0.2
5.0 ± 0.2
Tape
Direction of feed
※When you order , please order in times the amount of package quantity.
Catalog No.05T388Be '05.10 ROHM C 1000 TSU
Appendix
Notes
No technical content pages of this document may be reproduced in any form or transmitted by any
means without prior permission of ROHM CO.,LTD.
The contents described herein are subject to change without notice. The specifications for the
product described in this document are for reference only. Upon actual use, therefore, please request
that specifications to be separately delivered.
Application circuit diagrams and circuit constants contained herein are shown as examples of standard
use and operation. Please pay careful attention to the peripheral conditions when designing circuits
and deciding upon circuit constants in the set.
Any data, including, but not limited to application circuit diagrams information, described herein
are intended only as illustrations of such devices and not as the specifications for such devices. ROHM
CO.,LTD. disclaims any warranty that any use of such devices shall be free from infringement of any
third party's intellectual property rights or other proprietary rights, and further, assumes no liability of
whatsoever nature in the event of any such infringement, or arising from or connected with or related
to the use of such devices.
Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or
otherwise dispose of the same, no express or implied right or license to practice or commercially
exploit any intellectual property rights or other proprietary rights owned or controlled by
ROHM CO., LTD. is granted to any such buyer.
Products listed in this document are no antiradiation design.
The products listed in this document are designed to be used with ordinary electronic equipment or devices
(such as audio visual equipment, office-automation equipment, communications devices, electrical
appliances and electronic toys).
Should you intend to use these products with equipment or devices which require an extremely high level
of reliability and the malfunction of which would directly endanger human life (such as medical
instruments, transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers
and other safety devices), please be sure to consult with our sales representative in advance.
It is our top priority to supply products with the utmost quality and reliability. However, there is always a chance
of failure due to unexpected factors. Therefore, please take into account the derating characteristics and allow
for sufficient safety features, such as extra margin, anti-flammability, and fail-safe measures when designing in
order to prevent possible accidents that may result in bodily harm or fire caused by component failure. ROHM
cannot be held responsible for any damages arising from the use of the products under conditions out of the
range of the specifications or due to non-compliance with the NOTES specified in this catalog.
Thank you for your accessing to ROHM product informations.
More detail product informations and catalogs are available, please contact your nearest sales office.
ROHM Customer Support System
www.rohm.com
Copyright © 2008 ROHM CO.,LTD.
THE AMERICAS / EUROPE / ASIA / JAPAN
Contact us : webmaster@ rohm.co. jp
21 Saiin Mizosaki-cho, Ukyo-ku, Kyoto 615-8585, Japan
TEL : +81-75-311-2121
FAX : +81-75-315-0172
Appendix1-Rev2.0
工商网监
湘ICP备2023018690号
