Datasheet
7.5V to 15V, 2A Integrated MOSFET
1ch Synchronous Buck DC/DC Converter
BD95821MUV
●Description
BD95821MUV is a 1ch synchronous buck converter that
can generate output voltage (0.8V to 5.5V) at the input
voltage range (7.5V to 15V). Space-saving and high
efficient switching regulator can be achieved due to
built-in N-MOSFET power transistors. The IC also
3
TM
incorporates H Reg technology, a Rohm proprietary
constant ON TIME control mode which facilitates
ultra-high transient response against changes in load
without external compensation components. Fixed soft
start function, power good function, and short circuit /
over voltage protection with timer latch functions are
incorporated. The BD95821MUV is designed for power
supplies for Digital AV Equipment.
●Features
・Input Voltage Range:
7.5V to 15.0V
・Reference Voltage:
0.8V±1.5%
・Output Voltage Range:
0.8V to 5.5V
・Output Current:
2.0A (Max.)
・Switching Frequency:
500kHz to 800kHz
（depend on input-output condition）
・Built-in Power MOS FET
High-side Nch FET ON resistance:
120mΩ(typ.)
Low-side Nch FET ON resistance:
65mΩ(typ.)
3
・Fast Transient Responses due to H Reg control
・Over Current Protection (OCP) – Cycle-by-Cycle
・Thermal Shut Down (TSD)
・Under-Voltage Lock-Out (UVLO)
・Short Circuit Protection (SCP)
・Over Voltage Protection (OVP)
・Fixed Soft Start (1msec ; typ)
・Power Good function
●Applications
・LCD TVs
・Set Top Boxes (STB)
・DVD/Blu-ray players/recorders
・Broadband Network and Communication Interface
・Amusement, other.
W(Typ.) x D(Typ.) x H(Max.)
3.0mm x 3.0mm x 1.0mm
●Package
・VQFN016V3030
●Pin Configuration (TOP VIEW)
●Typical Application
GND
GND
VREG
11
VOUT
PGOOD
EN
12
11
10
9
GND 13
9
10
FB
EN
EN
VOUT
FB
12
GND
PGOOD
PGOOD
13
8
BOOT
14
7
SW
15
6
SW
16
5
SW
8
BOOT
VREG 14
7 SW
TEST 15
6
SW
VIN 16
5
SW
Thermal Pad
TEST
2
3
4
PGND
Figure 2 .Pin Configuration
Figure 1. Typical Application Circuit
○Product structure：Silicon monolithic integrated circuit
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1
PGND
VOUT
4
VIN
3
PGND
2
VIN
1
PGND
VIN
VIN
VIN
VIN
GND
○This product is not designed protection against radioactive rays.
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Datasheet
BD95821MUV
●Block Diagram
Figure 3. Block Diagram
●Pin Description
No.
Symbol
Description
1, 2, 16
VIN
Input Voltage Supply pin.
The IC determines the duty cycles internally based on the input voltage. Therefore, variations of
VIN pin can lead to unstable operation. This pin also acts as the input voltage to the internal
switching regulator output block, and is sensitive to the impedance of the power supply.
Connect over 10F ceramic capacitors for the decoupling capacitors to PGND as near as these
pins.
3, 4
PGND
5, 6, 7
SW
8
BOOT
9
EN
Enable Input pin.
When the input voltage of the EN pin reaches at least 2.2V, the switching regulator becomes
active. At the voltage less than 0.3 V, the IC becomes standby mode.
10
PGOOD
Open-drain Power Good Output pin.
Due to the open-drain output, a 100kΩ pull-up resistor should be connected between this pin and
VREG or other power supply. In the case of no use, this pin is opened or shortened to ground.
Power ground pin connected to the source of the Low side FET.
Switch node connection between High side FET source and Low side FET drain.
Connect 0.01F capacitor between BOOT and SW. This pin is also connected to inductor (L).
High side FET Gate Driver Power Supply pin.
Connect 0.01F capacitor between BOOT and SW.
BOOT voltage swings from VREG to (VIN + VREG) during normal switching operation.
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BD95821MUV
●Pin Description (Continued)
No.
Symbol
Description
11
VOUT
12
FB
13
GND
14
VREG
Power supply output inside IC. When at least 2.2V is supplied to the EN pin, the VREG is active.
This pin supplies 5.0V at up to 10mA. Insert a 0.022F capacitor between this pin and ground
pin.
15
TEST
TEST Pin. Connect to ground.
Thermal
Pad
-
Output Voltage Sense pin.
Connect to output voltage directly. ONTIME is determined by monitoring the output voltage.
Output Voltage Feedback pin. FB is compared with REF in the IC. Please set the output voltage
in the feedback resistances of less than total 50kΩ. (Refer to page 15)
Sense ground pin for all internal analog and digital power supplies.
Exposed Thermal Pad. Connect to ground.
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BD95821MUV
●Absolute Maximum Ratings (Ta=25℃)
Parameter
Symbol
Limit
Input Voltage
VIN
15.2 *1
V
BOOT Voltage
BOOT
21.5 *1
V
BOOT-SW
7 *1
V
VOUT
7 *1
V
SW Voltage
SW
15.2 *1
V
Output Feedback Voltage
FB
VREG
V
VREG
7 *1
V
EN Input Voltage
EN
15.2 *1
V
PGOOD Voltage
PGOOD
7 *1
V
Power Dissipation 1
Pd1
0.27
W
Power Dissipation 2
Pd2
0.62
W
Power Dissipation 3
Pd3
1.77
W
Power Dissipation 4
Pd4
2.66
W
Operating Temperature Range
Topr
-20 to +100 *1
℃
Storage Temperature Range
Tstg
-55 to +150
℃
Tjmax
+150
℃
BOOT-SW Voltage
Output Voltage
VREG Voltage
Junction Temperature
*1
Comment
Unit
Ta≧25°C (IC only), power dissipated at
2.2mW / °C.
Ta≧25°C (70mm×70mm×1.6mm single-layer
board, 6.28mm2 copper heat dissipation pad),
power dissipated at 5.0mW / °C.
Ta≧25°C (70mm×70mm×1.6mm 4-layer
board, 6.28 mm2 copper heat dissipation pad
on top and bottom layer, 5505 mm2 pad on 2nd
and 3rd layer), power dissipated at 14.1mW
/ °C.
Ta≧25°C (70mm×70mm×1.6mm 4-layer
board, all layers with 5505 mm2 copper heat
dissipation pads), power dissipated at
21.3mW / °C.
Not to exceed Pd.
●Operating Ratings (Ta= -20 to 100℃)
Parameter
Symbol
Limit
Unit
Min
Typ
Max
VIN
7.5
12
15
V
VREG Voltage
VREG
4.5
5.0
5.5
V
BOOT Voltage
BOOT
4.5
-
21
V
SW
-0.7
-
15
V
BOOT-SW
4.5
-
5.5
V
EN
0
-
15
V
Output Voltage
VOUT *2
0.8
-
5.5
V
PGOOD Voltage
PGOOD
0
-
5.5
V
Minimum ON Time
Tonmin
-
-
200
nsec
Input Voltage
SW Voltage
BOOT-SW Voltage
EN Input Voltage
*2 VOUT depends on Input Voltage (VIN) in some cases.
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BD95821MUV
●Electrical Characteristics
(Unless otherwise noted Ta=25℃, VIN=12V, EN=3V, VOUT=3.3V)
Parameter
Symbol
Limit
Unit
Condition
Min
Typ
Max
IIN
-
1.2
2.0
mA
IIN_STB
-
2
15
A
EN Low Voltage
ENLOW
GND
-
0.3
V
EN High Voltage
ENHIGH
2.2
-
15
V
EN Bias Current
IEN
-
3
10
A
EN=3V
VREG_STB
-
-
0.1
V
EN=0V
VREG Output Voltage
VREG
4.5
5.0
5.5
V
IREG=10mA
Maximum Output Current
IREG
10
-
-
mA
High side FET ON Resistance
RONH
-
120
240
mΩ
Low side FET ON Resistance
RONL
-
65
130
mΩ
FB threshold Voltage
VFB
0.788
0.800
0.812
V
FB Input Current
IFB
-1
-
1
A
TON
-
470
-
nsec
TOFFMIN
200
450
-
nsec
Soft Start Time
TSOFT
-
1.0
-
msec
VOUT Discharge Current
IVOUT
3
6.6
-
mA
VIN Bias Current
VIN Standby Current
EN=0V
Enable Control
VREG Output Voltage
VREG Standby Voltage
Power MOSFET
Reference Voltage
H3Reg Control
ON Time
Minimum OFF Time
Soft Start / Output Discharge
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BD95821MUV
●Electrical Characteristics (Continued)
(Unless otherwise noted Ta=25℃, VIN=12V, EN=3V, VOUT=3.3V)
Parameter
Symbol
Limit
Unit
Condition
Min
Typ
Max
IOCP
2.5
3.5
6.0
A
*3
SCP Threshold Voltage
VSCP
0.48
0.56
0.64
V
VFB=0.8V → 0V
SCP delay time
TSCP
-
1.0
-
msec
OVP Threshold Voltage
VOVP
0.86
0.96
1.06
V
OVP delay time
TOVP
-
1.0
-
msec
VREG Threshold Voltage
VREG_UVLO
3.75
4.20
4.65
V
VREG Hysteresis Voltage
dVREG_UVLO
100
160
220
mV
VFB Power Good Low Voltage
VFB_PL
0.61
0.68
0.75
V
VFB=0.8V → 0V
VFB Power Good High Voltage
VFB_PH
0.65
0.72
0.79
V
VFB=0V → 0.8V
Over Current Protection
Over Current Protection
Current Limit
SCP
OVP
VFB=0.8V → 2.0V
UVLO
VREG: Sweep up
VREG: Sweep down
Power Good
＊3
No tested on outgoing inspection.
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BD95821MUV
●Typical Performance Curves (Unless otherwise noted
Ta=25℃, VIN=12V)
100
60
90
50
80
VOUT = 3.3V
60
40
VOUT = 5.0V
Tc [℃]
Efficiency [%]
70
50
VOUT = 1.2V
40
30
20
30
20
10
10
0
0
0
0.5
1
1.5
2
0
1
Iout [A]
Iout [A]
Figure 4. Efficiency
(VIN=12V, L=3.3H)
Figure 5. Tc – Iout
(VIN=12V, VOUT=3.3V, L=3.3H)
VOUT
(AC)
20mV/div
VOUT
(AC)
20mV/div
SW
5V/div
SW
5V/div
1sec/div
1sec/div
Figure 6. VOUT Ripple voltage
(VIN=12V, VOUT=3.3V, L=3.3H, COUT=44F, Iout=0A)
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Figure 7. VOUT Ripple voltage
(VIN=12V, VOUT=3.3V, L=3.3H, COUT=44F, Iout=2A)
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Datasheet
BD95821MUV
Ta=25℃, VIN=12V) (Continued)
3.45
3.45
3.40
3.40
3.35
3.35
VOUT [V]
VOUT [V]
●Typical Performance Curves (Unless otherwise noted
3.30
3.30
3.25
3.25
3.20
3.20
3.15
3.15
0
1
Iout=0A
Iout=2A
7
2
9
11
13
Iout [A]
VIN[V]
Figure 8. VOUT Load Regulation
(VIN=12V, VOUT=3.3V, L=3.3H)
Figure 9. VOUT Line Regulation
(VOUT=3.3V, L=3.3H, Iout=0A / 2A)
15
800
3.45
750
Frequency [kHz]
VOUT [V]
3.40
3.35
700
650
600
3.30
550
500
3.25
-20
0
20
40
60
80
7
100
9
11
13
Temperature [℃]
VIN [V]
Figure 10. VOUT - Temperature
(VIN=12V, VOUT=3.3V, L=3.3H, Iout=0A)
Figure 11. Frequency - VIN
(VIN=12V, VOUT=3.3V, L=3.3H, Iout=0A)
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BD95821MUV
●Typical Performance Curves (Unless otherwise noted
Ta=25℃, VIN=12V) (Continued)
EN
5V/div
EN
5V/div
SW
10V/div
SW
10V/div
VOUT
2V/div
VOUT
2V/div
PGOOD
5V/div
PGOOD
5V/div
200sec/div
10msec/div
Figure 13. Power down with EN
(VIN=12V, VOUT=3.3V, L=3.3H, COUT=44F, Iout=0A)
Figure 12. Start up with EN
(VIN=12V, VOUT=3.3V, L=3.3H, COUT=44F, Iout=0A)
VOUT
2V/div
VOUT (AC)
50mV/div
SW
20V/div
Iout
2A/div
IL
2A/div
100sec/div
Figure 15. OCP function
(VIN=12V, VOUT=3.3V, L=3.3H, COUT=44F)
(VOUT is shorted to ground)
Figure 14. VOUT Transient Response
(VIN=12V, VOUT=3.3V, L=3.3H, COUT=44F)
Iout=0⇔2A (SR=1.0A/sec)
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BD95821MUV
●Explanation of Operation
The BD95821MUV is a 1ch synchronous buck converter incorporating ROHM’s proprietary H3RegTM CONTROLLA system.
When VOUT drops due to a rapid load change, the system quickly restores VOUT by increasing the frequency.
1. H3RegTM System
1-1. Normal Operation
When FB falls below the threshold voltage (REF), a drop is detected, activating the H3RegTM CONTROLLA system.
Ton
V OUT
1
V IN
f
[sec]
(1)
HG (Gate of High side MOSFET) output is determined by the formula (1). LG (Gate of Low side MOSFET) output operates
until FB voltage falls below REF voltage after HG becomes OFF. OFF time is restricted by MIN OFF Time (typ.:450nsec).
Hence, BD95821MUV runs with a constant on-time by using the input and output voltage to set the internal on-time timer.
1-2. VOUT drops due to a rapid load change
When FB (VOUT) drops due to a rapid load change and the voltage remains below REF, the system quickly restores
VOUT by shortening OFF time of HG (increasing the frequency), improving transient response as shown Figure 16 (b).
FB
FB
REF
REF
HG
Io
LG
HG
LG
(a) Normal operation
(b) Rapid load change
Figure 16. H3REG System
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BD95821MUV
●Timing Chart
1. Soft Start Function
Soft start is utilized when the EN pin is set high. Current control takes effect at startup, enabling a moderate “ramping start”
on the output voltage. Soft start time is 1.0msec (typ). Rush current is determined via formula (2) below.
I IN
C OUT V OUT
1.0msec
[A]
(2)
COUT: All capacitors connected with VOUT
EN
1.0msec (typ)
FB
VOUT
IIN
Figure 17. Soft Start Timing Chart
2. Power Good Function
When FB voltage is more than 0.72V (90%), the integrated open-drain NMOS is set to OFF, and PGOOD outputs High due
to pull-up register. If FB voltage falls below 0.68V (85%), PGOOD becomes Low.
EN
0.72V
0.68V
FB
PGOOD
Figure 18. Power Good Timing Chart
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BD95821MUV
●Protection Operation
1. OCP Operation
Normally, when FB voltage falls below REF voltage, HG becomes high. However, if the current through the inductor (IL)
exceeds OCP current value (IOCP) during LG=ON, HG does not become high and IL is restricted by IOCP. When IL falls down
below IOCP, HG is stricken by the pulse width of Ton decided by formula (1). As the result, the output voltage can decrease
as the frequency and duty are changed.
When OCP is released in the state that the output has decreased by OCP operation, the output voltage might rise up due
to high-speed load response. Also OFF Latch is operated when FB voltage becomes below the SCP setting voltage during
1msec (typ.) (Refer to 2-1).
Figure 19. OCP Timing Chart
2. SCP Operation / OVP Operation (OFF Latch)
2-1. SCP Operation
SCP monitors FB voltage. When FB falls below 0.56V, after 1msec (typ.) later, the short circuit protection (SCP) operates,
turning the high side MOSFET and low side MOSFET OFF, and performs OFF latch operation.
2-2. OVP Operation
OVP monitors FB voltage. When FB exceeds 0.96V, after 1msec (typ.) later, the output over voltage protection (OVP)
operates, turning the high side FET OFF and the low side FET ON, and performs OFF latch operation.
2-3. Recovery from OFF Latch mode
Off latch is released by EN=OFF or UVLO operation, and then it returns to standard operation.
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BD95821MUV
Figure 20. SCP Timing Chart
FB > REF, HG=L
HG
LG=H
LG
0.96V
FB
1msec(typ)
SS
VREG
EN
Latch Release
by EN or UVLO
Normal Operation
OVP
OFF Latch
Normal Operation
Stand by
Figure 21. OVP Timing Chart
3. TSD Operation (Self Recovery)
TSD is self-activating. If the junction temperature exceeds Tj = 175℃, and HG, LG, PGOOD, and SS become Low.
The IC becomes standby when TSD operating.
When Tj falls below 150℃, it returns to standard operation.
4. UVLO Operation
UVLO operates when VREG voltage falls below 4.05V, ad HG, LG, PGOOD and SS become Low.
The IC becomes standby when UVLO operating.
UVLO is released when VREG goes up to 4.2V, and starts standard operation
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BD95821MUV
●Selection of Components Externally Connected
1. Output LC Filter Selection (Buck Converter)
1-1. Inductor (L) Selection
The Output LC filter is required to supply constant current to the output load. A larger value inductance at this filter results
in less inductor ripple current (∆IL) and less output ripple voltage. However, the larger value inductors tend to have less
fast load transient-response, a larger physical size, a lower saturation current and higher series resistance. A smaller
value inductance has almost opposite characteristics above.
The recommended inductor values are shown in Table 1(Refer to page 18).
The value of ΔIL is shown as formula (3).
ΔI L
V IN
V OUT V OUT
L f V IN
[A]
(3)
For example, with VIN = 12 V, VOUT = 3.3 V, L = 3.3H and the switching frequency f = 600 kHz, the calculated ripple
current ⊿IL is 1.2A.
Then, the inductor saturation current must be larger than the sum of the maximum output current (IOUTMAX) and 1/2 of
the inductor ripple current (∆IL / 2). A larger current than the inductor’s saturation current will cause magnetic saturation in
the inductor, and decrease efficiency. When selecting an inductor, be sure to allow enough margins to assure that peak
current does not exceed the inductor’s saturation current value.
※To minimize loss of inductor and improve efficiency, choose a inductor with a low resistance (DCR, ACR).
VIN
HG
I
Inductor saturation current > IOUTMAX +⊿IL /2
IL
⊿IL
VOUT
SW
L
Average inductor current
(Output Current：IOUT)
t
COUT
LG
Figure 22. Inductor Ripple Current
1-2. Output Capacitor (COUT) Selection
Output Capacitor (COUT) has a considerable influence on output voltage regulation due to a rapid load change and
smoothing output ripple voltage. Determine the capacitor by considering the value of capacity, the equivalent series
resistance, and equivalent series inductance. Also, make sure the capacitor’s voltage rating is high enough for the set
output voltage (including ripple).
Output ripple voltage is determined as in formula (4) below.
ΔVOUT=ΔIL/(8×COUT×f)+ESR×ΔIL +ESL×ΔIL / Ton
[V]
(4)
(ΔIL Output ripple current、ESR: Equivalent series resistance、ESL: Equivalent series inductance)
Also, give consideration to the conditions in formula (5) below for output capacitance, bearing in mind that output rise
time must be established within the fixed soft start time. As output capacitance, bypass capacitor will be also connected
to output load side (CEXT, Figure 23). Please set the over current detection value with regards to these capacitance.
C OUT
1msec I OCP I OUT
V OUT
[F]
(5)
(IOCP : OCP Current Limit, IOUT : Output Current)
Note: an improper output capacitor may cause startup malfunctions.
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BD95821MUV
VIN
HG
VOUT
SW
L
ESR
LG
Load
CEXT
ESL
COUT
Figure 23. Output Capacitor
2. Input Capacitor (CIN) Selection
In order to prevent transient spikes in voltage, the input capacitor should have a low
enough ESR resistance to fully support a large ripple current. The formula for ripple
current IRMS is given in equation (6) as below.
VIN
CIN
HG
VOUT
SW
L
VOUT (VIN VOUT )
IRMS IOUT
COUT
LG
[A]
VIN
Where VIN =2×VOUT, IRMS=
(6)
IOUT
2
A low ESR capacitor is recommended to reduce ESR loss and improve efficiency.
Figure 24. Input Capacitor
3. Output Voltage Setting
The IC controls output voltage as REF≒VFB.
However, the actual output voltage will also reflect the average ripple voltage value.
The output voltage is set with a resistor divider from the output node to the FB pin. The formula for output voltage is given
in (7) below:
Output Voltage =
R1+R2
R2
× REF +ΔVOUT
REF = VFB(TYP 0.8V) + 0.02 – (ON DUTY × 0.05)
ON DUTY =
[V]
(7)
[V]
(8)
VOUT
(9)
VIN
Please refer to eq. (4) regarding ΔVOUT.
VIN
REF
H3RegTM
CONTROLLA
R
Output Voltage
VOUT
Q
Driver
Circuit
S
VFB
R1
R2
Figure 25. Output Voltage Setting
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BD95821MUV
4. Relationship between Output Voltage and ONTIME
BD95821MUV is a synchronous buck converter controlling constant ONTIME. The ONTIME (Ton) depends on the output
voltage settings, as described by the formula (10).
Ton 1770
VOUT 610
55
VIN
VIN
[nsec]
(10)
The frequency of the application condition is determined by the formula (11) using the above Ton.
Frequency =
VOUT
1
[kHz]
(11)
VIN
Ton
However with actual applications, there exists a rising and falling time of the SW due to the gate capacitance of the
integrated MOSFET and the switching speed, which may vary the above parameters. Therefore please also verify those
parameters experimentally.
×
5. Relationship between Output Current and Frequency
BD95821MUV is a constant ontime type of switching regulator. When the output current increases, the switching loss of
the inductor, MOSFET, and output capacitor also increases. Hence the switching frequency speeds up.
The loss of the inductor, MOSFET, and output capacitor is determined as below.
① Loss of Inductor = IOUT2 × DCR
VOUT
VIN
VOUT
× (1 VIN
② Loss of MOSFET (High Side) = IOUT2 × RONH ×
③ Loss of MOSFET (Low Side) = IOUT2 × RONL
)
④ Loss of Output Capacitor = IOUT2 × ESR
(DCR : Inductor Equivalent series resistance、RONH : On resistance of High-side MOSFET、RONL : On resistance of Low-side MOSFET、
ESR :COUT Equivalent series resistance)
Taking the above losses into the frequency equation, then T (=1/Freq) becomes
T (=1/Freq) =
VIN × IOUT × Ton
VOUT × IOUT + ① + ② + ③ + ④
[nsec]
(12)
However since the parasitic resistance of the PCB layout pattern exists in actual applications and affects the parameter,
please also verify experimentally.
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Datasheet
BD95821MUV
●PCB Layout Guide
Two high pulsing current flowing loops exist in the buck regulator system.
The first loop, when FET is ON, starts from the input capacitors, to the VIN terminal, to the SW terminal, to the inductor, to
the output capacitors, and then returns to the input capacitor through GND.
The second loop, when FET is OFF, starts from the low FET, to the inductor, to the output capacitor, and then returns to the
low FET through GND.
To reduce the noise and improve the efficiency, please minimize these two loop area.
Especially input capacitor and output capacitor should be connected to GND (PGND) plain.
PCB Layout may affect the thermal performance, noise and efficiency greatly. So please take extra care when designing
PCB Layout patterns.
L
VIN
CIN
FET
VOUT
COUT
Figure 26. Current loop Buck regulator system
・The thermal Pad on the back side of IC has the great thermal conduction to the chip. So using the GND plain as broad and
wide as possible can help thermal dissipation. And a lot of thermal via for helping the spread of heat to the different layer is
also effective.
・The input capacitors should be connected to PGND as close as possible to the VIN terminal.
・The inductor and the output capacitors should be placed close to SW pin as much as possible.
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BD95821MUV
●List of Evaluation Board Components
VREG
PGOOD
R1
EN
100kΩ
R4
R3
1.5kΩ 13kΩ
GND
C6 VREG_C
GND
VREG
9
10
8
BOOT
7
SW
15
6
SW
16
5
SW
13
14
Thermal Pad
(Shorted to GND)
0.022μF
TEST
11
EN
VOUT
FB
12
GND
PGOOD
4.7kΩ
R2
C5
BOOT_C
0.01μF
GND
L1
PGND
3
VOUT
3.3V
3.3µ H
4
C3
COUT
PGND
10µ F
2
VIN
10µ F
C2
CIN
VIN
C1
CIN
1
PGND
VIN
VIN
12V
C4
COUT
22µ F
PGND
PGND
22µ F
PGND
PGND
Figure 27. Typical Application Circuit (VOUT=3.3V)
Table 1. Recommended BOM List(VIN=12V)
Symbol
Part
Value
L1
Coil
※
CIN (C1, C2)
Ceramic capacitor
Manufacture
Series
TOKO
FDVC0630 Series
TDK
SPM6530 Series
10F / 25V
Murata
GRM31CR71E16KA12
COUT (C3, C4)
Ceramic capacitor
22F / 16V
Murata
GRM31CB31C226ME15
BOOT_C (C5)
Ceramic capacitor
0.01F / 50V
Murata
GRM18 Series
R1
Resistance
100kΩ
Rohm
MCR03 Series
R2
Resistance
※
Rohm
MCR03 Series
R3
Resistance
※
Rohm
MCR03 Series
R4
Resistance
※
Rohm
MCR03 Series
VREG_C (C6)
Ceramic capacitor
0.022F / 50V
Murata
GRM18 Series
※
VOUT
1.0V
1.2V
1.8V
3.3V
5.0V
R2
360Ω
2kΩ
5.6kΩ
13kΩ
24kΩ
R3
130Ω
220Ω
110Ω
1.5kΩ
680Ω
R4
2.2kΩ
4.7kΩ
4.7kΩ
4.7kΩ
4.7kΩ
L1
1.5H
1.5H
2.2H
3.3H
3.3H
The above components list is an example. Please check actual circuit characteristics on the application carefully before use.
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Datasheet
BD95821MUV
●I/O Equivalence circuit
VIN
SW
BOOT
BOOT
VIN
VIN
BOOT
SW
SW
SW
VREG
EN
PGOOD
EN
PGOOD
VREG
VOUT
VOUT
167k
833k
FB
VREG
V IN
FB
BOOT
VREG
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Datasheet
BD95821MUV
●Operational Notes
(1) Absolute Maximum Ratings
Use of the IC in excess of absolute maximum ratings may result in damage to the IC. Assumptions should not be made
regarding the state of the IC (e.g., short mode or open mode) when such damage is suffered. If operational values are
expected to exceed the maximum ratings for the device, consider adding protective circuitry (such as fuses) to eliminate
the risk of damaging the IC.
(2) GND voltage
The potential of the GND, PGND pin must be the minimum potential in the system in all operating conditions.
(3) Thermal design
Use a thermal design that allows for a sufficient margin for power dissipation (Pd) under actual operating conditions
(4) Inter-pin Shorts and Mounting Errors
Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result
in damage to the IC. Shorts between output pins or between output pins and the power supply and GND pins caused by
poor soldering or foreign objects may result in damage to the IC.
(5) Operation in Strong Electromagnetic Fields
Using this product in strong electromagnetic fields may cause IC malfunction. Caution should be exercised in
applications where strong electromagnetic fields may be present.
(6) ASO (Area of Safe Operation)
When using the IC, ensure that operating conditions do not exceed absolute maximum ratings or ASO of the output
transistors.
(7) Testing on application boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance pin may subject the IC
to stress. Always discharge capacitors completely after each process or step. The IC’s power supply should always be
turned off completely before connecting or removing it from a jig or fixture during the evaluation process. To prevent
damage from static discharge, ground the IC during assembly and use similar precautions during transport and storage.
(8) Electrical Characteristics
The electrical characteristics indicated in this datasheet may change upon the conditions of temperature, supply voltage,
and external components. Please validate/verify your design at the worst case conditions.
(9) Not of a radiation-resistant design.
(10) Back Electromotive Force
If a large inductive load is connected at the output pin that might cause introducing back electromotive force at the start
up and at the output disable, please insert protection diodes.
OUTPUT
PIN
Figure 28. Back Electromotive Force
(11) Regarding input pins of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated.
PN junctions are formed at the intersection of these P layers with the N layers of other elements, creating parasitic
diodes and/or transistors. For example (refer to the figure below):､
• When GND > Pin A and GND > Pin B, the PN junction operates as a parasitic diode
• When GND > Pin B, the PN junction operates as a parasitic transistor
Parasitic diodes occur inevitably in the structure of the IC, and the operation of these parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Accordingly, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be
avoided.
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Datasheet
BD95821MUV
Resistor
Transistor (NPN)
Pin B
Pin A
C
Pin B
B
E
Pin A
P
N
P
+
P+ N
N
N
Parasitic
element
P+
N
P substrate
Parasitic element
B
P
P
+
N
C
E
Parasitic
element
P substrate
GND
Parasitic element
GND
GND
Other adjacent
elements
GND
Figure 29. Example of IC structure
(12) Ground Wiring Pattern
When using both small-signal and large-current GND traces, the two ground traces should be routed separately but
connected to a single ground potential within the application in order to avoid variations in the small-signal ground
caused by large currents. Also ensure that the GND traces of external components do not cause variations on GND
voltage.
(13) Operating Condition
The electrical characteristics indicated in this datasheet are not guaranteed for the whole operational and temperature
ranges, however these characteristics do not significantly fluctuate within the operational and temperature ranges.
(14) Thermal shutdown (TSD) circuit
The IC incorporates a built-in thermal shutdown circuit, which is designed to turn the IC off completely in the event of
thermal overload. It is not designed to protect the IC from damage or guarantee its operation. ICs should not be used
after this function has activated, or in applications where the operation of this circuit is assumed. If the thermal
shutdown is activated while the load current exists, the output may possibly be latched off at the release of the thermal
shutdown.
TSD ON Temp.[℃]
175
(typ.)
Hysteresis Temp[℃]
25
(typ.)
(15) Heat Sink (FIN)
The heat sink (FIN) is connected to the substrate. Please connect it to GND.
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Datasheet
BD95821MUV
●Thermal Derating Curves
(1) 4 layer board
2
(All layers with 5505 mm copper heat dissipation pads)
θj-a=47.0℃/W
(2) 4 layer board
2
(6.28 mm copper heat dissipation pad on top and bottom layer,
2
nd
rd
5505 mm pad on 2 and 3 layer)
θj-a=70.62℃/W
2
(3) 1 layer board (6.28 mm copper heat dissipation pad)
θj-a=201.6℃/W
Figure 30. Thermal derating curve
(VQFN016V3030)
●Ordering Information
B
D
9
5
8
2
1
Part Number
M
U
V
-
E2
Package
MUV: VQFN016V3030
Packaging and forming specification
E2: Embossed tape and reel
●Physical Dimension Tape and Reel Information
VQFN016V3030
3.0±0.1
3.0±0.1
0.5
5
13
8
0.75
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
4
16
12
E2
9
1.4±0.1
0.4±0.1
1
3000pcs
(0.22)
1.4±0.1
+0.03
0.02 −0.02
1.0MAX
S
C0.2
Embossed carrier tape
Quantity
Direction
of feed
1PIN MARK
0.08 S
Tape
+0.05
0.25 −0.04
1pin
(Unit : mm)
Reel
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
●Marking Diagram
VQFN016V3030 (TOP VIEW)
Part Number Marking
D95
LOT Number
8 2 1
1PIN MARK
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Datasheet
BD95821MUV
●Revision History
Date
Revision
Changes
6.Aug.2012
001
New Release
24.Aug.2012
002
Revised the General Description
18.Mar.2013
003
Revised the General Description
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(Note 1)
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Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any
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(Note1) Medical Equipment Classification of the Specific Applications
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7.
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8.
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Precaution for Mounting / Circuit board design
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For details, please refer to ROHM Mounting specification
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2.
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[d] the Products are exposed to high Electrostatic
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Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
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