BD95830MUV

1/4 STRUCTURE TYPE PRODUCT SERIES FEATURES Silicon Monolithic Integrated Circuit 2ch DC/DC converter IC BD95830MUV 3 ・Built in 2ch H Reg DC/DC converter controller ・Adjustable output voltage setting (0.8V～5.5V) ○Absolute Maximum Ratings (Ta=25℃) Parameter Input Voltage BOOT Voltage BOOT-SW Voltage Output Voltage Output Feedback Voltage VREG Voltage VCC Voltage Logic Input Voltage Power Dissipation 1 Power Dissipation 2 Power Dissipation 3 Power Dissipation 4 Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Symbol VIN1, VIN2, VINS BOOT1,BOOT2 Limit 15.1 21.1 *1*2 *1*2 Unit V V V V V V V V W W W W ℃ ℃ ℃ BOOT1-SW1, BOOT2-SW2 VOUT1, VOUT2 FB1, FB2 VREG VCC EN1, EN2 Pd1 Pd2 Pd3 Pd4 Topr Tstg Tjmax 7 *1*2 7 *1*2 VREG 7 *1*2 VREG 15.1 *1*2 0.38 0.88 3.26 4.56 *3 *4 *5 *6 -20～+100 -55～+150 +150 *1 Not to exceed Pd. *2 Instantaneous surge voltage, back electromotive force and voltage under less than 10% duty cycle. *3 Reduced by 3.04mW/℃ for each increase in Ta of 1℃ over 25℃ (when don’t mounted on a heat radiation board ) *4 Reduced by 7.04mW/℃ for increase in Ta of 1℃ over 25℃. (when mounted on a board 74.2mm×74.2mm×1.6mm Glass-epoxy PCB(1 layer), copper foil area : 20.2mm2) 2 *5 Reduced by 26.11mW/℃ for increase in Ta of 1℃ over 25℃. (when mounted on a board 74.2mm×74.2mm×1.6mm Glass-epoxy PCB(4 layer), copper foil area: 20.2mm , 2-3layer: 5505mm2) *6 Reduced by 36.5mW/℃ for increase in Ta of 1℃ over 25℃. (when mounted on a board 74.2mm×74.2mm×1.6mm Glass-epoxy PCB(4 layer), copper foil area: 5505mm2) ○Operating Conditions （Ta=25℃） Parameter Input Voltage BOOT Voltage SW Voltage BOOT-SW Voltage Logic Input Voltage Output Voltage MIN ON TIME ● Symbol VIN1, VIN2, VINS BOOT1, BOOT2 SW1, SW2 BOOT1-SW1, BOOT2-SW2 EN1, EN2 VOUT1, VOUT2 tonmin MIN. 7.5 4.5 -0.7 4.5 0 0.8 - MAX. 15 21 15 5.5 15 5.5 100 Unit V V V V V V ns This product is not designed to be used in a radioactive environment. REV. A 2/4 ○Electrical Characteristics (Unless otherwise noted, Ta=25℃ VCC=VREG, VIN1=VIN2=VINS=12V, VEN1=VEN2=3V, VOUT1=VOUT2=1.8V) Standard Value Parameter Symbol Unit Conditions MIN. TYP. MAX. [Whole Device] VINS Bias current IINS 1.7 2.2 mA VINS Standby current IINS_stb 0 10 μA VEN1=VEN2=0V EN Low Voltage1,2 VEN_low1,2 GND 0.3 V EN High Voltage1,2 VEN_high1,2 2.2 15 V EN Pull-down resistance1,2 REN1,2 28 48 68 kΩ [5VLinear Regulator] VREG Standby Voltage VREG_stb 0.1 V VEN1=VEN2=0V VINS=7.5V to 15V VREG Output Voltage VREG 4.8 5.0 5.2 V IREG=10mA [Under Voltage Lock Out] UVLO threshold Voltage VCC_UVLO 4.0 4.3 4.6 V VCC:Sweep up UVLO hysteresis Voltage dVCC_UVLO 100 160 220 mV VCC:Sweep down [Over Voltage Protection] OVP threshold Voltage1,2 VOVP1,2 0.86 0.96 1.06 V [H3RegTM Control] ON Time1,2 ton1,2 200 255 310 ns MIN OFF Time1,2 toffmin1,2 300 550 ns [FET Driver] High side ON resistance1,2 Ron_high1,2 75 120 mΩ Low side ON resistance 1,2 Ron_low1,2 50 75 mΩ [Current Control] Current Limit 1,2 Ilim1,2 3 4 5 A [Output Voltage Sense] FB threshold Voltage1,2 VFB1,2 0.788 0.8 0.812 V FB Input current1,2 IFB1,2 -1 1 μA VOUT=1V, VEN=0V, VOUT discharge current1,2 IVOUT1,2 5 10 mA VCC=5V [SCP] SCP threshold Voltage1,2 VSCP1,2 0.48 0.56 0.64 V REV. A 3/4 ○Block Diagram VOUT1 VOUT1 23 VIN VINS 3 4 VREG VREG BOOT1 25 EN1/UVLO EN1 EN2 5VReg VREG 1 2 32 26 27 28 VIN1 VIN VOUT1 SW1 EN1 UVLO FB1 22 Soft Start SS1 H3RegTM Controller Block + + R S Q SW1 Driver OCP1 Circuit VREG REF1 SS1 VREG 5 UVLO OCP1 SCP TSD OVP 0.96V FB1 + 29 30 31 PGND1 OVP1 EN1 + + 0.56V FB1 0.56V FB2 VCC Logic Input EN1 EN2 24 17 Reference Block REF1 REF2 BG UVLO UVLO SCP Delay OVP OVP2 TSD 0.96V FB2 VINS H3RegTM Controller Block + EN2 VREG BOOT2 16 7 8 9 VOUT2 VOUT2 18 Thermal Protection VIN2 VIN EN2/UVLO EN2 UVLO Soft Start SS2 REF2 SS2 UVLO OCP2 SCP TSD + + R S Q OCP2 SW2 Driver Circuit VREG 13 14 15 VOUT2 SW2 19 - FB2 OVP 10 11 12 PGND2 6, 20 21 GND TEST ○Physical Dimension Package：VQFN032V5050 Lot No. ○Pin number・Pin name PIN No. 1,2,32 3 4 5 6,20 7-9 10-12 13-15 16 17 18 19 21 22 23 24 25 26-28 29-31 Reverse PIN name VIN1 VINS VREG VCC GND VIN2 PGND2 SW2 BOOT2 EN2 VOUT2 FB2 *7 TEST FB1 VOUT1 EN1 BOOT1 SW1 PGND1 *7 FIN D95830 *7 The TEST pin (21pin) and the FIN should be connected with the GND. (Unit : mm) REV. A 4/4 ○ NOTE FOR USE 1. Absolute maximum ratings An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down the devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. If any over rated values will expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as fuses. 2. GND pin voltage GND, PGND1 and PGND2 terminal should be connected the lowest voltage, under all conditions. And all terminals except SW should be under GND terminal voltage under all conditions including transient situations. If a terminal exists under GND, it should be inserting a bypass route. 3. Thermal design If IC is used on condition that the power loss is over the power dissipation, the reliability will become worse by heat up, such as reduced output current capability. Also, be sure to use this IC within a power dissipation range allowing enough of margin. 4. Input supply voltage Input supply pattern layout should be as short as possible. 5. Inter-pin shorts and mounting errors Note the direction and the miss-registration of IC enough when you install it in the set substrate. IC might destroy it as well as reversely connecting the power supply connector when installing it by mistake. Moreover, there is fear of destruction when the foreign body enters between terminals, the terminal, the power supply, and grandeur and it is short-circuited. 6. Actions in strong electromagnetic field Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction. 7. ASO When using the IC, set the output transistor so that it does not exceed absolute maximum ratings or ASO. 8. Testing on application boards When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always discharge capacitors after each process or step. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic measure. Use similar precaution when transporting or storing the IC. 9. Electrical characteristics The electrical characteristics in the Specifications may vary depending on ambient temperature, power supply voltage, circuit(s) externally applied, and/or other conditions. It is therefore requested to carefully check them including transient characteristics. OUTPUT 10. Not of a radiation-resistant design. PIN 11. In the event that load containing a large inductance component is connected to the output terminal, and generation of back-EMF at the start-up and when output is turned OFF is assumed, it is requested to insert a protection diode. 12. Regarding input pin of the IC This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. P-N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic diode or transistor. For example, the relation between each potential is as follows: When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode. When GND > Pin B, the P-N junction operates as a parasitic transistor. Parasitic diodes can occur inevitable in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits, operational faults, or physical damage. Accordingly, methods by which parasitic diodes operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin, should not be used. Transistor (NPN) Resistor Pin A Pin B C B Pin B Pin A N N P P P N Parasitic element N N P P N E B C E Parasitic element P P substrate Parasitic element GND Parasitic element P substrate GND GND GND Other adjacent elements 13. Ground Wiring Pattern When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing a single ground point at the ground potential of application so that the pattern wiring resistance and voltage variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring pattern of any external components, either. 14. Operating ranges If it is within the operating ranges, certain circuit functions and operations are warranted in the working ambient temperature range. With respect to characteristic values, it is unable to warrant standard values of electric characteristics but there are no sudden variations in characteristic values within these ranges. 15. Thermal shutdown circuit This IC is provided with a built-in thermal shutdown (TSD) circuit, which is activated when the chip temperature reaches the threshold value listed below. When TSD is on, the device goes to high impedance mode. Note that the TSD circuit is provided for the exclusive purpose shutting down the IC in the presence of extreme heat, and is not designed to protect the IC per se or guarantee performance when or after extreme heat conditions occur. Therefore, do not operate the IC with the expectation of continued use or subsequent operation once the TSD is activated. TSD ON temperature [℃] (typ.) Hysteresis temperature[℃] (typ.) 175 15 16.Output Voltage Resistor Setting Output volage is adjusted with resistor. Total 10kohm resistor is recommended so that the output voltage is not affected by the FB input current (Typ. 1uA). 17. Over Output Current Protection This IC has an over current protection (4.0A[typ]), with prevents IC from being damage by short circuit at over current. However, It is recommend not to use that continuously operates the protection circuit (For instance, always the load that greatly exceeds the output current ability is connected or the output is short-circuited, etc.) in these protection circuits by an effective one to the destruction prevention due to broken accident. 18. Heat sink (FIN) Since the heat sink (FIN) is connected with the Sub, short it to the GND. REV. A Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. 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