Datasheet
3.5V to 60V Input
1ch Boost DC/DC Controller
BD9615MUV-LB
General Description
Key Specifications
This is the product guarantees long time support in
Industrial market.
BD9615MUV-LB is a low side MOSFET controller with
high withstand voltage (60V). It is suitable for circuits
requiring low side FET such as boost and flyback, and it
can be used in various applications.
An external resistor can adjust the switching frequency
from 100kHz to 2500kHz. It reduces the total mounting
area because It can operate at extremely high switching
frequency. In addition, it has an external clock
synchronization function to perform noise management.
BD9615MUV-LB has Thermal Shutdown (TSD), Over
Voltage Protection (OVP), and Over Current Protection
(OCP) to prevent damage caused by various abnormal
modes.
Input Voltage Range:
3.5V to 60V
Reference Voltage Precision: (Ta=25°C) 0.8V±1.5%
(Ta=-40°C to +105°C)
±2.0%
Frequency Range:
100kHz to 2500kHz
Operating Temperature Range:
-40°C to +105°C
Package
W (Typ) x D (Typ) x H (Max)
VQFN16KV3030
3.00mm x 3.00mm x 1.00mm
Features
Long Time Support Product for Industrial
Applications
Wide Input Voltage Range: 3.5V to 60V
Frequency Setting Function: 100kHz to 2500kHz
External Clock Synchronization Function
Soft Start Time Control Function
ON/OFF Control by the EN Pin (Standby Current
0μA)
Over Voltage Protection Function by an Independent
Pin
Normal/Abnormal Signal Output by the PGDB Pin
UVLO Control Function by External Resistors
MAX DUTY Change Function: (50%/90%)
High Power Small Package (VQFN16KV3030)
VQFN16KV3030
3.00mm x 3.00mm x 1.00mm
Applications
Industrial Instruments
Typical Application Circuit
VCC
CVCC
CVREF
EN
CVREG
VREF
VCC
CVIN
VREG
10μA
VREF
+
-
1.8V
+
-
ENUVLO
3.1V
C3
- OVP
+
0.9V
MON
R2
TSD
TSD
VCCUVLO
L1
VCCUVLO
OVP
SS_RST
CMP_GND
ENUVLO
COMP
UVP
+
0.65V
Power Good
TSD
PowerGood
LOGIC
OVP
C2
VREG
OCP
UVP
PGDB
CVOUT
UVP
DRV_CTL
SSDET
VOUT
D1
VREG
Q1
DRV_IN
-
FB
Soft
Start
CSS
SS
SS_
RST
OUT
+
+
-
ERROR AMP
0.8V
+
+
1.2V
+SSDET
-
CMP_
GND
ROCPM
PWM
+
OCP
SSDET
OCP
OCP_P
COCP
OCP_M
ROCPP
-
MAX
DUTY
OSC
MDT
RT
SYNC
R1
RSCOP
C1
RFB1
RMON1
RFB2
RMON2
GND
RRT
Figure 1. Typical Application Circuit
〇Product structure : Silicon monolithic integrated circuit
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Pin Configuration
VCC
EN
VREF
PGDB
(TOP VIEW)
SYNC
VREG
MDT
OUT
EXP-PAD
OCP_P
OCP_M
FB
SS
COMP
GND
MON
RT
Figure 2. Pin Configuration
Pin Description
Pin No.
Pin Name
Function
1
SYNC
2
MDT
3
RT
Resistor pin for setting frequency
4
SS
Pin for setting soft start time
5
MON
6
COMP
7
FB
8
OCP_P
Over current detect pin plus input pin
9
OCP_M
Over current detect pin minus input pin. Connect to GND
10
GND
GND pin
External clock input pin
MAX DUTY setting input pin
Output voltage monitor input Pin
ERROR AMP output pin
ERROR AMP input pin
11
OUT
Output pin for external FET driver
12
VREG
Power voltage output pin for driver
13
VCC
Power input pin
14
EN
15
VREF
Internal power voltage output pin
16
PGDB
-
EXP-PAD
Power Good output pin
Thermal pad for heat dissipation.
Connect to GND for increased heat dissipation.
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Block Diagram
EN
VREF
VCC
VREG
10μA
+
-
1.8V
+
-
ENUVLO
3.1V
- OVP
+
0.9V
MON
TSD
VREF
TSD
VCCUVLO
VCCUVLO
OVP
SS_RST
CMP_GND
ENUVLO
TSD
UVP
+
0.65V
Power Good
LOGIC
OVP
COMP
VREG
PGDB
OCP
UVP
UVP
DRV_CTL
SSDET
VREG
DRV_IN
-
FB
SS
Soft
Start
SS_
RST
OUT
+
+
-
ERROR AMP
0.8V
+
+
1.2V
+SSDET
-
CMP_
GND
PWM
+
OCP
OCP_P
OCP
SSDET
-
MAX
DUTY
OCP_M
OSC
MDT SYNC
RT
GND
LOGIC
OCP
ENUVLO
VCCUVLO
DRV_CTL
OVP
TSD
SS_RST
CMP_GND
OCP latch
OCP
S
UVP
SSDET
PowerGood
Q
R
20ms
Figure 3. Block Diagram
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Description of Blocks
1.
ERROR AMP
The ERROR AMP block is an error amplifier that detects the output signal and outputs the PWM control signal.
The internal reference voltage is set to 0.8V (Typ).
Connect a phase compensation element at the COMP pin.
2.
OSC
OSC block is an oscillation circuit with frequency setting function and external synchronization function.
The oscillation frequency can be set by the RT pin.
It can do external clock synchronous operation by inputting an external clock at the SYNC pin that is within ±20% of the
set frequency.
When not using the external synchronization function, connect the SYNC pin to GND.
3.
MAX DUTY
It is a MAX DUTY switching function. It can switch MAX DUTY 50% and 90% by setting H/L voltage. (H: 50%, L: 90%)
4.
PWM
PWM is a voltage – pulse width converter for controlling output voltage depending on the input voltage.
It compares the internal sawtooth waveform with the ERROR AMP output voltage, controls the pulse and outputs it to
the driver.
5.
VREF
The VREF block is an internal circuit power supply regulator. This voltage is 3.0V (Typ).
6.
VREG
VREG block is regulator for FET drive voltage. This voltage is 5.0V (Typ).
Voltage can be applied from an output voltage to the VREG pin.
7.
VCCUVLO
The VCCUVLO block prevents internal circuit error during decrease of power supply voltage.
It monitors the VCC pin voltage. When the VCC voltage becomes 3.1V (Typ) or less, it turns off output FET and DC/DC
converter output, and resets Soft Start circuit.
8.
ENUVLO
It can set low input voltage protection setting by configuring the EN pin with a resistor divider from VCC.
If the voltage from this pin is 0.3V or less, IC operation is off. If it is between 1.4V and 1.7V, internal REG circuit turns on.
If it is 1.8V (Typ) or more, the IC operates and a hysteresis generation current of 10μA (Typ) is sourced from the internal
circuit. To turn off the IC, source current should be removed.
9.
TSD
The TSD block is for thermal protection. When it detects the temperature exceeding Maximum Junction Temperature
(Tj=150°C), it turns off the output FET, and resets Soft Start circuit. When the temperature is decreased, the IC
automatically returns to normal operation with hysteresis.
10. OCP
This IC has over current protection to protect the FET from over current.
If over current flows in FET, OCP function turns off the output and protects FET.
11. OVP
The OVP block is an over voltage output detect function. If the MON pin voltage is 0.9V (Typ) or more, IC operation is
OFF. OVP detect threshold has a hysteresis of 50mV (Typ).
12. UVP
The UVP block is an under voltage output detect function. If the FB pin voltage is 0.65V (Typ) or less, the comparator
output is low. The output signal is added with other protection feature detection signals, and is output from the PGDB
pin.
13. Soft Start
The Soft Start circuit raises slowly the output voltage of the DC/DC converter to prevent in-rush current during start-up.
Soft Start time can be adjusted by an external capacitor CSS.
14. SSDET
This is a Soft Start finish detect block. If the SS pin voltage is SSDETTH (1.2V (Typ)) or more, SSDET output is high.
Output signal is added with other protection feature detection signals, and is output from the PGDB pin.
15. Power Good
This block generates an output signal that is the output voltage state of Normal or Error.
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Absolute Maximum Ratings (Ta=25°C)
Parameter
Supply Voltage
VCC to GND
EN to GND
PGDB to GND
Supply Voltage
VREG to GND
OUT to GND
Supply Voltage
VREF, SS, FB, COMP, MDT, RT, SYNC,
OCP_P, OCP_M, MON to GND
Storage Temperature Range
Symbol
Rating
Unit
VCC
VEN
VPGDB
62
V
VREG
12
V
VREF, VSS, VFB, VCOMP,
VMDT, VRT, VSYNC, VOCP_P,
VOCP_M, VMON
Tstg
7
V
-55 to +150
°C
Tjmax
150
°C
Maximum Junction Temperature
Caution 1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is
operated over the absolute maximum ratings.
Caution 2: Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in deterioration of the
properties of the chip. Increase the board size and copper area to prevent exceeding the maximum junction temperature rating.
Thermal Resistance(Note 1)
Parameter
Thermal Resistance (Typ)
Symbol
Unit
1s(Note 3)
2s2p(Note 4)
θJA
189.0
57.5
°C/W
ΨJT
23
10
°C/W
VQFN16KV3030
Junction to Ambient
Junction to Top Characterization
Parameter(Note 2)
(Note 1) Based on JESD51-2A(Still-Air).
(Note 2) The thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside
surface of the component package.
(Note 3) Using a PCB board based on JESD51-3.
Layer Number of
Measurement Board
Single
Material
Board Size
FR-4
114.3mm x 76.2mm x 1.57mmt
Top
Copper Pattern
Thickness
Footprints and Traces
70μm
(Note 4) Using a PCB board based on JESD51-5, 7.
Layer Number of
Measurement Board
4 Layers
Material
Board Size
FR-4
114.3mm x 76.2mm x 1.6mmt
Top
Thermal Via(Note 5)
Pitch
Diameter
1.20mm
Φ0.30mm
2 Internal Layers
Bottom
Copper Pattern
Thickness
Copper Pattern
Thickness
Copper Pattern
Thickness
Footprints and Traces
70μm
74.2mm x 74.2mm
35μm
74.2mm x 74.2mm
70μm
(Note 5) This thermal via connects with the copper pattern of all layers.
Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Power Supply Voltage
VCC
3.5
12
60
V
Switching Frequency
fOSC
100
500
2500
kHz
Switching Frequency Setting Resistor
RRT
19
100
500
kΩ
External Synchronize Frequency
External Synchronize Frequency for RT Setting
Frequency
Operating Temperature
fEXT
100
-
2500
kHz
-
-20
-
+20
%
Topr
-40
+25
+105
°C
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Electrical Characteristics (Unless otherwise specified Ta=25°C, VCC=12V, VEN=3V, RRT=100kΩ)
Parameter
Symbol
Limit
Min
Typ
Max
Unit
Conditions
Circuit Current
Standby Current
IST
-
0
10
µA
VEN=0V
Operating Current
ICC
-
2.0
4.0
mA
VFB=1.2V
VCCUVLO
UVLO Detect Threshold Voltage
UVLO Hysteresis
VUV
2.9
3.1
3.3
V
VUVHYS
30
100
200
mV
VREF
-
3.0
-
V
VCC sweep down
VREF
Output Voltage
VREG
Output Voltage
VREG
4.8
5.0
5.2
V
VREGOV
5.2
5.4
5.6
V
VREGOVHYS
30
100
200
mV
fOSC
450
500
550
kHz
MAX DUTY1
DMAX1
82
90
98
%
VMDT=L, VSYNC=0V
MAX DUTY2
DMAX2
42
50
58
%
VMDT=H, VSYNC=0V
MDT Pin Input High Level
VIH_MD
0.8 x VREF
-
VREF + 0.2
V
MDT Pin Input Low Level
VIL_MD
-0.3
-
0.2 x VREF
V
MDT Pin Input Current
IIH_MD
-
3
8
μA
VMDT=3.0V
0.788
0.800
0.812
V
Ta=25°C
0.784
0.800
0.816
V
Ta=-40°C to +105°C
OVLO Threshold Voltage
OVLO Hysteresis
VREG sweep up
Oscillator
Oscillating Frequency
MAX DUTY Cycle
RRT=100kΩ
ERROR AMP
FB Threshold Voltage
VFB
FB Pin Input Current 1
IFB1
-1
0
+1
μA
VFB=0V
FB Pin Input Current 2
IFB2
-1
0
+1
μA
VFB=3.0V
Maximum Output Voltage
VCMPH
2.7
VREF
-
V
Minimum Output Voltage
VCMPL
-
0
0.3
V
Output Sink Current
ICMPSI
0.5
1.5
-
mA
VCOMP=1.25V, VFB=1.5V
Output Source Current
ICMPSO
100
180
-
μA
VCOMP=1.25V, VFB=0V
SS Pin Source Current
ISSSO
1.4
2
2.6
μA
VSS=0.5V
SS Pin Sink Current
ISSSI
5
12
-
mA
VSS=0.5V
PGDB Pin Output Low Level Voltage
VPGBOL
-
-
0.4
V
IPGDB=1mA
PGDB Pin Leak Current
IPGBLK
-
0
10
μA
VPGDB=60V
UVP Detect Threshold Voltage
VPGTH
0.60
0.65
0.70
V
VFB sweep down
UVP Detect Hysteresis
VPGHYS
-
50
75
mV
OVP Detect Threshold Voltage
VOVPTH
0.85
0.90
0.95
V
OVP Detect Hysteresis
VOVPHYS
-
50
75
mV
MON Pin Input Current 1
IMON1
-1
0
+1
μA
VMON=0.0V
MON Pin Input Current 2
IMON2
-1
0
+1
μA
VMON=3.0V
Output High Side ON Resistance
RONH
1.5
3.0
4.5
Ω
VREG=5.0V
Output Low Side ON Resistance
RONL
0.8
1.7
2.6
Ω
VREG=5.0V
Soft Start
Power Good Signal Output
Monitor Output Voltage
VMON sweep up
Output
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Electrical Characteristics (Unless otherwise specified Ta=25°C, VCC=12V, VEN=3V, RRT=100kΩ) - continued
Parameter
Symbol
Limit
Unit
Conditions
Min
Typ
Max
VOCPTH
80
100
120
mV
OCP_P Pin Input Bias Current
IOCP_P
-
20
100
μA
VOCP_P=0.1V
OCP_M Pin Input Bias Current
IOCP_M
-
50
100
μA
VOCP_M=GND
tOCP
10
20
30
ms
EN Pin Internal REG ON-Threshold
VENON
0.3
-
1.4
V
EN Pin UVLO Threshold
VENUV
1.7
1.8
1.9
V
IC Output ON condition
IEN
9.0
10.0
11.0
μA
VEN=3V
SYNC Pin Threshold Voltage High
VSYNCH
2.0
-
5.5
V
SYNC Pin Threshold Voltage Low
VSYNCL
-0.3
-
+0.8
V
ISYNC
6
12
24
µA
OCP
Over Current Detect Threshold
Over Current Detect Latch Stop Time
CTL
EN Pin Source Current
SYNC
SYNC Pin Input Current
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Detailed Description
Frequency Setting Function
It can determine frequency input to PWM by using the RT pin.
It establishes constant current in the IC by connecting a timing resistor, RRT.
Oscillation frequency can be set from 100kHz to 2500kHz and calculated as follows.
1
𝑓𝑂𝑆𝐶 = 20×10−9 +𝑅
9
𝑅𝑇 ⁄(50×10 )
[Hz]
3,000
Frequency : fOSC[kHz]
2,500
2,000
1,500
1,000
500
0
0
100
200
300
400
500
RRT [kΩ]
Figure 4. Frequency vs RRT
External CLK for SYNC Function
This IC can operate synchronization function by inputting an external CLK signal to the SYNC pin.
Input CLK signal is limited within ±20% of the frequency set by the RT pin. LOW level is 0.8V or less, and HIGH level is
2.0V or more. Required width of H section and L section is 100ns or more.
After the 3rd input pulse at the SYNC pin, falling edge of internal sawtooth wave synchronizes with the falling edge of the
SYNC pin. If external CLK stops, the device transitions to self-running mode after 1.5 times of oscillation period.
SYNC
SYNC_LATCH
IC INTERNAL WAVE
Figure 5. Frequency Synchronization Function Timing Chart
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Detailed Description - continued
In the Case of Not Using the Synchronization Function
Although the SYNC pin is internally pulled down by a resistor, it is recommended to connect the SYNC pin to GND if the
synchronization function is not in use.
SYNC
GND
Figure 6. Circuit Diagram of SYNC Pin Not in Use
MDT Pin Function
It can change MAX DUTY by processing the MDT pin
If the MDT pin is connected to the GND pin, MAX DUTY is prescribed in DMAX1 and is limited to 90% (Typ).
If the MDT pin is connected to the VREF pin, MAX DUTY is prescribed in DMAX2 and is limited to 50% (Typ).
To prevent malfunction caused by noise, connect the MDT pin to the GND pin or the VREF pin.
When External Synchronize Frequency is input from SYNC (fEXT), MAX DUTY is determined by the frequency (fOSC) set
by the RT pin and MAX DUTY set by the MDT pin and is prescribed in DMAX_SYNC by following formula.
𝐷𝑀𝐴𝑋_𝑆𝑌𝑁𝐶 = (1 −
1
×(1−𝐷𝑀𝐴𝑋 )
𝑓𝑂𝑆𝐶
1
𝑓𝐸𝑋𝑇
) × 100 [%]
Where:
MDT=GND: DMAX = DMAX1: 90% (Typ)
MDT=VREF: DMAX = DMAX2: 50% (Typ)
UVLO Control Function by External Resistors
The EN pin has built-in precise reset function. The EN pin connected with a resistor divider from VCC, as shown in
Figure 7, can set low voltage malfunction prevention more than internal UVLO.
When it is used, establish REN1 and REN2, as shown in Figure 7, for any VCC start-up voltage VSTART [V] and VCC
shutdown voltage VSTOP [V].
VCC
𝑅𝐸𝑁1 =
VCCUVLO
REN1
𝑉𝑆𝑇𝐴𝑅𝑇 −𝑉𝑆𝑇𝑂𝑃
𝐼𝐸𝑁
𝑉𝐸𝑁𝑈𝑉 ×𝑅𝐸𝑁1
EN
𝑅𝐸𝑁2 = 𝑉
𝑆𝑇𝐴𝑅𝑇 −𝑉𝐸𝑁𝑈𝑉
IEN=10μA (Typ)
[Ω]
[Ω]
+
REN2
VENUV=1.8V (Typ)
Figure 7. Circuit Diagram of UVLO External Setting Method
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Detailed Description - continued
Soft Start Time
Soft Start Time tSS is determined by Soft Start Time Setting Capacitor CSS, SS Source Current ISSSO, and the FB pin
Threshold Voltage VFB. Set CSS capacitance that can be fully discharged during the “Hiccup” time when OCP is detected.
𝑉𝐹𝐵
𝑡𝑠𝑠 = 𝐶𝑆𝑆 × 𝐼
𝑆𝑆𝑆𝑂
[s]
In addition, when COMP terminal capacitor C3 is big and CSS is small, rise voltage ΔVSS of the SS pin voltage becomes
big at time tCOMP before COMP pin voltage arriving at lower voltage of the internal saw-tooth wave (1.0V) from EN ON,
and rush current occurs at the time of switching start. tCOMP, ΔVSS is calculated in the following formula.
Set CSS and COUT in consideration of rush current to be proportional to ΔVSS and COUT.
VOUT
R2
RFB1
FB
RFB2
+
+
VFB
C3
COMP
ERROR AMP
ISSSO
SS
CSS
Figure 8. Error amplifier circuit diagram
tCOMP
tCOMP
1.5V
1.5V
1.0V
1.0V
COMP
COMP
FB
SS
ΔVSS
ΔVSS
SS
OUT
OUT
Ideal line
Ideal line
VOUT
VOUT
EN ON
EN ON
Swiching start
Swiching start
Flyback application
Boost application
Figure 9. Output voltage starting diagram
Boost application
𝑡𝐶𝑂𝑀𝑃 = 𝐶3 (√(𝑅𝐹𝐵2 + 𝑅2 )2 +
2×𝐶𝑆𝑆 ×𝑅𝐹𝐵2
𝐶3 ×𝐼𝑆𝑆
(𝑅
𝑅2 ×𝑉𝐶𝐶
𝐹𝐵1 +𝑅𝐹𝐵2
+ 1) − (𝑅𝐹𝐵2 + 𝑅2 )) + 𝐼
𝐶𝑆𝑆 ×𝑉𝐶𝐶×𝑅𝐹𝐵2
𝑆𝑆 ×(𝑅𝐹𝐵1 +𝑅𝐹𝐵2 )
[s]
Flyback application
𝑡𝐶𝑂𝑀𝑃 = 𝐶3 (√(𝑅𝐹𝐵1 //𝑅𝐹𝐵1 + 𝑅2 )2 +
2×𝐶𝑆𝑆 ×𝑅𝐹𝐵1 //𝑅𝐹𝐵1
𝐶3 ×𝐼𝑆𝑆
− (𝑅𝐹𝐵1 //𝑅𝐹𝐵1 + 𝑅2 )) [s]
𝐼
∆𝑉𝑆𝑆 = 𝐶𝑆𝑆 × 𝑡𝐶𝑂𝑀𝑃 [V]
𝑆𝑆
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Detailed Description - continued
OVP Function
The MON pin has built-in OVP function. When the MON pin voltage becomes VOVPTH or more, switching of the OUT pin
is stop and switching is reopened if the MON pin voltage becomes VOVPTH-VOVPHYS or less. The OVP detect voltage
(VOVP) can be set by connecting the MON pin with a resistor divider from VOUT, as shown in Figure 10.
VOUT
OVP
RMON1
MON
𝑉𝑂𝑉𝑃 =
𝑅𝑀𝑂𝑁1 +𝑅𝑀𝑂𝑁2
RMON2
𝑅𝑀𝑂𝑁2
× 𝑉𝑂𝑉𝑃𝑇𝐻 [V]
VOVPTH = 0.9V (Typ)
Figure 10. Circuit Diagram of OVP Function Setting Method
OCP Function
If over current flows in FET, OCP function turns off the output and protects FET.
The voltage between the OCP_P pin and the OCP_M pin is monitored by OCP sense resistance. If the voltage exceeds
the overcurrent detection voltage (100mV (Typ)), the OUT pin is set to Low during the period (pulse by pulse control).
When OCP is detected twice consecutively, the IC is turned off 20ms (Typ) (“hiccup” operation), and the IC is turned on
if the voltage between the OCP_P pin and the OCP_M pin is lower than the over current detect voltage.
𝑅𝑆𝑂𝐶𝑃 =
Where:
VOCPTH
IOCP
𝑉𝑂𝐶𝑃𝑇𝐻
𝐼𝑂𝐶𝑃
[Ω]
Over Current Detect Threshold (100mV (Typ))
OCP detect current
If OCP detect circuit is unused, short the OCP_P pin and the OCP_M pin to the GND pin near the IC.
Figure 11. Timing Chart at OCP Operation
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Detailed Description – continued
[Noise Design for the OCP_P pin and the OCP_M pin]
The OCP input OCP_P OCP_M is a very sensitive circuit.
Therefore, there is a possibility of erroneous detection due to generated noise on the board.
As a measure to prevent erroneous detection at the OCP_P and the OCP_M pin, insert coupling capacitor and
resistance near and between the OCP_P and the OCP_M pin.
OCP_P
+
OCP
OCP Detect Resistance
OCP
OCP_M
Figure 12. Circuit Diagram of Noise Measurement
Before Measures
After Measures
OCP_P Voltage
OCP_P Voltage
OCP_M
Voltage
OCP_M Voltage
OCPth
OCP_P Voltage-OCP_M Voltage
OCP Detect
by Noise
OCPth
OCP_P Voltage-OCP_M Voltage
Figure 13. Effect of Noise Measurement
Consider in advance noise reduction on the board because there is limit to noise attenuation by the above measures.
As precaution on pattern, make current path as short as possible, and shorten the wiring to the OCP_P and OCP_M pin
as much as possible.
For peripheral components, select FET with small gate amount of charge Qg and select Di with small equivalent
capacitance and short reverse recovery time tRR for noise reduction.
Aside from adding a bypass capacitor, adding an RGATE makes the waveform duller (concern about the efficiency
deterioration as contradictory matter).
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Detailed Description – continued
VREG Pin Function
The VREG pin is output pin of internal regulator and it supplies 5.0V (Typ).
It drives Nch MOSFET via the OUT pin of driver output.
[Output Voltage Regenerative Function]
For the power consumption improvement of the VREG, it can regenerate to the VREG pin via diode when voltage is
upper than VREGOV. Voltage range that can regeneration is VREGOV (5.4V (Typ)) to 10V.
VCC
BD9615MUV-LB
VREG
VOUT
OUT
Figure 14. Example of Regeneration Application
[VCC Reduced Voltage]
Due to decrease of VCC supply voltage, drive voltage output from the VREG pin also decrease and driver R ON of the
OUT pin is increased.
Optimal drive voltage of FET is changed by oscillation frequency and the gate capacitance.
Selects FET and oscillation frequency that consider characteristic data when use at VCC is less than or equal to 5V.
Power Good Output Function
The PGDB pin is the open drain output of the internal Nch FET. Using external resistance, pull up the PGDB pin to
external power supply by external resister, to use Power Good Output function.
When an internal detection function is the non-detection, and output voltage is within the range from UVP (the FB pin) to
OVP (the MON pin), the PGDB pin is Low. When other operation mode or shutdown (EN=L), Nch MOSFET turns off and
the PGDB pin turns HIGH (pull-up voltage).
In addition, a connection between power supply (VCC) and output (VOUT) can be cut by connecting the PGDB pin like
Figure 15. Pull-up voltage of the PGDB pin has to be below its absolute maximum rating of 62V.
VCC
VOUT
OUT
PGDB
Figure 15. Circuit Diagram of Power Line Cutting Method
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Performance Curves (Reference Data)
(Unless Otherwise Specified, Ta=25°C, VCC=12V)
1.0
3.0
0.8
Operating Current : ICC [mA]
Standby Current : IST [µA]
0.9
0.7
0.6
0.5
0.4
0.3
0.2
2.5
2.0
1.5
1.0
0.5
0.1
0.0
0.0
0
10
20
30
40
50
Power Supply Voltage : VCC [V]
60
Figure 16. Standby Current vs Power Supply Voltage
0
10
20
30
40
50
Power Supply Voltage : VCC [V]
60
Figure 17. Operating Current vs Power Supply Voltage
(VFB=1.2V)
3.5
10.0
VREG Output Voltage : VREG [V]
9.0
UVLO Threshold [V]
3.4
3.3
release
3.2
3.1
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
detect
3.0
0.0
-40 -20
0
20 40 60 80 100 120
Temperature [˚C]
0
Figure 18. UVLO Threshold vs Temperature
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10
20
30
40
50
Power Supply Voltage : VCC [V]
60
Figure 19. VREG Output Voltage vs Power Supply
Voltage
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5.20
5.20
5.15
5.15
VREG Output Voltage : VREG [V]
VREG Output Voltage : VREG [V]
Performance Curves (Reference Data) - continued
5.10
5.05
5.00
4.95
4.90
4.85
5.05
5.00
4.95
4.90
4.85
4.80
4.80
-40 -20
0
20 40 60 80 100 120
Temperature [˚C]
Figure 20. VREG Output Voltage vs Temperature
0
5
10
15
VREG Output Current : IVREG [mA]
20
Figure 21. VREG Output Voltage vs VREG Output Current
550
100
540
90
530
80
MAX DUTY Cycle : DMAX [%]
Oscillating Frequency : fOSC [kHz]
5.10
520
510
500
490
480
470
460
MDT=0V
70
60
50
40
MDT=3V
30
20
10
450
0
-40 -20
0
20 40 60 80 100 120
Temperature [˚C]
-40 -20
20 40 60 80 100 120
Temperature [˚C]
Figure 23. MAX DUTY Cycle vs Temperature
Figure 22. Oscillating Frequency vs Temperature
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0.820
0.820
0.816
0.816
FB Threshold Voltage : VFB [V]
FB Threshold Voltage : VFB [V]
Performance Curves (Reference Data) - continued
0.812
0.808
0.804
0.800
0.796
0.792
0.788
0.808
0.804
0.800
0.796
0.792
0.788
0.784
0.784
0.780
0.780
0
10
20
30
40
50
Power Supply Voltage : VCC [V]
-40 -20
60
20 40 60 80 100 120
Temperature [˚C]
8
7
6
VCC=3.5V
5
4
3
2
0
Figure 25. FB Threshold Voltage vs Temperature
Figure 24. FB Threshold Voltage vs Power Supply
Voltage
8
Output Low Side ON Resistance : RONL [Ω]
Output High Side ON Resistance : RONH [Ω]
0.812
VCC=12V
1
7
6
5
VCC=3.5V
4
3
2
1
VCC=12V
0
0
-40
-20
0
20 40 60 80
Temperature [˚C]
-40
100 120
Figure 26. Output High Side ON Resistance vs
Temperature
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-20
0
20 40 60 80
Temperature [˚C]
100 120
Figure 27. Output Low Side ON Resistance vs
Temperature
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Performance Curves (Reference Data) - continued
11.0
120
Over Current Detect Threshold : VOCPTH [mV]
EN pin Source Current : IEN [µA]
10.8
10.6
10.4
10.2
10.0
9.8
9.6
9.4
9.2
9.0
115
110
105
100
95
90
85
80
-40 -20
0
20 40 60 80 100 120
Temperature [˚C]
-40 -20
Figure 28. EN pin Source Current vs Temperature
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20 40 60 80 100 120
Temperature [˚C]
Figure 29. Over Current Detect Threshold vs Temperature
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PGDB
DRV_CTL
SSDET
SS
OVP
UVP
FB/MON
(VOUT)
OCP_latch
OCP
TSD
ENUVLO
EN
VCCUVLO
VCC
NG
release
detect
detect
release
ENUVLO
OK
detect
SSDETTH
release
VPGTH+VPGHYS
release
detect
VPGTH
VUV
VCCUVLO
SSDETTH
VPGTH+VPGHYS
release
VUV+VUVHYS
VPGTH
detect
TSD
SSDETTH
VPGTH+VPGHYS
detect
VPGTH
20ms
OCP latch
OCP
SSDETTH
VPGTH+VPGHYS
VPGTH
UVP
release
VPGTH+VPGHYS
detect
VOVPTH
OVP
VOVPTH+VOVPHYS
ENUVLO
BD9615MUV-LB
Timing Chart
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BD9615MUV-LB
Reference Characteristics of Typical Application Circuit
VIN=3.5V, VOUT=5.1V,
fOSC=500kHz, Output Current=1A
1μF/10V
VIN
1μF/50V
10μF/50V
160kΩ
VREG
SYNC
12
1μF/25V
2
MDT
VOUT
SW
OUT
11
47μF/16V
RTR030N05FRATL
(ROHM)
220pF 4.3kΩ
EN
6.8μH
RB050LAM-60TFTR
(ROHM)
13
VCC
14
160kΩ
1
15
VREF
PGDB
16
RT
GND
10
4
SS
OCP_M
9
COMP
FB
OCP_P
0.01μF
MON
100kΩ
5
6
7
8
30kΩ
3
30kΩ
BD9615MUV-LB
39mΩ
100pF
10kΩ 3300pF
Figure 30. Typical Application Circuit
100
90
80
Efficiency [%]
70
60
50
40
30
20
10
0
1
10
100
Output Current [mA]
1000
Figure 31. Efficiency vs Output Current
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Reference Characteristics of Typical Application Circuits - continued
Phase
Phase
Gain
Gain
Figure 32. Frequency Characteristics Output
Current=0.1A
Figure 33. Frequency Characteristics Output
Current=1.0A
EN 2.0V/div.
EN 2.0V/div.
VOUT 5.0V/div.
VOUT 5.0V/div.
SW 3.0V/div.
SW 3.0V/div.
IL 1.0A/div.
IL 1.0A/div.
2ms/div.
2ms/div.
Figure 34. Startup Waveform
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Application Part Setting Method
(1) Inductor
It is recommended to use shielded type inductor that satisfies the
current rating (IPEAK) and has low DCR (direct current resistance).
Inductor value affects inductor ripple current and causes the
output ripple. This ripple current can become small when inductor
is large and switching frequency is high.
𝑉𝑂𝑈𝑇
𝐼𝑃𝐸𝐴𝐾 = 𝐼𝑂𝑈𝑇 𝜂×𝑉𝐼𝑁 + 𝛥 𝐼𝐿 ⁄2 [A]
∆𝐼𝐿 =
𝑉𝐼𝑁(𝑉𝑂𝑈𝑇−𝑉𝐼𝑁)
𝑉𝑂𝑈𝑇×𝑓𝑂𝑆𝐶 ×𝐿
[A]
Δ IL
∆IL
(1)
Figure 36. Inductor Current
(2)
where:
η is the efficiency
ΔIL is the output ripple current
fOSC is the switching frequency
Normally, ΔIL is set 30% or less of Max Output Current (IOUTMAX).
When a current flowing into the inductor exceeds the inductor current rating, it causes a magnetic saturation which
causes a decrease in efficiency and oscillation at the output. Choose an inductor with a sufficient margin so that
peak current does not exceed current rating of the inductor.
(2) About Switching Components FET and Di
Set switching components with sufficient margin of current tolerance obtained by the formula (1).
For noise and efficiency improvement, select FET with small input capacitance (CISS, Qg) and ON resistance.
Select Di with small equivalent capacitance, short reverse recovery time tRR, and small forward voltage VF.
(3) Output Capacitor
Choose output capacitor with the lower Equivalent Series Resistance (ESR).
Output Ripple Voltage VPP is determined in the formula (3).
𝑉𝑃𝑃 = 𝐼𝑂𝑈𝑇 × 𝐹
𝑉𝑂𝑈𝑇−𝑉𝐼𝑁
𝑂𝑆𝐶 ×𝐶𝑂𝑈𝑇 ×𝑉𝑂𝑈𝑇
+ 𝐼𝑃𝐸𝐴𝐾 × 𝐸𝑆𝑅 [V]
(3)
Set within the range of allowable ripple voltage.
The VREF pin, the VREG pin connection capacitor
Between the VREF pin, the VREG pin and the GND pin is need to connect 1μF ceramic capacitor.
It is needed to select capacitor from 0.5μF to 1.5μF that considers DC bias effect and temperature characteristics.
In case capacitor short Grand fault is supposed, there is a possibility of destruction by generation of heat.
Therefore, it is needed to measure set the capacitor in two series.
(4) Input Capacitor
Input capacitor needs to use electrolytic capacitor and ceramic capacitor.
Output switching current is supplied by Input Capacitor (CIN), so set ceramic bypass capacitor near FET and Di.
When using electrolytic capacitor, consider the allowable ripple current.
(5) Output Voltage Setting
Output Voltage is determined in the formula (4)
VOUT
RFB1
FB
𝑉𝑂𝑈𝑇 =
RFB2
𝑅𝐹𝐵1 +𝑅𝐹𝐵2
𝑅𝐹𝐵2
× 𝑉𝐹𝐵 [V]
(4)
VFB
Figure 37. Circuit Diagram of Voltage Feedback Resistor Setting Method
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Application Part Setting Method - continued
(6) Selection of External Phase Compensation
Stable condition of application
Negative feedback is applied is as follows.
When Gain is 1(0dB), phase delay is 135 degrees or less (phase margin is 45 degrees or more).
DC/DC converter application is sampled by switching frequency, so as a whole fBW (frequency at which gain is 0dB)
is set 1/10 or less of the switching frequency.
Also set fBW in less than 1/5 of boost converter peculiar right half plane zero (f RHPZ) so that right half plane zero
frequency does not influence a control loop.
In conclusion, Application target specifications are as follows.
(A) Gain is 1 (0dB), phase delay is 135 degrees or less (phase margin is 45 degrees or more).
(B) fBW is 1/10 or less of switching frequency
(C) fBW is 1/5 or less of fRHPZ
It set C1, C3, R1, and R2 of Figure 38 that meet the above.
fBW that determines DC/DC converter responsiveness is able to calculate by evaluate 1st pole frequency and DC
gain.
1st pole frequency
DC Gain
𝑓𝑝1 =
1
𝑅
×𝑅
(2𝜋×𝐴× 𝐹𝐵1 𝐹𝐵2 ×𝐶3 )
𝑅𝐹𝐵1 +𝑅𝐹𝐵2
𝐴
𝐷𝐶𝑔𝑎𝑖𝑛 = 𝐵 × 𝑉𝐹𝐵 ×
[Hz]
VOUT
C1
RFB1
R2
C3
R1
𝑉𝑂𝑈𝑇
𝑉𝐼𝑁
COMP
RFB2
Where
A: ERROR Amp Gain=104 (=80dB)
B: Oscillator amplitude=0.5V
𝑓𝐵𝑊 = 𝐷𝐶𝑔𝑎𝑖𝑛 × 𝑓𝑝1 [Hz]
Figure 38. Example of Phase Compensation Setting
𝑉𝐼𝑁 2
1
𝑓𝑅𝐻𝑃𝑍 = 2×𝜋×𝐿×𝐼𝑂𝑈𝑇 × 𝑉𝑂𝑈𝑇 [Hz]
Insert second order phase lead in order to cancel the second order phase delay by LC. Insert phase lead near LC
resonance frequency.
1
Phase Lead
𝑓𝑧1 =
Phase Lead
𝑓𝑧2 = 2×𝜋×𝑅
[Hz]
2𝜋×𝑅𝐹𝐵1 ×𝐶1
1
2 ×𝐶3
LC Resonance Frequency
[Hz]
1−𝐷
= 2×𝜋√𝐿×𝐶
𝑂𝑈𝑇
[Hz]
Where
COUT: Output Capacitor
D: ON Duty=(VOUT-VIN)/VOUT
If fBW goes excessive high frequency by second order phase lead, it may be stabilized by inserting first order phase
delay to frequency above LC resonance frequency to further compensate it.
Phase Delay
1
𝑓𝑝2 = 2×𝜋×𝑅
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PCB Layout
Consider the following general points to bring out the IC performance.
1.
2.
3.
4.
5.
Each input of the OCP_P pin and the OCP_M pin are very sensitive. Consider the above-mentioned contents.
For noise caused by parasitic capacitance coupling, consider routing by keep distance to providing a buffer zone.
Especially wiring those are sensitive to noise such as the OCP_P pin, the OCP_M pin and the COMP pin.
Near the OCP_P pin, the OCP_M pin and phase compensation circuit need to set pre-pattern about capacitor as
insurance.
Place the bypass capacitor near the input of the IC, FET, and Di and wire it as short as possible.
Be careful not to have common impedance to high current system with analog system VCC (GND).
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I/O Equivalence Circuit
Pin
No.
Pin
Name
Pin
No.
Pin Equivalence Circuit
Pin
Name
Pin Equivalence Circuit
VREF
SYNC
MON
1
SYNC
5
MON
GND
GND
VREF
VREF
VREF
MDT
2
COMP
MDT
6
COMP
GND
GND
VREF
VREF
+
FB
RT
3
RT
7
FB
GND
GND
VREF
VREF
VREF
SS
4
SS
8
OCP_P
OCP_P
GND
GND
GND
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I/O Equivalence Circuit - continued
Pin
No.
Pin
Name
Pin
No.
Pin Equivalence Circuit
Pin
Name
Pin Equivalence Circuit
VREF
VREF
VCC
EN
9
OCP_M
14
OCP_M
EN
GND
GND
GND
VCC
VCC
+
-
11
OUT
VREF
OUT
15
VREF
GND
GND
VCC
+
-
12
VREG
PGDB
16
VREG
PGDB
GND
GND
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Operational Notes
1.
Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power
supply pins.
2.
Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Furthermore, connect a capacitor to ground at
all power supply pins. Consider the effect of temperature and aging on the capacitance value when using electrolytic
capacitors.
3.
Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.
4.
Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5.
Recommended Operating Conditions
The function and operation of the IC are guaranteed within the range specified by the recommended operating
conditions. The characteristic values are guaranteed only under the conditions of each item specified by the electrical
characteristics.
6.
Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow
instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power
supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and
routing of connections.
7.
Operation Under Strong Electromagnetic Field
Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction.
8.
Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may
subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply
should always be turned off completely before connecting or removing it from the test setup during the inspection
process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during
transport and storage.
9.
Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and
unintentional solder bridge deposited in between pins during assembly to name a few.
10. Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small
charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and
cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the
power supply or ground line.
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BD9615MUV-LB
Operational Notes – continued
11. Regarding the Input Pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be
avoided.
Resistor
Transistor (NPN)
Pin A
Pin B
C
E
Pin A
N
P+
P
N
N
P+
N
Pin B
B
Parasitic
Elements
N
P+
N P
N
P+
B
N
C
E
Parasitic
Elements
P Substrate
P Substrate
GND
GND
Parasitic
Elements
GND
Parasitic
Elements
GND
N Region
close-by
Figure 39. Example of monolithic IC structure
12. Ceramic Capacitor
When using a ceramic capacitor, determine a capacitance value considering the change of capacitance with
temperature and the decrease in nominal capacitance due to DC bias and others.
13. Thermal Shutdown Circuit(TSD)
This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always
be within the IC’s maximum junction temperature rating. If however the rating is exceeded for a continued period, the
junction temperature (Tj) will rise which will activate the TSD circuit that will turn OFF power output pins. When the Tj
falls below the TSD threshold, the circuits are automatically restored to normal operation.
Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no
circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from
heat damage.
14. Over Current Protection Circuit (OCP)
This IC incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. This
protection circuit is effective in preventing damage due to sudden and unexpected incidents. However, the IC should
not be used in applications characterized by continuous operation or transitioning of the protection circuit.
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BD9615MUV-LB
Ordering Information
B
D
9
6
1
Part Number
5
M
U
V
-
Package
MUV: VQFN16KV3030
LBE2
Product Rank
LB: for Industrial applications
Packaging specification
E2: Embossed tape and reel
Marking Diagram
VQFN16KV3030 (TOP VIEW)
Part Number Marking
BD9
LOT Number
6 1 5
Pin 1 Mark
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BD9615MUV-LB
Physical Dimension and Packing Information
Package Name
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BD9615MUV-LB
Revision History
Date
Revision
24.Apr.2018
001
21.jun.2018
002
07.May.2020
003
Changes
New release
The Package Name was changed.
VQFN16SV3030 → VQFN16KV3030
Add the value to Electrical Characteristics.
VUVHYS Min,
VREGOVHYS Min,
RONH Min/Max,
RONL Min/Max
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Notice
Precaution on using ROHM Products
1.
If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment (Note 1),
aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,
bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales
representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any
ROHM’s Products for Specific Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅣ
CLASSⅢ
2.
ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3.
Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below.
Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the
use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our
Products under any special or extraordinary environments or conditions (as exemplified below), your independent
verification and confirmation of product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used.
However, recommend sufficiently about the residue.); or Washing our Products by using water or water-soluble
cleaning agents for cleaning residue after soldering
[h] Use of the Products in places subject to dew condensation
4.
The Products are not subject to radiation-proof design.
5.
Please verify and confirm characteristics of the final or mounted products in using the Products.
6.
In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7.
De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in
the range that does not exceed the maximum junction temperature.
8.
Confirm that operation temperature is within the specified range described in the product specification.
9.
ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1.
When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2.
In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PAA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.004
Precautions Regarding Application Examples and External Circuits
1.
If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2.
You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1.
Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl 2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2.
Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3.
Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4.
Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
trade act, please consult with ROHM in case of export.
Precaution Regarding Intellectual Property Rights
1.
All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data.
2.
ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the
Products with other articles such as components, circuits, systems or external equipment (including software).
3.
No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM
will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to
manufacture or sell products containing the Products, subject to the terms and conditions herein.
Other Precaution
1.
This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2.
The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3.
In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4.
The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice-PAA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.004
Datasheet
General Precaution
1. Before you use our Products, you are requested to carefully read this document and fully understand its contents.
ROHM shall not be in any way responsible or liable for failure, malfunction or accident arising from the use of any
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this document is current as of the issuing date and subject to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the latest information with a ROHM sales
representative.
3.
The information contained in this document is provided on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate and/or error-free. ROHM shall not be in any way responsible or
liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccuracy or errors of or
concerning such information.
Notice – WE
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.001
