BD9775FV-E2

Large Current External FET Switching Regulator Controllers High Efficiency Step-down Switching Regulator Controller BD9775FV No.11028EAT17 ●Description BD9775FV is Switching Controller with synchronous rectification (BD9775FV is 1channel synchronous rectification) and wide input range. It can contribute to ecological design (lower power consumption) for most of electronic equipments. ●Features 1) 2channel Step-Down DC/DC FET driver 2) Synchronous rectification for channel 2 3) Able to synchronize to an external clock signal 4) Over Current Protection (OCP) by monitoring VDS of P channel FET 5) Short Circuit Protection (SCP) by delay time and latch method 6) Under Voltage Lock Out (UVLO) 7) Thermal Shut Down (TSD) 8) Package: SSOP-B28 ●Applications Car navigation system, Car Audio, Display, Flat TV ●Absolute maximum ratings (Ta=25℃) Parameter Supply Voltage (VCC to GND) VREF to GND Voltage VREGA to GND Voltage VREGB to VCC Voltage OUT1, OUT2H to VCC Voltage OUT2L to GND Voltage Power Dissipation Operating Temperature Range Storage Temperature Range Junction Temperature Symbol VCC Vref Vrega Vregb Vouth Voutl Pd Topr Tstg Tjmax Ratings 36 7 7 7 7 7 640(*1) -40 to +85 -55 to +125 +125 Unit V V V V V V mW ℃ ℃ ℃ (*1) Without heat sink, reduce to 6.4mW when Ta=25℃ or above Pd is 850mW mounted on 70x70x1.6mm, and reduce to 8.5mW/℃ above 25℃. ●Recommended operating conditions (Ta=-25 to +75℃) Parameter Supply Voltage Oscillating Frequency Timing Resistance Timing Capacitance Symbol VCC fosc RT CT Ratings Min. 6.0 30 10 100 Typ. 100 27 470 Max. 30.0 300 56 4700 Unit V kHz kΩ pF www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 1/14 2011.05 - Rev.A BD9775FV ●Electrical characteristics (Ta=25℃, VCC=13.2V, fosc=100kHz, CTL1=3V, CTL2=3V) Limits Parameter Symbol Unit Min. Typ. Max. 【Whole Device】 Stand-by Current Circuit Current 【Reference Voltage】 VREF Output Voltage Line Regulation Load Regulation Short Output Current 【Internal Voltage Regulator】 VREGA Output Voltage VREGB Output Voltage VREGB Dropout Voltage 【Oscillator】 Oscillating Frequency Frequency Tolerance 【Synchronized Frequency】 Synchronized Frequency FIN Threshold Voltage FIN Input Current 【Error Amplifier】 Threshold Voltage INV Input Bias Current Voltage Gain Band Width Maximum Output Voltage Minimum Output Voltage Output Sink Current Output Source Current Vthea Ibias Av Bw Vfbh Vfbl Isink Isource1 Isource2 0.98 -1 － － 2.2 － 0.5 -170 -200 1.00 － 70 2.0 2.4 － 2 -110 -130 1.02 1 － － 2.6 0.1 5.2 -70 -85 V µA dB MHz V V mA µA µA DC Av=0dB INV=0.5V INV=1.5V FB1,2 Terminal FB1 Terminal FB2 Terminal fosc2 Vthfin IFIN － 1.2 -1 120 1.4 － － 1.6 1 kHz V µA VFIN=1.4V FIN=120kHz fosc Dfosc 90 － 100 － 110 2 kHz % Vrega Vregb Vdregb 4.5 VCC-5.5 － 5.0 VCC-5.0 1.8 5.5 VCC-4.5 2.2 V V V Vref DVli DVlo Ios 2.97 － － -60 3.00 － － -22 3.03 10 10 -5 V mV mV mA Io=-1mA Iccst Icc － 2.5 － 4.2 5 7 µA mA CTL1,CTL2=0V FB1,FB2=0V Technical Note Condition Vcc=7 to 18V,Io=-1mA Io=-0.1mA to -2mA Switching with COUT=5000pF Switching with COUT=5000pF VREGB to GND Voltage RT=27kΩ,CT=470pF Vcc=7 to 18V www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 2/14 2011.05 - Rev.A BD9775FV Technical Note Parameter 【PWM Comparator】 Threshold Voltage at 0% Threshold Voltage at 100% DTC Input Bias Current 【FET Driver】 Sink Current Source Current ON Resistance Rise Time Fall Time Driver’s Duty Cycle of Synchronous Rectification SYNC Terminal Voltage Symbol Limits Min. Typ. Max. Unit Condition Vth0 Vth100 Idtc 0.88 1.88 -1 0.98 1.98 － 1.08 2.08 1 V V µA FB Voltage FB Voltage Isink Isource RonN RonP Tr Tf ΔDuty Vsync 20 -510 7.0 0.7 － － 42 1.45 36 -320 11.0 1.4 20 100 45 1.55 58 -180 17.8 2.2 － － 48 1.65 mA mA Ω Ω nsec nsec % V VDS=0.4V VDS=0.4V OUT1,2H,2L : L OUT1,2H,2L : H Switching with COUT=5000pF Switching with COUT=5000pF RSYNC=30KΩ, 50% of main driver’s duty cycle Rsync=30KΩ,FB=1.5V RCL=21kΩ, the output turn off after detected 8 cycle VS1,VS2=PBU VS1,VS2=0V 【Over Current Protection (OCP)】 VS Threshold Voltage VS Input Current CL Input Current 【Stand-by】 Threshold Voltage CL Input Current 【Short Circuit Protection (SCP)】 Timer Start Voltage Threshold Voltage Stand-by Voltage Source current Vtime Vthscp Vstscp Isoscp 0.6 1.92 － -4.0 0.7 2.00 10 -2.5 0.8 2.08 100 -1.5 V V mV µA INV Voltage SCP Voltage SCP Voltage SCP=1.0V Vctl Ictl 1.0 6 1.5 15 2.0 30 V µA CTL1,CTL2=3V Vths IVSH IVSL Icl VCC-0.24 VCC-0.21 VCC-0.18 -1 -1 9 － － 10 1 1 11 V µA µA µA 【Under Voltage Lock Out (UVLO)】 Threshold Voltage Hysteresis Voltage Range Vuvlo DVuvlo 5.6 0.05 5.7 0.1 5.8 0.15 V V Vcc sweep down www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 3/14 2011.05 - Rev.A BD9775FV ●Pin Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Technical Note ●Pin No. / Pin Name VS1 CL1 PVCC1 OUT1 VREGB OUT2H PVCC2 CL2 VS2 SCP VREGA OUT2L PGND SYNC 28 27 26 25 24 23 22 FB1 INV1 RT CT Fin GND VREF DTC1 DTC2 INV2 FB 2 CTL1 CTL2 VCC Pin No. 1 2 3 4 5 Pin Name FB1 INV1 RT CT FIN GND VREF DTC1 DTC2 INV2 FB2 CTL1 CTL2 VCC SYNC PGND Description Error amplifier output pin(Channel 1) Error amplifier negative input pin(Channel 1) Oscillator frequency adjustment pin connected resistor Oscillator frequency adjustment pin connected capacitor Oscillator synchronization pulse signal input pin Low-noise ground Reference voltage output pin Maximum duty and soft start adjustment pin (Channel 1) Maximum duty and soft start adjustment pin (Channel 2) Error amplifier negative input pin(Channel 2) Error amplifier output pin(Channel 2) Enable/stand-by control input(Channel 1) Enable/stand-by control input(Channel 2) Main power supply pin Synchronous rectification timing adjustable pin 21 20 19 18 6 7 8 9 10 11 12 17 16 15 Fig.1 Pin Description ●Block Diagram 13 14 15 16 17 18 19 20 21 22 Fig.2 Block Diagram 23 24 25 26 27 28 Power ground (connected low-side gate driver and digital ground) Low-side ( synchronous rectifier ) gate driver OUT2L output pin(Channel 2) VREGA Connected capacitor for internal regulator Delay time of short circuit protection adjustment pin connected capacitor Over current detection voltage monitor pin VS2 (connected FET drain, Channel 2) Over current detection voltage adjustment pin CL2 connected capacitor and resistor(Channel 2) High-side gate driver power supply input PVCC2 (Channel 2) SCP OUT2H High-side gate driver output pin(Channel 2) VREGB Connected capacitor for internal regulator OUT1 PVCC1 CL1 VS1 High-side gate driver output pin(Channel 1) High-side gate driver power supply input (Channel 1) Over current detection voltage adjustment pin connected capacitor and resistor(Channel 1) Over current detection voltage monitor pin (connected FET drain, Channel 1) www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 4/14 2011.05 - Rev.A BD9775FV Technical Note ●Function Explanation 1. DC/DC Converter ・Reference Voltage Stable voltage of compensated temperature, is generated from the power supply voltage (VCC). The reference voltage is 3.0V, the accuracy is ±1%. Place a capacitor with low ESR (several decades mΩ) between VREF and GND. ・Internal Regulator A (VREGA) 5V is generated the power supply voltage. The voltage is for the driver of the synchronous rectification’s MOSFET. Place a capacitor with low ESR (several decades mΩ) between VREGA and PGND. ・Internal regulator B (VREGB) (VCC-5V) is generated from the power supply voltage. The voltage is for the driver of the main MOSFET switch. Place a capacitor with low ESR (several decades mΩ) between VREGB and PVCC. ・Oscillator Placing a resistor and a capacitor to RT and CT, respectively, generates two triangle waves for both cannels, and each wave is opposite phase. The waves are input to the PWM comparators for CH1 and CH2. Also, the oscillating frequency can be slightly adjusted (less than 20%) by putting external clock pulse into Fin pin, which is higher frequency than the fixed one. ・Error Amplifier It amplifies the difference, between the establish output voltage and the actual output one detected at INV. And amplified voltage comes out from FB. The comparing voltage is 1.0V and the accuracy is ± 2%. The phase can be compensated externally by placing a resistor and a capacitor between INV and FB. ・PWM Comparator It converts the output voltage from error amplifier into PWM waveform, then output to MOSFET driver. ・MOSFET Driver The main drivers (OUT1, OUT2H) are for P-channel MOSFETs, and the driver (OUT2L) for synchronous rectification is for N-channel MOSFET. The values of output voltage are clamp to VREGB, VREGA, respectively. All drivers’ output configurations are push-pull type. In addition, the output current capability is 36mA for the sink current and 320mA (Vds=0.4V) for the source current. 2. Channel Control Each output can be individually turned on or off with CTL1 and CTL2. When the CTL is “H” (more than 1.5V), it becomes turned on. 3. Protection ・Over Current Protection(OCP) When detected over current (detecting drop voltage of the main MOSFET’s ON resistance), the MOSFET switch becomes turned off, and the energy on DTC pin is discharged. After discharged, the output restarts automatically. The level of the OCP detection threshold can be set by the resistance, which is connected between VCC and CL. ・Short Circuit Protection(SCP) When either output goes down and the voltage on INV pin gets lower than 0.7V, a capacitor placed on SCP is started to charge. When the SCP pin becomes more than 2.0V, the main MOSFET switches of both outputs are turned off; then, the outputs are latched. While they are latched, the IC can be reset by restarting VCC or CTL, or discharging SCP. ・Under Voltage Lock Out(UVLO) Due to avoiding malfunctions when the IC is started up or the power supply voltage is rapidly disconnected, the main MOSFET switches become off and DTC is discharged when the supply voltage is less than 5.7V. Also, when the output is latched because of SCP function, the latch becomes reset. Due to preventing malfunctions in the case the power supply voltage fluctuate at near UVLO threshold, there is 0.1V hysteresis between the detection and reset voltage of UVLO threshold. ・Thermal Shut Down(TSD) Due to preventing breakdown of the IC by heating up, the main MOSFET switches become off and DTC pin is discharged by detecting over temperature of the chip. Due to preventing malfunctions in the case temperature fluctuate at near TSD threshold, there is hysteresis between TSD on and off. www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 5/14 2011.05 - Rev.A BD9775FV Technical Note ●Setting Up Information 1) Simultaneously OFF Duty of MOSFETs for Synchronous Rectification The simultaneously OFF duty of both main MOSFET switch and synchronous rectification MOSFET is determined by resistance (Rsync) between SYNC and GND. See Fig.3. In Synchronous Rectification, insert RFB2-GND (RFB2-GND≒3 ×Rsync) between FB2 and GND, because it is possible to reduce overshoot(see Fig.3). RFB2-GND decides following formula. 40 35 30 25 ΔDuty (%) T=-40℃ T= 25℃ T=105℃ 20 15 10 5 t t1 t2 O UT2H OUT2L 0 0 20 40 Rsync (kΩ) 60 80 100 Fig.3 ・Resistance at FB2-GND setup condition Threshold Voltage at100% Vsync 3×Rsync(MAX) < RFB2-GND < 3xRsync(MIN) -Output Source Current at FB2 2.08 0.4908 Rsync(MAX) +80.7x10 -6 < RFB2-GND < 3xRsync(MIN) ※Rsync(MAX)…MAX dispersion range at Rsync Rsync(MIN)…MIN dispersion range at Rsync SYNC Rsync FB2 RFB2-GND Short SYNC to VREF if the synchronous rectification function is not needed. VREF SYNC Without Synchronous Rectification(Don’t insert RFB2-GND) www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 6/14 2011.05 - Rev.A BD9775FV Technical Note 2) Oscillator Synchronization by External Pulse Signal At the operation the oscillator is externally synchronized, input the synchronization signal into Fin in addition to connect a resistor and a capacitor at RT and CT, respectively. Input the external clock pulse on Fin, which is higher frequency than the fixed one. However, the frequency variation should be less than 20%. Also, the duty cycle of the pulse should be set from 10% to 90%. Fin ： Fixed with RT and CT CT ： Synchronized Fig.4 CT Waveform during Synchronized with External Pulse Short Fin to GND if the function of external synchronization is not needed. Fin Fig.5 Without Synchronization Signal 3) Setting the Over Current Threshold Level The OCP detection level (Iocp) is determined by the ON resistance (RON) of the main MOSFET switch and the resistance (Rcl) which is placed between CL and VCC. Rcl Iocp = RON ×10 -5 [A] (typ.) To prevent a malfunction caused by noise, place a capacitor (Ccl) parallel to Rcl. If OCP function is not needed, short VS to VCC, and short CL to GND. VCC Rcl CL Ccl CL VCC VS To Main MOSFET Drain VS With OCP Without OCP Fig.6 CL, VS Pin Connection www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 7/14 2011.05 - Rev.A BD9775FV Technical Note 4) Setting the Time for Short Circuit Protection The time (tscp) from output short to latch activation is determined by the capacitor, Cscp, connected SCP pin. 5 tscp=7.96×10 ×Cscp [sec] (typ.) Short SCP to GND if SCP function is not being used. SCP Fig.7 Without SCP 5) Single Channel Operation This device can be used as a single output. The connection is as follows; DTC, FB, CTL, CL VS, PVCC INV Short to GND Short to VCC Short to VREF DTC FB CTL CL VS PVCC INV VREF VCC Fig.8 Single Channel Operation 6) Setting the Oscillating Frequency The oscillating frequency can be set by selecting the timing resistor (RRT) and the timing capacitor (CCT). 1000 1000 Oscillating Frequency (kHz) CCT=100pF CCT=470pF Oscillating Frequency (kHz) RRT=5.1kΩ 100 RRT=27kΩ 100 CCT=1000pF RRT=100kΩ 10 10 100 Timing Resistance (kΩ) 1000 10 100 1000 Timing Capacitance(pF) 10000 Fig.9 Oscillating Frequency vs. Timing Capacitance (CCT) Fig.10 Oscillating Frequency vs. Timing Capacitance (RRT) www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 8/14 2011.05 - Rev.A BD9775FV ●Timing Chart ・Output ON/OFF, Minimum Input(UVLO) VCC Technical Note 6.0V UVLO is activated at 5.7V UVLO is inactivated at 5.8V CTL1 DTC1 Vout1 CTL2 DTC2 Vout2 1.0V 1.0V Stand-by Soft start Fig.11 ・Over Current Protection, Short Circuit Protection, Thermal Shut Down CTL1,2 SCP DTC1,2 0.7×fixed output voltage 1.0V Activate TSD Inactivate TSD Activate SCP 2.0V Reset the latch by restarting CTL Vout1,2 Half short of output OCP detection level Iout1,2 Inactivate half-short OCP is activated by detecting 8 consecutive cycles Fig.12 www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 9/14 2011.05 - Rev.A BD9775FV ●I/O Equivalent Circuit FB1(1) VREF VREGA VCC Technical Note FB2(11) VREF VREGA VCC RT(3) VREF VCC FB1 RT INV1(2),INV2(10) VREF VCC CT(4) VREF VCC FIN(5) VREG A VCC INV1,2 FIN DTC1(8),DTC2(9) VREGA VREF VCC CTL1(12),CTL2(13) VREGA VCC SYNC(15) VREF VCC DTC1,2 CTL1,2 SYNC SCP(19) VREF VCC OUT2L(17),VREGA(18) VCC VREF(7) VCC VREGA ～ ～ SCP OUT2L ～ ～ VREF PVCC1(26),PVCC2(22) OUT1(25),OUT2H(23),VREGB(24) VCC PVCC1,2 OUT1,2H VS1(28),VS2(20),CL1(27),CL2(21) VCC CL1,2 VREGB VS1,2 Fig.13 www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 10/14 2011.05 - Rev.A BD9775FV Technical Note ●Notes for use 1) Absolute maximum ratings Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may result in IC deterioration or damage. Assumptions should not be made regarding the state of the IC (short mode or open mode) when such damage is suffered. A physical safety measure such as a fuse should be implemented when use of the IC in a special mode where the absolute maximum ratings may be exceeded is anticipated. 2) GND potential Ensure a minimum GND pin potential in all operating conditions. In addition, ensure that no pins other than the GND pin carry a voltage lower than or equal to the GND pin, including during actual transient phenomena. Thermal design Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. Inter-pin shorts and mounting errors Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in damage to the IC. Shorts between output pins or between output pins and the power supply and GND pin caused by the presence of a foreign object may result in damage to the IC. Operation in a strong electromagnetic field Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction. Thermal shutdown circuit (TSD circuit) This IC incorporates a built-in thermal shutdown circuit (TSD circuit). The TSD circuit is designed only to shut the IC off to prevent runaway thermal operation. Do not continue to use the IC after operating this circuit or use the IC in an environment where the operation of the thermal shutdown circuit is assumed. Testing on application boards When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always discharge capacitors after each process or step. Ground the IC during assembly steps as an antistatic measure, and use similar caution when transporting or storing the IC. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process. Common impedance Power supply and ground wiring should reflect consideration of the need to lower common impedance and minimize ripple as much as possible (by making wiring as short and thick as possible or rejecting ripple by incorporating inductance and capacitance). Applications with modes that reverse VCC and pin potentials may cause damage to internal IC circuits. For example, such damage might occur when VCC is shorted with the GND pin while an external capacitor is charged. It is recommended to insert a diode for preventing back current flow in series with VCC or bypass diodes between VCC and each pin. Bypass diode Countercurrent prevention diode Vcc Pin 3) 4) 5) 6) 7) 8) 9) Fig.14 10) Timing resistor and capacitor Timing resistor (capacitor) connected between RT (CT) and GND, has to be placed near RT (CT) terminal 3pin (4pin). And pattern has to be short enough. 11) The Dead time input voltage has to be set more than 1.1V. Also, the resistance between DTC and VREF is used more than 30kΩ to work OCP function reliably. 12) The energy on DTC1(8pin)and DTC2(9pin)is discharged when CTL1(12pin)and CTL2(13pin)are OFF, respectively, or VCC(14pin)is OFF (UVLO activation). However, it is considerable to occur overshoot when CTL and VCC are turned on with remaining more than 1V on the DTC. www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 11/14 2011.05 - Rev.A BD9775FV Technical Note 13) If Gate capacitance of P-channel MOSFET or resistance placed on Gate is large, and the time from beginning of Gate switching to the end of Drain’s (tsw), is long, it may not start up due to the OCP malfunction. To avoid it, select MOSFET or adjust resistance as tsw becomes less than 270nsec. GATE DRAIN Fig.15 14) IC pin input This monolithic IC contains P+ isolation and PCB layers between adjacent elements in order to keep them isolated. P/N junctions are formed at the intersection of these P layers with the N layers of other elements to create a variety of parasitic elements. For example, when a resistor and transistor are connected to pins as shown in following chart, ○the P/N junction functions as a parasitic diode when GND > (Pin A) for the resistor or GND > (Pin B) for the transistor (NPN). ○Similarly, when GND > (Pin B) for the transistor (NPN), the parasitic diode described above combines with the N layer of other adjacent elements to operate as a parasitic NPN transistor. The formation of parasitic elements as a result of the relationships of the potentials of different pins is an inevitable result of the IC's architecture. The operation of parasitic elements can cause interference with circuit operation as well as IC malfunction and damage. For these reasons, it is necessary to use caution so that the IC is not used in a way that will trigger the operation of parasitic elements, such as by the application of voltages lower than the GND (PCB) voltage to input and output pins. Resistor (PINA) (PINB) C B E (PINB) (PINA) P N P + tsw Transistor (NPN) P N P + P N + P N P substrate GND P + B N C E GND Parasitic element Parasitic element GND Parasitic element or transistor Parasitic element or transistor Fig.16 www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 12/14 2011.05 - Rev.A BD9775FV ●Thermal Derating Curve 1.0 Technical Note ②0.85 0.8 Power Dissipation : Pd （ W) 0.6 ①0.64 0.4 0.2 ①With no heat sink ②Copper laminate area 70 mm×70mm 0.0 0 25 50 75 100 125 150 Ambient Temperature: Ta(℃) Fig.17 www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 13/14 2011.05 - Rev.A BD9775FV ●Ordering part number Technical Note B D 9 Part No. 7 7 5 F V - E 2 Part No. Package FV: SSOP-B28 Packaging and forming specification E2: Embossed tape and reel SSOP-B28 10 ± 0.2 (MAX 10.35 include BURR) 28 15 Tape Quantity Direction of feed 0.3Min. Embossed carrier tape 2000pcs E2 The direction is the 1pin of product is at the upper left when you hold 7.6 ± 0.3 5.6 ± 0.2 ( reel on the left hand and you pull out the tape on the right hand ) 1 14 1.15 ± 0.1 0.15 ± 0.1 0.1 0.1 0.65 0.22 ± 0.1 1pin (Unit : mm) Direction of feed Reel ∗ Order quantity needs to be multiple of the minimum quantity. www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 14/14 2011.05 - Rev.A Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuelcontroller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law. Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact us. ROHM Customer Support System http://www.rohm.com/contact/ www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. R1120A