BD9855MWV

1/4 STURUCTURE Type PRODUCUT SERIES FEATURES Silicon Monolithic Integrated Circuit 4 Channel Switching Regulator control system for DSC BD9855MWV THYSICAL DIMENSIONS Package(Plastic Mold) Fig.1、Block Diagram Fig.2、Pin Description Fig.3 ●Include step-down 2ch,Cross converter 1ch,step down/inverting 1ch. ●Short Circuit Protection (SCP), Under Voltage Lockout Function (UVLO), Include external synchronous rectification operation ●Independent ON/OFF Function Each Channel、UQFN044V6060 Package（0.4mm pitch） ○Absolute Maximum Ratings（Ta=25℃） Parameter P o w e r S u p p l y Vo l t a g e Symbol VCC,PVCC BST1-LX1、BST2-LX2 LX31 Limits －0.3～15 －0.3～7 －0.3～15 －0.3～8.4 －0.3～15 －0.3～7 540(*1),1000(*2) －25～+85 －55～+150 150 Units V V V V V V mW ℃ ℃ ℃ Input Voltage Vo3,LX32 PG,SYNC, CTL1,2,3,4 SEL Power Dissipation Pd Topr Tstg Tjmax O p e r a t i n g Te m p e r a t u r e S t o r a g e Te m p e r a t u r e J u n c t i o n Te m p e r a t u r e (*1) Without external heat sink, the power dissipation degrades by 4.2mW/℃ above 25℃. (*2)Power dissipation degrades by 8.0mW/℃ above 25℃, when mounted on a PCB (70mm×70mm×1.6mm). ○Operating Conditions Parameter 【Input Voltage】 Power Supply Voltage 【Reference Output】 VREG,VREGA terminal capacitor VREF terminal capacitor 【Protect Circuit】 SCP terminal capacitor 【Oscillator】 Oscillator frequency OSC timming resistor RTSS terminal capacitor SYNC terminal input H SYNC terminal input L SYNC terminal input Duty 【Driver】 BST-Lx voltage BST-Lx capacitor LX31terminal input voltage CH3 output range PVCC1,2,4 terminal input voltage CH1,2,3output current Vbst Cbst VLX31 VVOUT3 PVCC1,2,4 Ioutch1,2,3 3.5 0.047 － 4.0 － － － 0.1 － － － － 5.5 0.22 14 7.0 14 1 V μF V V V A Fosc RT CRTSS VSYNCH VSYNCL Dsync 0.6 47 1000 3.0 -0.3 40 1.0 82 10000 50 1.5 120 － VCC 0.5 60 MHz CSCP 0.001 － 2.2 μF CVR* CVREF 0.47 0.047 1.0 0.1 2.2 2.2 μF μF VCC,PVCC 4 6 14 V Symbol MIN Spec. TYP MAX Unit Condition kΩ pF V V % ※)Please connect capacitor at input/output terminal (VCC,PVCC,VREF,VREG etc.) to operate IC stabilize. Status of this document The Japanese language version of this document shall be the official specification. Any translation of this document shall be for reference only. REV. C 2/4 ○Electrical Characteristics（Ta=25℃，VCC=PVCC=6V, RT=82kohm, CTL1～4=3V with no designation） Standard value TYP 5 2.5 3.6 0.1 2.2 5 0.5 10 1 0.5 84 92 1 -5 5 30 0.8 1 1 1 10 2 500 200 150 PVCC -0.5 0.5 250 200 150 PVCC -0.5 0.5 0.5 0 400 0 4 25 Parameter 【Internal Regulator】 Regulator Output voltage for Boost terminal Regulator Output Voltage for inside standard 【Under Voltage Lock Function】 Threshold Voltage１,2 Hysterisis voltage width 【Short Circuit Protection】 Timer Start Threshold Voltage SCP Out Source Voltage SCP Threshold Voltage Stand by Voltage 【Oscillator】 Frequency CH1～3 Frequency CH4 Max duty 1,2(Step Down) Max duty CH3 Lx31 Max duty CH3 Lx32 Max duty 4 RTSS Pin Standby Voltage RTSS Pin smk Current RTSS Pin source Current 【Error AMP】 Input Bias Current INV Threshold Voltage 1 NON_INVoffset Voltage 【Reference Voltage VREF】 VREF　Output Voltage Line Regulation Load Regulation Output Current when shorted 【Soft Start】 SS1,2,3,4　source current SS Discharge Resistance 【Output Driver】 CH1,2 Highside SW ON Resistance CH1,2 Highside SW ON Resistance CH3 Driver Output Voltage H CH3 Driver Output Voltage L CH3 Lx31Pin Lowside SW ON Resistance CH3 Lx32Pin Highside SW ON Resistance CH3 Lx32Pin Lowside SW ON Resistance CH4 Driver Output Voltage H CH4 Driver Output Voltage L 【PG Output Pin】 PG Pin ON Resistance PG Pin Leak Current 【Control terminal】 CTL terminal voltage(ON), CTL terminal voltage (OFF), SEL terminal voltage (? frequency) SEL terminal voltage (same frequency) CTL,SEL Pull down Resistance 【Circuit Current】 STAND-by Current Circuit Current（VCC,PVCC Pin Input Current） Circuit Current（Application Io=none） Symbol VREG VREGA Vstd1,2 Vhys1,2 Vtc Iscp1 Vtsc Vssc fosc123 Fosc4 Dmax1,2 Dmax31 Dmax32 Dmax4 RTSSF IRTSSI IRTSSO IINV VINV1 Voff VOREF DVLi DVLo Ios Iss RdisSS RON12p RON12N Vout3H Vout3L RON31N RON32p RON32N Vout4H Vout4L RonPG IlkPG VCTLH VCTLL VSELH VSELL RCTL,RSEL ISTB Icc Iccapl MIN 4.8 2.4 3.4 － 2.1 2.5 0.45 － 0.8 0.4 78 86 -7 3 0.79 0.99 2 1 PVCC-1.0 PVCC-1.0 2 -0.3 2 -0.3 250 - MAX 5.2 2.6 3.8 0.2 2.3 7.5 0.55 100 1.2 0.6 100 100 90 96 20 -3 7 100 0.81 5 1.01 7.5 7.5 3 1000 350 300 1 400 350 300 1 1 1 Vcc 0.8 7 0.8 700 5 8 35 Units V V V V V μA V mV MHz MHz % % % % mV μA μA nA V mV V mV mV mA μA Ω mΩ mΩ V V mΩ mΩ mΩ V V kΩ uA V V V V kΩ μA mA mA Ireg=1mA Ireg=1mA Conditions Test circuit VCCMonitor,VREGMonitor VCC cancel ,VREG cancel FB Pin Monitor VSCP=0.1V RT=82kΩ、SEL=GND RT=82kΩ、SEL=VREGA Vscp=0V ※ SEL=VREGA CTL1～4=0V INV1～4, NON4=0V CH1～3 NON4=1V, INV4=FB4 VCC=4.8～8.4V Iref=10μA～100μA Vref=0V VSCP=0.1V Vss=0.2V ILX=50mA ILX=-50mA IOUT3=50mA IOUT3=-50mA ILX=-50mA Vo3=6.0V, ILX=50mA ILX=-50mA IOUT4=50mA,INV4=1.1V IOUT4=-50mA,INV4=0.9V PG=1V PG=15V CTL1～4=0V INV=2.5V,NON=1V All CH ON ※The protective circuit start working when circuit is operated by 100% duty. So it is possible to use only for transition time shorter than charge time for SCP. ◎This product is not designed for normal operation with in a radioactive environment. REV. C 3/4 ○ Package BD9855 Lot No. Plastic Mold (UNIT：mm) Fig.1 ○ Block Diagram BST1 FB1 BST1 INV1 SS1 ERRORAMP1 ○ Pin Description BST1 PVCC1 Lx1 PGND12 BST2 + + CH1 Step Down (Current mode) FB2 INV2 SS2 ERRORAMP2 BST2 BST2 PVCC2 CH2 Step Down (Current mode) Lx2 + + OUT3 FB3 INV3 SS3 ERRORAMP3 PVCC4 Lx31 CH3 cross converter PGND3 Lx32 Vo3 + + FB4 INV4 NON4 ERRORAMP4 PVCC4 PWMCOMP4 + SS monitor + OUT4 SS4 VREF VREF SCP PGND4 + SCP TIMER LATCH latch PROTECTION TSD UVLO VCC VREGA VREG PG CH_CTL OSC OSC SYNC SYNC VREGA VREG latch CTL1 CTL2 CTL3 CTL4 RTSS RT SEL GND Fig.2 Fig.3 REV. C 4/4 ○Operation Notes 1.) Absolute maximum ratings Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may result in IC deterioration or damage. Assumptions should not be made regarding the state of the IC (short mode or open mode) when such damage is suffered. A physical safety measure such as a fuse should be implemented when use of the IC in a special mode where the absolute maximum ratings may be exceeded is anticipated. 2.) GND potential Ensure a minimum GND pin potential in all operating conditions. In addition, ensure that no pins other than the GND pin carry a voltage lower than or equal to the GND pin(except INV4 terminal), including during actual transient phenomena. 3.) Thermal design Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. 4.) Inter-pin shorts and mounting errors Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in damage to the IC. Shorts between output pins or between output pins and the power supply and GND pin caused by the presence of a foreign object may result in damage to the IC. 5.) Operation in a strong electromagnetic field Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction. 6.) Common impedance Power supply and ground wiring should reflect consideration of the need to lower common impedance and minimize ripple as much as possible (by making wiring as short and thick as possible or rejecting ripple by incorporating inductance and capacitance). 7.) Voltage of CTL pin The threshold voltages of CTL pin are 0.8V and 2.0V. STB state is set below 0.8V while action state is set beyond 2.0V. The region between 0.8V and 2.0V is not recommended and may cause improper operation. The rise and fall time must be under 10msec. In case to put capacitor to STB pin, it is recommended to use under 0.01μF. 8.) Thermal shutdown circuit (TSD circuit) This IC incorporates a built-in thermal shutdown circuit (TSD circuit). The TSD circuit is designed only to shut the IC off to prevent runaway thermal operation. Do not continue to use the IC after operating this circuit or use the IC in an environment where the operation of the thermal shutdown circuit is assumed. 9.) IC pin input This monolithic IC contains P+ isolation and PCB layers between adjacent elements in order to keep them isolated. P/N junctions are formed at the intersection of these P layers with the N layers of other elements to create a variety of parasitic elements. For example, when a resistor and transistor are connected to pins as shown in following chart,  the P/N junction functions as a parasitic diode when GND > (Pin A) for the resistor or GND > (Pin B) for the transistor (NPN).  Similarly, when GND > (Pin B) for the transistor (NPN), the parasitic diode described above combines with the N layer of other adjacent elements to operate as a parasitic NPN transistor. The formation of parasitic elements as a result of the relationships of the potentials of different pins is an inevitable result of the IC's architecture. The operation of parasitic elements can cause interference with circuit operation as well as IC malfunction and damage. For these reasons, it is necessary to use caution so that the IC is not used in a way that will trigger the operation of parasitic elements, such as by the application of voltages lower than the GND (PCB) voltage to input and output pins. Resistance （Pin A） （Pin B） C Transistor (NPN) ～ B E GND N P＋ N N P substrate Parasitic elementals Fig.4 N N N P substrate GND Parasitic elementals N GND Parasitic diode Simplified structure of a Bipolar IC REV. C ～ P P＋ P＋ P P＋ （PinＡ） Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. 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