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STRUCTURE NAME OF PRODUCT TYPE
Silicon Monolithic Integrated Circuit DC-AC Inverter Control IC
ＢＤ９８８２Ｆ, ＢＤ９８８２ＦＶ
・1ch control with Push-Pull ・Lamp current and voltage sense feed back control ・Sequencing easily achieved with Soft Start Control ・Short circuit protection with Timer Latch ・Under Voltage Lock Out ・Short circuit protection with over voltage ・Mode-selectable the operating or stand-by mode by stand-by pin ・Synchronous operating the other BD9882F or BD9882FV IC’s ・BURST mode controlled by PWM and DC input
FUNCTION
○Absolute Maximum Ratings（Ta = 25℃）
Parameter Supply Voltage Operating Temperature Range Storage Temperature Range Power Dissipation Maximum Junction Temperature
*1 *2
Symbol VCC Topr Tstg Pd Tjmax
Limits 15 -40～+95 -55～+125 550*1(BD9882F) 650*2(BD9882FV) +125
Unit V ℃ ℃ mW ℃
Pd derate at 5.5mW/℃ for temperature above Ta = 25℃ (When mounted on a PCB 70.0mm×70.0mm×1.6mm)
Pd derate at 6.5mW/℃ for temperature above Ta = 25℃ (When mounted on a PCB 70.0mm×70.0mm×1.6mm)
〇Recommended operating condition
Parameter Supply voltage CT oscillation frequency BCT oscillation frequency Symbol Vcc fCT fBCT Limits 5.0～14.0 20～150 0.10～0.50 Unit V kHz kHz
Status of this document The Japanese language version of this document shall be the official specification. Any translation of this document shall be for reference only.
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2/4 ○Electric Characteristics（Ta=25℃，VCC=7V）
Parameter （ （WHOLE DEVICE） ） Operating current Stand-by current （ （OVER VOLTAGE DETECT） ） FB over voltage detect voltage （ （STAND-BY CONTROL） ） Stand-by voltage H Stand-by voltage L （ （TIMER LATCH） ） Timer Latch voltage Timer Latch current （ （OSC BLOCK） ） OSC constant current OSC Max voltage OSC Min voltage MAX DUTY Soft start current IS COMP detect Voltage SS COMP detect voltage SRT ON resistance （ （UVLO BLOCK） ） Operating voltage Shut down voltage （ （FEED BACK BLOCK） ） IS threshold voltage VS threshold voltage IS source current 1 IS source current 2 VS source current （ （Output BLOCK） ） Output voltage Ｈ Output voltage L Output sink resistance Output source resistance Drive output frequency （ （BURST MODE） ） BOSC Max voltage BOSC Min Voltage BOSC constant current BOSC frequency （ （REG BLOCK） ） REG output voltage REG source current （ （COMP BLOCK） ） Over voltage detect Under voltage detect （ （FAIL PIN） ） Normal output voltage Protect output voltage Protect cancel voltage detect Symbol Icc1 Icc2 Vovf VstH VstL Vcp Icp ICT VoscH VoscL MAXDUTY Iss Visc Vss RSRT VuvloH VuvloL Vis Vvs Iis1 Iis2 Ivs VoutNH VoutNL RsinkN RsourceN FN VburH VburL Iburosc FBOSC VREG IREG VCOMPH VCOMPL VPH VPL VFAIL MIN. － － 2.20 1.8 -0.3 1.9 0.5 1.35/RT 1.8 0.3 44 1.0 0.45 2.0 － 4.000 3.800 1.225 1.220 － 13.0 － VCC-0.3 － － － 58.5 1.94 0.4 1.35/BRT 261 3.038 5.0 2.20 0.590 0.45 2.9 0.36 Limits TYP. 8 2 2.40 － － 2.0 1.0 1.5/RT 2.0 0.5 46.5 2.0 0.50 2.2 200 4.200 4.000 1.250 1.250 － 20.0 － VCC-0.1 0.1 8 10 60.0 2.0 0.5 1.5/BRT 275 3.100 － 2.5 0.640 0.5 3.1 0.40 MAX. 16 10 2.60 VCC 0.8 2.1 1.5 1.65/RT 2.2 0.7 49 3.0 0.55 2.4 400 4.400 4.200 1.275 1.280 1.5 27.0 1.0 － 0.3 16 20 61.5 2.06 0.6 1.65/BRT 289 3.162 － 2.80 0.690 0.55 3.3 0.44 Unit mA μA V V V V μA A V V % μA V V Ω V V V V μA μA μA V V Ω Ω kHz V V A Hz V mA V V V V V DUTY=2.0V DUTY=0V、IS=0.5V fCT=60kHz fCT=60kHz fCT=60kHz System ＯＮ System ＯＦＦ CT=0.5V Conditions
Isink = 10mA Isource = 10mA RT=18kΩ CT=400pF fBCT=0.2kHz fBCT=0.2kHz BRT=33kΩ BCT=0.051μF
（This product is not designed for normal operation with in a radio active environment.）
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〇Package Dimensions
Device Mark
(Include BURR 12.85)
BD9882F
BD9882FV
１
Lot No.
SOP20 (Unit:mm)
SSOP-B20 (Unit:mm)
〇Block Diagram
SS CT RT BRT BCT DUTY VCC
〇Pin Description
Pin No.
+
OSC BOSC
Pin Name DUTY BRT BCT RT SRT CT GND FB IS VS STB COMP REG SS SCP N2 PGND N1 FAIL Vcc
Function Control PWM mode and BURST mode External resistor from BRT to GND for adjusting the BURST triangle oscillator External capacitor from BCT to GND for adjusting the BURST triangle oscillator External resistor from SRT to RT for adjusting the triangle oscillator External resistor from SRT to RT for adjusting the triangle oscillator External capacitor from CT to GND for adjusting the triangle oscillator GROUND Error amplifier output Error amplifier input① Error amplifier input② Stand-by switch Under, over voltage detect Internal regulator output External capacitor from SS to GND for Soft Start Control External capacitor from SCP1 to GND for Timer Latch FET driver Ground for FET drivers FET driver Protect clock output Supply voltage input
-
1 2
STB
STB BLOCK
SYSTEM ON/OFF PWM BLOCK
FB
IS
+
F/B BLOCK VCC UVLO
LOGIC BLOCK
OUTPUT
N1 N2 PGND
3 4 5
BLOCK
VS
+
+
FAIL
6 7
VCC Reg BLOCK
8
VS IS PROTECT BLOCK
REG
9 10 11 12
GND
COMP
SCP
SRT
13 14 15 16 17 18 19 20
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〇NOTE FOR USE
１． When designing the external circuit, including adequate margins for variation between external devices and the IC.Use adequate margins for steady state and transient characteristics. ２． Recommended Operating Range The circuit functionality is guaranteed within of ambient temperature operation range as long as it is within recommended operating range. The standard electrical characteristic values cannot be guaranteed at other voltages in the operating ranges, however, the variation will be small. ３． Mounting failures, such as misdirection or miscounts, may harm the device. ４． A strong electromagnetic field may cause the IC to malfunction. ５. The GND pin should be the location within ±0.3V compared with the PGND pin
６． The BD9882F and BD9882FV incorporate a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is designed only to shut the IC off to prevent runaway thermal operation. It is not designed to protect the IC or guarantee its operation. Do not continue to use the IC after operating this circuit or use the IC in an environment where the operation of the thermal shutdown circuit is assumed. ７． Absolute maximum ratings are those values that, if exceeded, may cause the life of a device to become significantly shortened. Moreover, the exact failure mode caused by short or open is not defined. Physical countermeasures, such as a fuse, need to be considered when using a device beyond its maximum ratings. ８．About the external FET, the parasitic Capacitor may cause the gate voltage to change, when the drain voltage is switching. Make sure to leave adequate margin for this IC variation. ９． On operating Slow Start Control (SS is less than 2.2V), It does not operate Timer Latch. １０． By STB voltage, BD9882F and BD9882FV are changed to 2 states. Therefore, do not input STB pin voltage between one state and the other state (0.8～1.8V). １１．The pin connected a connector need to connect to the resistor for electrical surge destruction. １２．This IC is a monolithic IC which (as shown is Fig-1)has P+ substrate and between the various pins. A P-N junction is formed from this P layer of each pin. For example, the relation between each potential is as follows, ○(When GND > PinB and GND > PinA, the P-N junction operates as a parasitic diode.) ○(When PinB > GND > PinA, the P-N junction operates as a parasitic transistor.) Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits as well as operation faults and physical damage. Accordingly you must not
use methods by which parasitic diodes operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin.
(PinA) Resistance (PinB) C Transistor (NPN) B E GND P＋ P N P substrate GND Parasitic diode N P＋ P substrate GND Parasitic diode (PinB) (PinA) B Parasitic diode GND
Ｃ
Ｎ
Ｎ
N
N
Ｂ
CＣ EＥ GND
Other adjacent components
Parasitic diode
Fig-1 Simplified structure of a Bipolar IC
REV. A
Notice
Notes
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