BD9896FV-E2

1/4 STRUCTURE Silicon Monolithic Integrated Circuit NAME OF PRODUCT DC-AC Inverter Control IC TYPE ＢＤ９８９６ＦＶ FUNCTION ・2ch control with Push-Pull ・Lamp current and voltage sense feed back control ・Sequencing easily achieved with Soft Start Control ・Circuit protection with Timer Latch ・Under Voltage Lock Out ・Over Voltage Protection ・Mode-selectable the operating or stand-by mode by stand-by pin ・BURST mode controlled by PWM and DC input ・Output linear Controllable Analog dimming by external DC voltage ・Synchronous operating the other several BD9896FV IC’s ○Absolute Maximum Ratings（Ta = 25℃） Parameter Supply Voltage Operating Temperature Range Storage Temperature Range Power Dissipation Maximum Junction Temperature * Symbol VCC Topr Tstg Pd Tjmax Limits 15 -40～+90 -55～+150 1062* +150 Unit V ℃ ℃ mW ℃ Pd derated at 8.5mW/℃ for temperature above Ta = 25℃ (When mounted on a PCB 70.0mm×70.0mm×1.6mm) 〇Recommended operating condition Parameter Supply voltage Output oscillation frequency BCT oscillation frequency Symbol VCC fout fBCT Limits 6.0～14.0 25～90 0.05～1.00 Unit V kHz kHz Status of this document The Japanese version of this document is the official specification. Please use the translation version of this document as a reference to expedite understanding of the official version. If these are any uncertainty in translation version of this document, official version takes priority. REV. C 2/4 ○Electric Characteristics（Ta=25℃，VCC=7V） Parameter （（WHOLE DEVICE） ） Operating current Stand-by current （（OVER VOLTAGE DETECT）） FB over voltage detect voltage （（STAND BY CONTROL）） Stand-by voltage L Input voltage range of Slave setting Input voltage range of Master setting （（TIMER LATCH）） Timer Latch voltage Timer Latch current （（BURST MODE）） BOSC Max voltage BOSC Min Voltage BOSC constant current BOSC frequency （（OSC BLOCK）） MAX DUTY Soft start current IS COMP detect Voltage SS COMP detect voltage SRT ON resistance （（UVLO BLOCK）） Detect voltage (VCC_UVLO) Hysteresis width (VCC_UVLO) Operating voltage (UVLO) Hysteresis width (UVLO) （（REG BLOCK）） REG output voltage REG source current （（FEED BACK BLOCK）） IS threshold voltage ① IS threshold voltage ② VS threshold voltage IS source current 1 IS source current 2 VS source current VREF input voltage range （（OUTPUT BLOCK） ） NBｃｈ output voltage Ｈ NAｃｈ output voltageＨ NBｃｈ output voltage L NAｃｈ output voltage L NBｃｈ output sink resistance NBｃｈ output source resistance NAｃｈ output sink resistance NAｃｈ output source resistance Drive output frequency （（COMP BLOCK）） Overr voltage detect Hysteresis width (COMP) Symbol MIN. Limits TYP. MAX. Unit Icc1 Icc2 － － － － 17.0 10 mA μA Vovf 2.20 2.40 2.60 V VstL VstH1 VstH2 -0.3 1.8 2.55 － - 0.8 2.25 VCC V V V Vcp Icp 1.9 0.5 2.0 1.0 2.1 1.5 V μA VburH VburL IBCT fBCT 1.94 0.4 1.35/BRT 292.5 2.0 0.5 1.5/BRT 300 2.06 0.6 1.65/BRT 307.5 V V A Hz MAXDUTY Iss Visc Vssc RSRT 44 1.0 0.45 2.0 － 46.5 2.0 0.50 2.2 200 49 3.0 0.55 2.4 400 % μA V V Ω Vcc_vuvlo 5.100 5.300 5.500 V ⊿Vcc_vuvlo Vuvlo ⊿Vuvlo 0.150 2.260 0.075 0.200 2.340 0.100 0.250 2.420 0.125 V V V VREG IREG 3.038 5.0 3.100 － 3.162 － V mA Vis① Vis② Vvs Iis1 Iis2 Ivs 1.225 － 1.220 － 13.0 － 1.250 VREFIN 1.250 － 20.0 － 1.275 VIS① 1.280 1.5 27.0 1.0 V V V μA μA μA VREF IN 0.6 － 1.6 V VoutNBH VoutNAH VoutNBL VoutNAL RsinkNB RsourceNB RsinkNA RsourceNA fOUT VCC-0.3 VCC-0.3 － － － － － － 57.9 VCC-0.1 VCC-0.1 0.1 0.1 5 8 5 8 60.0 － － 0.3 0.3 10 16 10 16 62.1 V V V V Ω Ω Ω Ω KHz VCOMPH ⊿VCOMPH 2.4 0.040 2.5 0.060 2.6 0.080 V V （（PROTECT CLOCK）） FAIL-pin On resistor value R_FAIL － 200 400 （（ SYNCRO BLOCK）） CT_SYNC_IN_High input Voltage Range VCT_SYNC_IN_H 2.0 － VCC*0.8 CT_SYNC_IN_Low input Voltage Range VCT_SYNC_IN_L -0.3 － 1.5 CT_SYNC_IN Pull-up resistor RCT_SYNC_IN_pull_up 500 － － VCT_SYNC_IN CT_SYNC_IN Self-oscillation voltage VCC＊0.9 － VCC RCT_SYNC_OUT＿sink CT_SYNC_OUT sink resistor value － 150 300 RCT_SYNC_OUT＿source CT_SYNC_OUT source resistor value － 370 740 CT_SYNC_OUT_High output Voltage Range VCT_SYNC_OUT _H 2.8 3.1 3.4 CT_SYNC_OUT_Low output Voltage Range VCT_SYNC_OUT_L － － 0.5 SRT SYNC Exchange detect Voltage Vsrtc 0.5 0.8 1.1 （This product is not designed for normal operation with in a radio active environment.） REV. C Ω V V kΩ V Ω Ω V V V Conditions CT_SYNC_IN=Low CT_SYNC_IN=OPEN fBCT=0.3kHz fBCT=0.3kHz BRT=36kΩ BCT=0.048μF fout=60kHz VREF pin:OPEN,REG is shorted VREF pin is supplied DUTY=2.2V DUTY=0V、IS=0.5V Over 1.25V effective Isink = 10mA Isource = 10mA Isink = 10mA Isource = 10mA RT=15.94kΩ is not 3/4 〇Package Dimensions Device Mark BD9896FV １ Lot No. SSOP-B28 (Unit:mm) 〇Block Diagram VCC REG 〇Pin Description CT_SYNC_IN CT_SYNC_OUT REG Block RT OSC BRT BCT DUTY BOSC DUTY Block SYSTEM　ON/OFF STB STB Block CT Master/Slave VCC UVLO Block FB1 VS1 VCC F/B Block ① PWM Block ① SS CT LOGIC Block ① FB2 IS2 VS2 OUTPUT Block ① NA1 NB1 VCC F/B Block ② PWM Block ② SS CT 端子名 NA1 2 NB1 LOGIC Block OUTPUT Block ② CP 4 REG 5 FAIL Protect clock output 6 VREF Reference voltage 7 CT_SYNC_OUT Output pin of CT synchronous signal 8 CT_SYNC_IN 9 RT 10 SRT 11 GND 12 BCT 13 BRT 14 DUTY Input pin of CT synchronous signal External resistor from SRT to RT for adjusting the triangle oscillator External resistor from SRT to RT for adjusting the triangle oscillator GROUND External capacitor from BCT to GND for adjusting the BURST triangle oscillator External resistor from BRT to GND for adjusting the BURST triangle oscillator Control PWM mode and BURST mode VREF PGND GND PROTECT Block COMP CP FAIL SRT REV. C 能 3 NA2 NB2 機 FET driver for 1ch FET driver for 1ch External capacitor from CP to GND for Timer Latch Internal regulator output UVLO SS IS1 端子番号 1 15 STB Stand-by switch, Master/Slave selection 16 VS2 Error amplifier input④ 17 IS2 Error amplifier input③ 18 FB2 Error amplifier output② 19 VS1 Error amplifier input② 20 IS1 Error amplifier input① 21 FB1 22 SS 23 COMP Error amplifier output① External capacitor from SS to GND for Soft Start Control Over voltage detector 24 VCC Supply voltage input 25 UVLO External Under Voltage Lock OUT 26 NB2 FET driver for 2ch 27 NA2 FET driver for 2ch 28 PGND Ground for FET drivers 4/4 〇NOTE FOR USE １． When designing the external circuit, including adequate margins for variation between external devices and the IC.Use adequate margins for steady state and transient characteristics. ２． Recommended Operating Range The circuit functionality is guaranteed within of ambient temperature operation range as long as it is within recommended operating range. The standard electrical characteristic values cannot be guaranteed at other voltages in the operating ranges, however, the variation will be small. ３． Mounting Failures Mounting failures, such as misdirection or miscounts, may harm the device. ４． Electromagnetic Fields A strong electromagnetic field may cause the IC to malfunction. ５. The GND pin should be the location within ±0.3V compared with the PGND pin ６． BD9896FV has the short circuit protection with Thermal Shut Down System. When STB or Vcc pin re-supplied, They enables to cancel the latch. If It rise the temperature of the chip more than 170℃(TYP), It make the external FET OFF ７． Absolute maximum ratings are those values that, if exceeded, may cause the life of a device to become significantly shortened. Moreover, the exact failure mode caused by short or open is not defined. Physical countermeasures, such as a fuse, need to be considered when using a device beyond its maximum ratings. ８． About the external FET, the parasitic Capacitor may cause the gate voltage to change, when the drain voltage is switching. Make sure to leave adequate margin for this IC variation. ９． On operating Slow Start Control (SS is less than 2.2V), It does not operate Timer Latch. １０． By STB voltage, BD9896FV is changed to 3 states. Therefore, do not input STB pin voltage between one state and the other state (0.8～1.8, 2.25～2.55). １１．The pin connected a connector need to connect to the resistor for electrical surge destruction. １２．This IC is a monolithic IC which (as shown is Fig-1)has P+ substrate and between the various pins. A P-N junction is formed from this P layer of each pin. For example, the relation between each potential is as follows, ○(When GND > PinB and GND > PinA, the P-N junction operates as a parasitic diode.) ○(When PinB > GND > PinA, the P-N junction operates as a parasitic transistor.) Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits as well as operation faults and physical damage. Accordingly you must not use methods by which parasitic diodes operate, such as applying a voltage that is lower than the GND(P substrate)voltage to an input Transistor (NPN) Resistance pin. (PinA) B (PinB) E C Ｃ GND P P＋ N P＋ N Ｎ N Ｎ P substrate GND Parasitic diode N P substrate GND Parasitic diode (PinB) (PinA) B CＣ Ｂ EＥ Parasitic diode GND GND Other adjacent components Parasitic diode Fig-1 Simplified structure of a Bipolar IC REV. C Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. 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