Nano Pulse ControlTM
Datasheet
4.5 V to 36 V Input, 5 A Integrated MOSFET
Single Synchronous Buck DC/DC Converter
BD9F500QUZ
Key Specifications
General Description
BD9F500QUZ is a synchronous buck DC/DC converter
with built-in low on-resistance power MOSFETs. It is
capable of providing current up to 5 A. It features fast
transient response due to Constant On-Time control
system. The Light Load Mode control improves efficiency in
light-load conditions. It is ideal for reducing standby power
consumption of equipment. Power Good function makes it
possible for system to control sequence. It achieves the
high power density and offer a small footprint on the PCB
by employing small package.
Input Voltage Range:
4.5 V to 36 V
Output Voltage Range:
0.6 V to 14 V
Output Current:
5 A (Max)
Switching Frequency: 600 kHz, 1 MHz, 2.2 MHz (Typ)
High-Side FET ON Resistance:
40 mΩ (Typ)
Low-Side FET ON Resistance:
22 mΩ (Typ)
Shutdown Current:
2 μA (Typ)
Operating Quiescent Current:
20 μA (Typ)
Package
VMMP16LZ3030
W (Typ) x D (Typ) x H (Max)
3.0 mm x 3.0 mm x 0.40 mm
Features
Single Synchronous Buck DC/DC Converter
Constant On-Time Control
Light Load Mode Control
Adjustable Soft Start
Power Good Output
Nano Pulse Control™
Output Capacitor Discharge Function
Over Voltage Protection (OVP)
Over Current Protection (OCP)
Short Circuit Protection (SCP)
Thermal Shutdown Protection (TSD)
Under Voltage Lockout Protection (UVLO)
VMMP16LZ3030 Package
Backside Heat Dissipation, 0.5 mm Pitch
VMMP16LZ3030
Applications
Step-down Power Supply for SoC, FPGA,
Microprocessor
Printer (MFP / LBP / IJP / POS)
OA Equipment
Laptop PC
USB Type-C Applications
Typical Application Circuit
BD9F500QUZ
EN
PGD
VEN
VIN
VIN
BOOT
0.1 μF
CIN
VOUT
PGND
VSEL1
VSEL2
L
SEL1
CFB
SEL2
VREG
CREG
SW
SS
R1
COUT
FB
AGND
R2
Nano Pulse Control™ is a trademark or a registered trademark of ROHM Co., Ltd.
〇Product structure : Silicon integrated circuit
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〇This product has no designed protection against radioactive rays.
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Pin Configuration
VIN
VIN
EN
AGND
(TOP VIEW)
16
15
14
13
12
FB
1
PGND
2
PGND
3
10
SEL2
PGND
4
9
SEL1
SW
VIN
PGND
6
7
PGD
8
SS
5
BOO T
18
SW
17
11 VREG
Pin Descriptions
Pin No.
Pin Name
1-4
PGND
5, 17
SW
Switch pin. This pin is connected to the source of the High-Side FET and the drain of the
Low-Side FET. Connect a bootstrap capacitor of 0.1 µF between this pin and the BOOT pin.
In addition, connect an inductor considering the direct current superimposition characteristic.
6
BOOT
Pin for bootstrap. Connect a bootstrap capacitor of 0.1 µF between this pin and the SW pin.
The voltage of this pin is the gate drive voltage of the High-Side FET.
7
PGD
Power Good pin. This pin is an open drain output that requires a pull-up resistor. See
Function Explanations (4) Power Good for setting the resistance. If not used, this pin can be
left floating or connected to the ground.
8
SS
Pin for setting the soft start time of output voltage. The soft start time is 2 ms (Typ) when the
SS pin is open. A ceramic capacitor connected to the SS pin makes the soft start time more
than 2 ms. See Selection of Components Externally Connected 4. Soft Start Capacitor for
how to calculate the capacitance.
9
SEL1
Pin for setting switching control mode. See Function Explanations (7) Control Mode
Selectable Function for how to control.
10
SEL2
Pin for setting switching control mode. See Function Explanations (7) Control Mode
Selectable Function for how to control.
11
VREG
Internal power supply output pin. This node supplies power 5.2 V (Typ) to other blocks which
are mainly responsible for the control function of the switching regulator. Connecting 2.2 µF
(Typ) ceramic capacitor is recommended.
12
FB
Output voltage feedback pin. See Selection of Components Externally Connected 3. Output
Voltage Setting, FB Capacitor for the output voltage setting.
13
AGND
14
EN
Enable pin. The device starts up with setting V EN to 1.2 V (Typ) or more. The device enters
the shutdown mode with setting VEN to 1.1 V (Typ) or less. This pin must be terminated.
VIN
Power supply pin. Connecting 0.1 µF (Typ) and 10 µF (Typ) ceramic capacitors is
recommended. The detail of a selection is described in Selection of Components Externally
Connected 1. Input Capacitor. Connecting to the PCB VIN pattern by using thermal vias
provides excellent heat dissipation characteristics. See PCB Layout Design for the detailed
PCB layout design.
15, 16,
18
Function
Ground pins for the output stage of the switching regulator.
Ground pin for the control circuit.
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Block Diagram
VREG
11
REG
HOCP
＋
－
15
16
18
EN
UVLO
VIN
EN 14
VREF
6
BOOT
5
SW
17
SW
TSD
Error Amplifier
SS 8
VIN
SS
＋
＋
－
Main Comparator
＋
－
On-Time
Control
Logic
VREG
SCP
OVP
FB 12
LOCP
＋
－
PGOOD
1
2
ZX/ROCP
FREQ
SEL1 9
SEL2
10
SELECTOR
OCP
PGND
3
＋
－
4
MODE
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7
13
PGD
AGND
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Description of Blocks
1.
VREF
This block generates the internal reference voltage.
2.
REG
This block generates the internal power supply.
3.
Soft Start
The Soft Start circuit slows down the rise of output voltage during start-up and controls the current, which allows the
prevention of output voltage overshoot and inrush current. The internal soft start time is 2 ms (Typ) when the SS pin is
open. A capacitor connected to the SS pin makes the rising time more than 2 ms.
4.
Error Amplifier
The Error Amplifier adjusts the Main Comparator input voltage to make the internal reference voltage equal to FB
voltage.
5.
Main Comparator
The Main Comparator compares the Error Amplifier output voltage and FB voltage (VFB). When VFB becomes lower than
the Error Amplifier output voltage, the output turns high and reports to the On-Time block that the output voltage has
dropped below the control voltage.
6.
On-Time
This block generates On-Time. The designed On-Time is generated after the Main Comparator output turns high.
7.
PGOOD
The PGOOD block is for power good function. When the output voltage reaches within ±7 % (Typ) of the setting voltage,
the built-in open drain Nch MOSFET connected to the PGD pin is turned off and the PGD pin becomes Hi-Z (High
impedance). When the output voltage reaches outside ±10 % (Typ) of the setting voltage, the open drain Nch MOSFET
is turned on and PGD pin is pulled down with 500 Ω (Typ).
8.
UVLO
The UVLO block is for under voltage lockout protection. The device is shutdown when input voltage (VIN) falls to 4.0 V
(Typ) or less. The threshold voltage has the 200 mV (Typ) hysteresis.
9.
TSD
The TSD block is for thermal protection. The device is shutdown when the junction temperature Tj reaches to 175 °C
(Typ) or more. The device is automatically restored to normal operation with a hysteresis of 25 °C (Typ) when the Tj
goes down.
10. OVP
The OVP block is for output over voltage protection. When the FB voltage (VFB) exceeds 120 % (Typ) or more of FB
threshold voltage VFBTH, the SW pin is pulled down with 400 Ω (Typ). After VFB falls 115 % (Typ) or less of VFBTH, the
device is returned to normal operation condition.
11. HOCP
This block is for over current protection of the High-Side FET. When the current that flows through the High-Side FET
reaches the value of over current limit, it turns off the High-Side FET and turns on the Low-Side FET.
12. LOCP
This block is for over current protection of the Low-Side FET. While the current that flows through the Low-Side FET
over the value of over current limit, the condition that being turned on the Low-Side FET is continued.
13. SCP
This block is for short circuit protection. After soft start is completed and in condition where V FB is 90 % (Typ) of 0.6 V or
less, this block counts the number of times of which current flowing in the Low-Side FET reaches over current limit.
When 128 times is counted, the device is shutdown for 16 times of soft start time (Typ) and re-operates.
14. ZX/ROCP
The ZX/ROCP is a comparator that monitors the inductor current. When inductor current falls below 0 A (Typ) while the
Low-Side FET is on, it turns off the Low-Side FET (Light Load Mode). When the current that flows through the Low-Side
FET reaches the value of over current limit, it turns off the Low-Side FET (Fixed PWM Mode).
15. Control Logic
The Control Logic controls the switching operation and protection function operation.
16. SELECTOR
This block controls switching frequency, maximum output current, and operating mode.
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Absolute Maximum Ratings (Ta = 25 °C)
Parameter
Input Voltage
SW Voltage
Symbol
Rating
Unit
VIN
-0.3 to +39
V
VSW
-0.3 to VIN + 0.3
V
SW Voltage (3 ns pulse width)
VSWAC1
-2 to VIN + 0.3
V
SW Voltage (30 ns pulse width)
VSWAC2
-1 to VIN + 0.3
V
Voltage from GND to BOOT
Voltage from SW to BOOT
FB Voltage
VBOOT
-0.3 to +45
V
ΔVBOOT-SW
-0.3 to +7
V
VFB
-0.3 to +7
V
VREG Voltage
VVREG
-0.3 to +7
V
SEL1 Voltage
VSEL1
-0.3 to VVREG + 0.3
V
SEL2 Voltage
VSEL2
-0.3 to VVREG + 0.3
V
PGD Voltage
VPGD
-0.3 to +45
V
EN Voltage
VEN
-0.3 to +39
V
SS Voltage
VSS
-0.3 to +7
V
Output Current
IOUT
6
A
Tjmax
150
°C
Tstg
-55 to +150
°C
Maximum Junction Temperature
Storage Temperature Range
Caution 1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is
operated over the absolute maximum ratings.
Caution 2: Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in deterioration of the
properties of the chip. In case of exceeding this absolute maximum rating, design a PCB with thermal resistance taken into consideration by
increasing board size and copper area so as not to exceed the maximum junction temperature rating.
Thermal Resistance
(Note 1)
Parameter
Symbol
Thermal Resistance (Typ)
1s
(Note 3)
(Note 4)
2s2p
Unit
VMMP16LZ3030
Junction to Ambient
Junction to Top Characterization Parameter
(Note 2)
θJA
125.1
50.7
°C/W
ΨJT
12
8
°C/W
(Note 1) Based on JESD51-2A (Still-Air).
(Note 2) The thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside
surface of the component package.
(Note 3) Using a PCB board based on JESD51-3.
(Note 4) Using a PCB board based on JESD51-5, 7.
Layer Number of
Measurement Board
Single
Material
Board Size
FR-4
114.3 mm x 76.2 mm x 1.57 mmt
Top
Copper Pattern
Thickness
Footprints and Traces
70 μm
Layer Number of
Measurement Board
4 Layers
(Note 5)
Material
Board Size
FR-4
114.3 mm x 76.2 mm x 1.6 mmt
Top
2 Internal Layers
Thermal Via
Pitch
Diameter
1.20 mm
Φ0.30 mm
Bottom
Copper Pattern
Thickness
Copper Pattern
Thickness
Copper Pattern
Thickness
Footprints and Traces
70 μm
74.2 mm x 74.2 mm
35 μm
74.2 mm x 74.2 mm
70 μm
(Note 5) This thermal via connects with the copper pattern of all layers.
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Recommended Operating Conditions
Parameter
Input Voltage
Operating Temperature
Output Current
(Note 1)
(Note 1)(Note 2)
(Note 3)
Output Voltage Setting
Symbol
Min
Typ
Max
Unit
VIN
4.5
-
36.0
V
Topr
-40
-
+85
°C
0
-
5
A
0
-
3
A
0.6
-
14.0
V
IOUT
VOUT
(Note 1) Tj must be 150 °C or less under the actual operating environment. Life time is derated at junction temperature greater than 125 °C.
(Note 2) The maximum value of the output current is determined by the control mode selection.
(Note 3) The switching frequency is reduced as needed to always ensure a proper regulation at low duty and high duty cycles. Use under the condition of VOUT ≤
VIN × 0.8 [V].
Electrical Characteristics (Unless otherwise specified Ta = 25 °C, VIN = 12 V, VEN = 3 V)
Parameter
Symbol
Min
Typ
Max
Unit
Conditions
ISDN
-
2
10
µA
IQ
-
20
40
µA
UVLO Detection Threshold Voltage
VUVLO1
3.7
4.0
4.3
V
VEN = 0 V
IOUT = 0 A,
No switching
VIN falling
UVLO Release Threshold Voltage
VUVLO2
3.9
4.2
4.5
V
VIN rising
VUVLOHYS
100
200
400
mV
VENH
1.1
1.2
1.3
V
VEN rising
VEN falling
Input Supply
Shutdown Current
Operating Quiescent Current
UVLO Hysteresis Voltage
Enable
EN Threshold Voltage High
EN Threshold Voltage Low
EN Hysteresis Voltage
EN Input Current
VENL
1.0
1.1
1.2
V
VENHYS
50
100
200
mV
IEN
-
0
2
µA
VEN = 3 V
VVREG_SD
-
0
0.1
V
VEN = 0 V
VVREG
5.0
5.2
5.4
V
0.594
0.600
0.606
V
PWM mode
VREG
VREG Shutdown Voltage
VREG Output Voltage
Reference Voltage, Error Amplifier, Soft Start
FB Threshold Voltage
VFBTH
FB Input Current
IFB
-
-
100
nA
VFB = 0.6 V
Soft Start Time
tSS
1.4
2.0
2.6
ms
The SS pin is open.
Soft Start Charge Current
ISS
1.6
2.0
2.4
µA
-
VVREG
V
-
0.3
V
Control
SEL1, SEL2 High Level Voltage
VSELH
SEL1, SEL2 Low Level Voltage
VSELL
VVREG
-0.3
0
SEL1, SEL2 Input Current
ISEL
-
-
3
µA
On-Time1
tON1
-
458
-
ns
On-Time2
tON2
-
275
-
ns
tON3
-
125
-
ns
tMINON
-
48
-
ns
High-Side FET ON Resistance1
RONH1
-
40
80
mΩ
High-Side FET ON Resistance2
RONH2
-
65
130
mΩ
Low-Side FET ON Resistance1
RONL1
-
22
44
mΩ
VBOOT - VSW = 5 V,
IOUTMAX = 5 A setting
VBOOT - VSW = 5 V,
IOUTMAX = 3 A setting
IOUTMAX = 5 A setting
Low-Side FET ON Resistance2
RONL2
-
38
76
mΩ
IOUTMAX = 3 A setting
On-Time3
Minimum On-Time
(Note 4)
VOUT = 3.3 V, PWM mode,
600 kHz setting
VOUT = 3.3 V, PWM mode,
1 MHz setting
VOUT = 3.3 V, PWM mode,
2.2 MHz setting
SW (MOSFET)
(Note 4) No tested on outgoing inspection.
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Electrical Characteristics – continued (Unless otherwise specified Ta = 25 °C, VIN = 12 V, VEN = 3 V)
Parameter
Symbol
Min
Typ
Max
Unit
VPGDTHGR
90
93
96
%
VPGDTHGF
104
107
110
%
VPGDTHFR
107
110
113
%
VPGDTHFF
87
90
93
%
ILKPGD
-
0
1
µA
PGD MOSFET ON Resistance
RPGD
-
500
1000
Ω
Protection
Low-Side FET Over Current
(Note 1)
Detection Current 1
Low-Side FET Over Current
(Note 1)
Detection Current 2
ILOCP1
5.3
6.7
8.1
A
IOUTMAX = 5 A setting
ILOCP2
3.2
4.0
4.8
A
IOUTMAX = 3 A setting
Power Good
Power Good Rising
Threshold Voltage
Power Good Falling
Threshold Voltage
Power Fault Rising
Threshold Voltage
Power Fault Falling
Threshold Voltage
PGD Output Leakage Current
Conditions
VFB rising,
VPGDTHGR = VFB / VFBTH x 100
VFB falling,
VPGDTHGF = VFB / VFBTH x 100
VFB rising,
VPGDTHFR = VFB / VFBTH x 100
VFB falling,
VPGDTHFF = VFB / VFBTH x 100
VPGD = 5 V
(Note 1) No tested on outgoing inspection.
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Typical Performance Curves
10
40
Operating Quiescent Current : IQ [μA]
Shutdown Current : ISDN [μA]
VIN = 12 V
8
6
4
2
0
30
25
20
15
10
5
0
-40
-20
0
20
40
Temperature : Ta [°C]
60
80
-40
Figure 1. Shutdown Current vs Temperature
-20
0
20
40
Temperature : Ta [°C]
60
80
Figure 2. Operating Quiescent Current vs Temperature
4.5
1.3
VIN = 12 V
4.4
EN Threshold Voltage : VENH, VENL [V]
UVLO Threshold Voltage : VUVLO1, VUVLO2 [V]
VIN = 12 V
35
4.3
UVLO Release ( VIN rising)
4.2
4.1
UVLO Detection ( VIN falling)
4
3.9
3.8
3.7
1.25
VENH ( VEN rising)
1.2
1.15
VENL ( VEN falling)
1.1
1.05
1
-40
-20
0
20
40
Temperature : Ta [°C]
60
80
-40
Figure 3. UVLO Threshold Voltage vs Temperature
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-20
0
20
40
Temperature : Ta [°C]
60
80
Figure 4. EN Threshold Voltage vs Temperature
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Typical Performance Curves – continued
0.1
2
VREG Shutdown Voltage : VVREG_SD [V]
VIN = 12 V, VEN = 3 V
1.8
EN Input Current : IEN [μA]
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0.08
0.06
0.04
0.02
0
-40
-20
0
20
40
Temperature : Ta [°C]
60
80
-40
Figure 5. EN Input Current vs Temperature
-20
0
20
40
Temperature : Ta [°C]
60
80
Figure 6. VREG Shutdown Voltage vs Temperature
5.4
0.61
VIN = 12 V
5.3
5.25
5.2
5.15
5.1
0.606
0.604
0.602
0.6
0.598
0.596
0.594
5.05
0.592
5
0.59
-40
-20
0
20
40
Temperature : Ta [°C]
60
-40
80
Figure 7. VREG Output Voltage vs Temperature
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VIN = 12 V
0.608
FB Threshold Voltage : VFBTH [V]
5.35
VREG Output Voltage : VVREG [V]
VIN = 12 V
-20
0
20
40
60
Temperature : Ta [°C]
80
Figure 8. FB Threshold Voltage vs Temperature
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Typical Performance Curves – continued
100
2.6
VIN = 12 V
2.4
Soft Start Time : tSS [ms]
80
FB Input Current : IFB [nA]
VIN = 12 V
2.5
60
40
20
2.3
2.2
2.1
2
1.9
1.8
1.7
1.6
1.5
1.4
0
-40
-20
0
20
40
Temperature : Ta [°C]
60
-40
80
Figure 9. FB Input Current vs Temperature
SEL1, SEL2 High Threshold Voltage : VSELH [V]
Soft Start Charge Current : ISS [μA]
VIN = 12 V
2.3
2.2
2.1
2
1.9
1.8
1.7
1.6
-20
0
20
40
Temperature : Ta [°C]
60
80
60
80
5.2
VIN = 12 V, VVREG = 5.2 V (Typ)
5.1
5
4.9
4.8
4.7
4.6
4.5
4.4
4.3
4.2
4.1
4
-40
Figure 11. Soft Start Charge Current vs Temperature
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0
20
40
Temperature : Ta [°C]
Figure 10. Soft Start Time vs Temperature
2.4
-40
-20
-20
0
20
40
Temperature : Ta [°C]
60
80
Figure 12. SEL1, SEL2 High Threshold Voltage vs
Temperature
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Typical Performance Curves – continued
3
VIN = 12 V
0.9
VSEL1, VSEL2 = 0 V
SEL1, SEL2 Input Current : ISEL [μA]
SEL1, SEL2 Low Threshold Voltage : VSELL [V]
1
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-40
-20
0
20
40
Temperature : Ta [°C]
60
VSEL1, VSEL2 = 5.25 V
2.5
2
1.5
1
0.5
0
-0.5
80
-40
Figure 13. SEL1, SEL2 Low Threshold Voltage vs
Temperature
-20
0
20
40
Temperature : Ta [°C]
60
80
Figure 14. SEL1, SEL2 Input Current vs Temperature
VIN = 12 V
High-Side FET ON Resistance2 : RONH2 [mΩ]
High-Side FET ON Resistance1 : RONH1 [mΩ]
80
70
60
50
40
30
20
10
0
-40
-20
0
20
40
Temperature : Ta [°C]
60
100
80
60
40
20
0
80
-40
Figure 15. High-Side FET ON Resistance1 vs Temperature
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VIN = 12 V
120
-20
0
20
40
Temperature : Ta [°C]
60
80
Figure 16. High-Side FET ON Resistance2 vs Temperature
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Typical Performance Curves – continued
80
Low-Side FET ON Resistance2 : RONL2 [mΩ]
Low-Side FET ON Resistance1 : RONL1 [mΩ]
50
VIN = 12 V
45
40
35
30
25
20
15
10
5
0
60
50
40
30
20
10
0
-40
-20
0
20
40
Temperature : Ta [°C]
60
80
-40
Figure 17. Low-Side FET ON Resistance1 vs Temperature
-20
0
20
40
Temperature : Ta [°C]
60
80
Figure 18. Low-Side FET ON Resistance2 vs Temperature
0.72
1.2
0.69
1.15
Switching Frequency : fSW [MHz]
Switching Frequency : fSW [MHz]
VIN = 12 V
70
0.66
0.63
0.6
0.57
0.54
0.51
1.1
1.05
1
0.95
0.9
0.85
0.48
-40
-20
0
20
40
Temperature : Ta [°C]
60
0.8
80
-40
Figure 19. Switching Frequency vs Temperature
(VIN = 12 V, VOUT = 3.3 V, IOUT = 2 A,
600 kHz_IOUTMAX = 5 A_PWM setting)
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-20
0
20
40
Temperature : Ta [°C]
60
80
Figure 20. Switching Frequency vs Temperature
(VIN = 12 V, VOUT = 3.3 V, IOUT = 2 A,
1 MHz_IOUTMAX = 5 A_PWM setting)
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Typical Performance Curves – continued
Power Good / Fault Threshold Voltage : VPGDTH [%]
2.6
Switching Frequency : fSW [MHz]
2.5
2.4
2.3
2.2
2.1
2
1.9
1.8
-40
-20
0
20
40
Temperature : Ta [°C]
60
80
VIN = 12 V
Power Fault (VFB rising)
110
105
Power Good (VFB falling)
100
95
Power Good (VFB rising)
90
Power Fault (VFB falling)
85
-40
Figure 21. Switching Frequency vs Temperature
(VIN = 12 V, VOUT = 3.3 V, IOUT = 2 A, 2.2 MHz setting)
-20
0
20
40
Temperature : Ta [°C]
60
80
Figure 22. Power Good / Fault Threshold Voltage vs
Temperature
1
1000
VIN = 12 V
0.9
PGD MOSFET ON Resistance : RPGD [Ω]
PGD Output Leakage Current : ILKPGD [μA]
115
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-40
-20
0
20
40
Temperature : Ta [°C]
60
800
700
600
500
400
300
200
100
0
80
-40
Figure 23. PGD Output Leakage Current vs Temperature
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TSZ22111 • 15 • 001
VIN = 12 V
900
-20
0
20
40
60
Temperature : Ta [°C]
80
Figure 24. PGD MOSFET ON Resistance vs Temperature
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Typical Performance Curves – continued
Time: 50 ms/div
Time: 1 ms/div
VIN: 5 V/div
VIN: 5 V/div
VEN: 3 V/div
VEN: 3 V/div
VOUT: 2 V/div
VOUT: 2 V/div
VPGD: 5 V/div
VPGD: 5 V/div
Figure 25. Start-up at No Load: VEN = 0 V to 5 V
(VIN = 12 V, VOUT = 3.3 V, CSS = OPEN,
1 MHz_IOUTMAX = 5 A_LLM setting)
Figure 26. Shutdown at No Load: VEN = 5 V to 0 V
(VIN = 12 V, VOUT = 3.3 V, CSS = OPEN,
1 MHz_IOUTMAX = 5 A_LLM setting)
Time: 1 ms/div
Time: 1 ms/div
VIN: 5 V/div
VIN: 5 V/div
VEN: 3 V/div
VEN: 3 V/div
VOUT: 2 V/div
VOUT: 2 V/div
VPGD: 5 V/div
VPGD: 5 V/div
Figure 27. Start-up at RLOAD = 0.66 Ω: VEN = 0 V to 5 V
(VIN = 12 V, VOUT = 3.3 V, CSS = OPEN,
1 MHz_IOUTMAX = 5 A_LLM setting)
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TSZ22111 • 15 • 001
Figure 28. Shutdown at RLOAD = 0.66 Ω: VEN = 5 V to 0 V
(VIN = 12 V, VOUT = 3.3 V, CSS = OPEN,
1 MHz_IOUTMAX = 5 A_LLM setting)
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100
100
95
95
90
90
85
85
80
80
Efficiency [%]
Efficiency [%]
Typical Performance Curves – continued
75
70
65
55
65
55
VOUT = 5 V
50
VOUT = 1.0 V
40
0
10
Figure 29. Efficiency vs Output Current
(VIN = 12 V, 600 kHz_IOUTMAX = 5 A_LLM setting)
1
2
3
Output Current : IOUT [A]
4
5
Figure 30. Efficiency vs Output Current
(VIN = 12 V, 600 kHz_IOUTMAX = 5 A_PWM setting)
100
95
95
90
90
85
85
80
80
Efficiency [%]
100
75
70
65
75
70
65
60
60
55
55
VOUT = 5 V
50
VOUT = 1.0 V
40
0
10
Figure 31. Efficiency vs Output Current
(VIN = 24 V, 600 kHz_IOUTMAX = 5 A_LLM setting)
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VOUT = 3.3 V
45
VOUT = 1.0 V
0.01
0.1
1
Output Current : IOUT [A]
VOUT = 5 V
50
VOUT = 3.3 V
45
40
0.001
VOUT = 3.3 V
45
VOUT = 1.0 V
0.01
0.1
1
Output Current : IOUT [A]
VOUT = 5 V
50
VOUT = 3.3 V
45
Efficiency [%]
70
60
60
40
0.001
75
1
2
3
4
Output Current : IOUT [A]
5
Figure 32. Efficiency vs Output Current
(VIN = 24 V, 600 kHz_IOUTMAX = 5 A_PWM setting)
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100
100
95
95
90
90
85
85
80
80
Efficiency [%]
Efficiency [%]
Typical Performance Curves – continued
75
70
65
65
55
55
VOUT = 5 V
50
0
10
95
90
90
85
85
80
80
Efficiency [%]
100
95
75
70
65
5
65
55
55
50
VOUT = 5 V
VOUT = 5 V
45
VOUT = 3.3 V
VOUT = 3.3 V
40
0
10
Figure 35. Efficiency vs Output Current
(VIN = 24 V, 1 MHz_IOUTMAX = 5 A_LLM setting)
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4
70
60
0.01
0.1
1
Output Current : IOUT [A]
2
3
Output Current : IOUT [A]
75
60
40
0.001
1
Figure 34. Efficiency vs Output Current
(VIN = 12 V, 1 MHz_IOUTMAX = 5 A_PWM setting)
100
45
VOUT = 1.0 V
40
Figure 33. Efficiency vs Output Current
(VIN = 12 V, 1 MHz_IOUTMAX = 5 A_LLM setting)
50
VOUT = 3.3 V
45
VOUT = 1.0 V
0.01
0.1
1
Output Current : IOUT [A]
VOUT = 5 V
50
VOUT = 3.3 V
45
Efficiency [%]
70
60
60
40
0.001
75
1
2
3
4
Output Current : IOUT [A]
5
Figure 36. Efficiency vs Output Current
(VIN = 24 V, 1 MHz_IOUTMAX = 5 A_PWM setting)
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100
95
95
90
90
85
85
80
80
Efficiency [%]
Efficiency [%]
Typical Performance Curves – continued
75
70
65
55
65
55
VOUT = 5 V
50
VOUT = 1.0 V
40
0
10
Figure 37. Efficiency vs Output Current
(VIN = 12 V, 600 kHz_IOUTMAX = 3 A_LLM setting)
1
2
Output Current : IOUT [A]
3
Figure 38. Efficiency vs Output Current
(VIN = 12 V, 600 kHz_IOUTMAX = 3 A_PWM setting)
100
95
95
90
90
85
85
80
80
Efficiency [%]
100
75
70
65
75
70
65
60
60
55
55
VOUT = 5 V
50
VOUT = 1.0 V
40
0
10
Figure 39. Efficiency vs Output Current
(VIN = 24 V, 600 kHz_IOUTMAX = 3 A_LLM setting)
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VOUT = 3.3 V
45
VOUT = 1.0 V
0.01
0.1
1
Output Current : IOUT [A]
VOUT = 5 V
50
VOUT = 3.3 V
45
40
0.001
VOUT = 3.3 V
45
VOUT = 1.0 V
0.01
0.1
1
Output Current : IOUT [A]
VOUT = 5 V
50
VOUT = 3.3 V
45
Efficiency [%]
70
60
60
40
0.001
75
1
2
Output Current : IOUT [A]
3
Figure 40. Efficiency vs Output Current
(VIN = 24 V, 600 kHz_IOUTMAX = 3 A_PWM setting)
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100
100
95
95
90
90
85
85
80
80
Efficiency [%]
Efficiency [%]
Typical Performance Curves – continued
75
70
65
55
65
55
VOUT = 5 V
50
VOUT = 3.3 V
45
VOUT = 1.0 V
VOUT = 1.0 V
40
0.01
0.1
1
Output Current : IOUT [A]
0
10
Figure 41. Efficiency vs Output Current
(VIN = 12 V, 1 MHz_IOUTMAX = 3 A_LLM setting)
95
90
90
85
85
80
80
Efficiency [%]
100
95
75
70
65
70
65
60
55
55
50
VOUT = 5 V
45
VOUT = 3.3 V
40
0
10
Figure 43. Efficiency vs Output Current
(VIN = 24 V, 1 MHz_IOUTMAX = 3 A_LLM setting)
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VOUT = 5 V
45
VOUT = 3.3 V
0.01
0.1
1
Output Current : IOUT [A]
3
75
60
50
1
2
Output Current : IOUT [A]
Figure 42. Efficiency vs Output Current
(VIN = 12 V, 1 MHz_IOUTMAX = 3 A_PWM setting)
100
40
0.001
VOUT = 5 V
50
VOUT = 3.3 V
45
Efficiency [%]
70
60
60
40
0.001
75
1
2
Output Current : IOUT [A]
3
Figure 44. Efficiency vs Output Current
(VIN = 24 V, 1 MHz_IOUTMAX = 3 A_PWM setting)
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Typical Performance Curves – continued
3.4
100
95
90
Output Voltage : VOUT [V]
85
Efficiency [%]
80
75
70
65
60
55
50
3.3
3.25
Fixed PWM Mode
VIN = 24 V
45
Light Load Mode
VIN = 12 V
3.2
40
0
1
2
Output Current : IOUT [A]
0
3
Figure 45. Efficiency vs Output Current
(VOUT = 3.3 V, 2.2 MHz setting)
1
2
3
4
Output Current : IOUT [A]
5
Figure 46. Load Regulation
(VIN = 12 V, VOUT = 3.3 V, 600 kHz_IOUTMAX = 5 A setting)
3.4
3.4
3.35
3.35
Output Voltage : VOUT [V]
Output Voltage : VOUT [V]
3.35
3.3
3.25
3.3
3.25
Fixed PWM Mode
Light Load Mode
3.2
3.2
0
1
2
3
4
Output Current : IOUT [A]
0
5
Figure 47. Load Regulation
(VIN = 12 V, VOUT = 3.3 V, 1 MHz_IOUTMAX = 5 A setting)
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1
2
Output Current : IOUT [A]
3
Figure 48. Load Regulation
(VIN = 12 V, VOUT = 3.3 V, 2.2 MHz setting)
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Typical Performance Curves – continued
0.8
1.2
1.1
Switching Frequency : fSW [MHz]
Switching Frequency : fSW [MHz]
0.7
0.6
0.5
0.4
0.3
0.2
Fixed PWM Mode
0.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
Fixed PWM Mode
0.1
Light Load Mode
Light Load Mode
0
0
0
1
2
3
Output Current : IOUT [A]
4
5
0
Figure 49. Switching Frequency vs Output Current
(VIN = 12 V, VOUT = 3.3 V, 600 kHz_IOUTMAX = 5 A setting)
1
2
3
Output Current : IOUT [A]
4
5
Figure 50. Switching Frequency vs Output Current
(VIN = 12 V, VOUT = 3.3 V, 1 MHz_IOUTMAX = 5 A setting)
3.4
2.6
2.4
Output Voltage : VOUT [V]
Switching Frequency : fSW [MHz]
2.5
2.3
2.2
2.1
2
3.35
3.3
3.25
1.9
1.8
3.2
0
1
2
Output Current : IOUT [A]
3
4
Figure 51. Switching Frequency vs Output Current
(VIN = 12 V, VOUT = 3.3 V, 2.2 MHz setting)
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8
12
16
20
24
28
Input Voltage : VIN [V]
32
36
Figure 52. Line Regulation
(VOUT = 3.3 V, IOUT = 2 A,
600 kHz_IOUTMAX = 5 A_PWM setting)
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3.4
3.4
3.35
3.35
Output Voltage : VOUT [V]
Output Voltage : VOUT [V]
Typical Performance Curves – continued
3.3
3.25
3.3
3.25
3.2
3.2
4
8
12
16
20
24
28
Input Voltage : VIN [V]
32
4
36
12
16
20
24
28
Input Voltage : VIN [V]
32
36
Figure 54. Line regulation
(VOUT = 3.3 V, IOUT = 1 A, 2.2 MHz setting)
0.72
1.2
0.69
1.15
Switching Frequency : fSW [MHz]
Switching Frequency : fSW [MHz]
Figure 53. Line Regulation
(VOUT = 3.3 V, IOUT = 2 A, 1 MHz_IOUTMAX = 5 A_PWM setting)
8
0.66
0.63
0.6
0.57
0.54
0.51
1.1
1.05
1
0.95
0.9
0.85
0.48
0.8
4
8
12
16
20
24
28
Input Voltage : VIN [V]
32
Figure 55. Switching Frequency vs Input Voltage
(VOUT = 3.3 V, IOUT = 2 A,
600 kHz_IOUTMAX = 5 A_PWM setting)
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36
4
8
12
16
20
24
28
Input Voltage : VIN [V]
32
36
Figure 56. Switching Frequency vs Input Voltage
(VOUT = 3.3 V, IOUT = 2 A, 1 MHz_IOUTMAX = 5 A_PWM setting)
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Typical Performance Curves – continued
6.5
2.6
6
VIN = 24 V
5.5
VIN = 12 V
5
2.4
Output Current : IOUT [A]
Switching Frequency : fSW [MHz]
2.5
2.3
2.2
2.1
2
4.5
4
3.5
3
2.5
2
1.5
1
1.9
0.5
1.8
4
8
12
16
20
24
28
Input Voltage : VIN [V]
32
0
36
-60
-20
0
20
40
60
Temperature : Ta [°C]
80
100
(Note 1)
Figure 58. Output Current vs Temperature
Operating Range: Tj < 150 °C (VOUT = 3.3 V, 600 kHz setting)
Figure 57. Switching Frequency vs Input Voltage
(VOUT = 3.3 V, IOUT = 1 A, 2.2 MHz setting)
6.5
4
VIN = 24 V
6
VIN = 24 V
3.5
VIN = 12 V
5.5
Output Current : IOUT [A]
5
Output Current : IOUT [A]
-40
4.5
4
3.5
3
2.5
2
1.5
1
VIN = 12 V
3
2.5
2
1.5
1
0.5
0.5
0
0
-60
-40
-20
0
20
40
60
Temperature : Ta [°C]
80
(Note 1)
100
Figure 59. Output Current vs Temperature
Operating Range: Tj < 150 °C (VOUT = 3.3 V, 1 MHz setting)
-60
-40
-20
0
20
40
60
Temperature : Ta [°C]
80
100
(Note 1)
Figure 60. Output Current vs Temperature
Operating Range: Tj < 150 °C (VOUT = 3.3 V, 2.2 MHz setting)
(Note 1) Measured on FR-4 board 85 mm x 85 mm, Copper Thickness: Top and Bottom 70 μm, 2 Internal Layers 35 μm.
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BD9F500QUZ
Function Explanations
1. Basic Operation
(1) DC/DC Converter Operation
BD9F500QUZ is a synchronous rectifying step-down switching regulator that has original On-Time control method.
Device operates as the SEL1 pin and the SEL2 pin setting. When the operating mode is Light Load Mode, it utilizes
switching operation in Pulse Width Modulation (PWM) mode control at heavier load, and it operates in Light Load
mode (LLM) control at lighter load to improve efficiency. When the operating mode is Fixed PWM Mode, the device
operates in PWM mode control regardless of the load.
Efficiency [%]
Light Load Mode Control
PWM Control
Fixed PWM Mode Control
Output Current [A]
Figure 61. Efficiency Image between Light Load Mode Control and PWM Mode Control
(2) Enable Control
The startup and shutdown can be controlled by the EN voltage (VEN). When VEN becomes 1.2 V (Typ) or more, the
internal circuit is activated and the device starts up. When VEN becomes 1.1 V (Typ) or less, the device is shutdown. In
this shutdown mode, the High-Side FET and the Low-Side FET are turned off and the SW pin is connected to GND
through an internal resistor 400 Ω (Typ) to discharge the output. The start-up with VEN must be at the same time of the
input voltage VIN (VIN = VEN) or after supplying VIN.
VIN
0V
VEN
VENH
VENL
0V
VOUT
0V
Startup
Shutdown
Figure 62. Startup and Shutdown with Enable Control Timing Chart
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1. Basic Operation – continued
(3) Soft Start
When VEN goes high, soft start function operates and output voltage gradually rises. This soft start function can
prevent overshoot of the output voltage and excessive inrush current. The soft start time tSS is 2 ms (Typ) when the SS
pin is left floating. A capacitor connected to the SS pin makes tSS more than 2 ms. See Selection of Components
Externally Connected 4. Soft Start Capacitor for how to set the soft start time.
VIN
0V
VEN
0V
VOUT
0V
VFBTH x 90 %
0.6 V
(Typ)
VFB
0V
VPGD
0V
0.4 ms (Typ)
tSS
Figure 63. Soft Start Timing Chart
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1. Basic Operation – continued
(4) Power Good
When the output voltage VOUT reaches within ±7 % (Typ) of the voltage setting, the built-in open drain Nch MOSFET
connected to the PGD pin is turned off, and the PGD pin goes Hi-Z (High impedance). When VOUT reaches outside
±10 % (Typ) of the voltage setting, the open drain Nch MOSFET is turned on and PGD pin is pulled down with 500 Ω
(Typ). It is recommended to connect a pull-up resistor of 20 kΩ to 100 kΩ.
Table 1. PGD Output
Condition
State
Before Supply Input Voltage
PGD Output
VIN < 2.5 V (Typ)
Hi-Z
Shutdown
VEN ≤ 1.1 V (Typ)
Low (Pull-down)
Enable
VEN ≥ 1.2 V (Typ)
93 % (Typ) ≤ VFB / VFBTH ≤ 107 % (Typ)
Hi-Z
VFB / VFBTH ≤ 90 % (Typ) or 110 % (Typ) ≤ VFB / VFBTH
Low (Pull-down)
UVLO
2.5 V (Typ) < VIN ≤ 4.0 V (Typ)
Low (Pull-down)
TSD
Tj ≥ 175 °C (Typ)
Low (Pull-down)
VIN
0V
VEN
0V
+10 % (Typ)
+7 % (Typ)
-7 % (Typ)
-10 % (Typ)
VOUT
0V
VFB TH x 107 % (Typ)
VFB TH x 110 % (Typ)
VFB TH x 93 % (Typ)
VFB TH x 90 % (Typ)
VFB
0V
tSS
VPGD
0V
Figure 64. Power Good Timing Chart
(Connecting a pull-up resistor to the PGD pin)
TM
(5) Nano Pulse Control
TM
Nano Pulse Control is an original technology developed by ROHM Co., Ltd. It enables to control voltage stably,
which is difficult in the conventional technology, even in a narrow SW ON time such as less than 50 ns at typical
condition.
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1. Basic Operation – continued
(6) Output Capacitor Discharge Function
When even one of the following conditions is satisfied, output is discharged with 400 Ω (Typ) resistor through the SW
pin.
• Shutdown: VEN ≤ 1.1 V (Typ)
• UVLO: VIN ≤ 4.0 V (Typ)
• TSD: Tj ≥ 175 °C (Typ)
• OVP: VFB / VFBTH ≥ 120 % (Typ)
When all of the above conditions are released, output discharge is stopped.
(7) Control Mode Selectable Function
BD9F500QUZ has the SEL1 pin and the SEL2 pin that can offer 9 different states of operation as a combination of
Switching Frequency, Maximum Output Current and Operation mode. It can operate at two different current limits to
support an output continuous current of 5 A, 3 A respectively. It can operate at three different frequencies of 600 kHz, 1
MHz and 2.2 MHz and also can choose between Light Load Mode and Fixed PWM mode for 600 kHz and 1 MHz
operation. Do not change the mode control of Switching Frequency and Maximum Output Current during operation.
SEL1 pin
condition
SEL2 pin
condition
GND
GND
GND
OPEN
VREG
GND
VREG
OPEN
OPEN
GND
OPEN
OPEN
GND
VREG
OPEN
VREG
VREG
VREG
Table 2. Control Mode Selection
Maximum
Switching
Output Current
Frequency
(IOUTMAX)
5A
1 MHz (Typ)
3A
5A
600 kHz (Typ)
3A
2.2 MHz (Typ)
3A
Operation Mode
Light Load Mode (LLM)
Fixed PWM Mode
Light Load Mode (LLM)
Fixed PWM Mode
Light Load Mode (LLM)
Fixed PWM Mode
Light Load Mode (LLM)
Fixed PWM Mode
Fixed PWM Mode
Table 3. OCP Value
Maximum Output
Current (IOUTMAX)
Low-Side OCP
High-Side OCP
Low-Side Sink OCP
(Fixed PWM mode)
5A
3A
ILOCP1 = 6.7 A (Typ)
ILOCP2 = 4.0 A (Typ)
IHOCP1 = 8.25 A (Typ)
IHOCP2 = 5.0 A (Typ)
IROCP1 = 4.2 A (Typ)
IROCP2 = 2.5 A (Typ)
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Function Explanations – continued
2. Protection
The protection circuits are intended for prevention of damage caused by unexpected accidents. Do not use the
continuous protection.
(1) Over Current Protection (OCP) / Short Circuit Protection (SCP)
Over Current Protection (OCP) restricts the flowing current through the Low-Side FET and the High-Side FET for every
switching period. If the inductor current exceeds the Low-Side OCP ILOCP1 = 6.7 A (Typ), ILOCP2 = 4.0 A (Typ) while the
Low-Side FET is on, the Low-Side FET remains on even with FB voltage VFB falls to VFBTH = 0.6 V (Typ) or less. If the
inductor current becomes less than ILOCP1, ILOCP2, the High-Side FET is able to be turned on. When the inductor current
becomes the High-Side OCP IHOCP1 = 8.25 A (Typ), IHOCP2 = 5.0 A (Typ) or more while the High-Side FET is on, the
High-Side FET is turned off. Output voltage may decrease by changing frequency and duty due to the OCP operation.
Short Circuit Protection (SCP) function is a Hiccup mode. When Low-Side OCP 128 times is counted while VFB is VFBTH
x 90 % or less (VPGD = Low), the device stops the switching operation for 16 times of Soft Start Time (Typ). After that,
the device restarts. SCP does not operate during the soft start even if the device is in the SCP conditions. Do not
exceed the maximum junction temperature (Tjmax = 150 °C) during OCP and SCP operation.
Table 4. The Operating Condition of OCP and SCP
VFB
Start-up
OCP
VEN
≤ VFBTH x 90 % (Typ)
≥ 1.2 V (Typ)
> VFBTH x 93 % (Typ)
≤ VFBTH x 90 % (Typ)
≤ 1.1 V (Typ)
During Soft Start
Complete Soft Start
-
Shutdown
SCP
Enable
Disable
Enable
Disable
Enable
Enable
Disable
Disable
VOUT
VFB TH x 93 % (Typ)
VFB
VFB TH x 90 % (Typ)
VPGD
VSW
High-Side FET
Inte rnal Gate Signal
Low-Side FET
Inte rnal Gate Signal
IHOCP
ILOCP
Inductor Current
High-Side OCP
Internal Signal
Low-Side OCP
Internal Signal
SCP
Internal Signal
OCP 128 counts
Less than
OCP 128 counts
16 tims of SS time (Typ)
Figure 65. OCP and SCP Timing Chart
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BD9F500QUZ
2. Protection – continued
(2) Low-Side Sink (Reverse) Over Current Protection (ROCP)
When operating mode is Fixed PWM and inductor current exceeds the sink current limit threshold value I ROCP1 = 4.2 A
(Typ), IROCP2 = 2.5 A (Typ) while Low-Side FET is ON, the Low-Side FET turns OFF.
(3) Under Voltage Lockout Protection (UVLO)
When input voltage VIN falls to 4.0 V (Typ) or less, the device is shutdown. When VIN becomes 4.2 V (Typ) or more, the
device starts up. The hysteresis is 200 mV (Typ).
VIN
(=VEN)
VOUT
Hysteresis
VUVLOHYS = 200 mV (Typ)
UVLO Release
VUVLO2 = 4.2 V (Typ)
UVLO Detection
VUVLO1 = 4.0 V (Typ)
0V
VOUT
0V
tSS
Figure 66. UVLO Timing Chart
(4) Thermal Shutdown Protection (TSD)
Thermal shutdown circuit prevents heat damage to the IC. The device should always operate within the IC’s maximum
junction temperature rating (Tjmax = 150 °C). However, if it continues exceeding the rating and the junction
temperature Tj rises to 175 °C (Typ), the TSD circuit is activated and it turns the output MOSFETs off. When the Tj falls
below the TSD threshold, the circuits are automatically restored to normal operation. The TSD threshold has a
hysteresis of 25 °C (Typ). Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings.
Therefore, under no circumstances, should the TSD circuit be used in a set design or for any purpose other than
protecting the IC from heat damage.
(5) Over Voltage Protection (OVP)
When the FB voltage VFB exceeds VFBTH x 120 % (Typ) or more, output is discharged with 400 Ω (Typ) resister through
the SW pin to prevent the increase in the output voltage. After the VFB falls VFBTH x 115 % (Typ) or less, the output
MOSFETs are returned to normal operation condition. Switching operation restarts after VFB falls below VFBTH (Typ).
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BD9F500QUZ
Application Examples
1. VIN = 12 V to 24 V, VOUT = 3.3 V, fSW = 1 MHz
Table 5. Specification of Application
Symbol
Parameter
Input Voltage
Output Voltage
Maximum Output Current
Switching Frequency
Operation Mode
Temperature
EN
VIN
EN
VIN
CIN2
12 V to 24 V (Typ)
VOUT
3.3 V (Typ)
IOUTMAX
5A
fSW
1 MHz (Typ)
-
Light Load Mode
Ta
25 °C
BD9F500QUZ
BOOT
CIN1
PGND
RS1U
RS2D
RS1D
CBOOT
VOUT
SW
L
VREG
RS2U
Specification Value
VIN
R0
SEL1
RPGD
COUT1
COUT2
CFB
CREG
PGD
R1A
R1B
SEL2
PGD
SS
CSS
FB
R2
AGND
Figure 67. Application Circuit
Part No.
Value
L
1.5 μH
Table 6. Recommended Component Values
Part Name
Size Code (mm)
Manufacturer
1217AS-H-1R5N
8080
Murata
0.1 μF (50 V, X5R, ±10 %)
UMK105BJ104KV-F
1005
TAIYO YUDEN
10 μF (50 V, X5R, ±20 %)
UMK325BJ106MM-P
3225
TAIYO YUDEN
(Note 3)
0.1 μF (50 V, X5R, ±10 %)
UMK105BJ104KV-F
1005
TAIYO YUDEN
COUT1
(Note 4)
22 μF (25 V, X5R, ±20 %)
TMK212BBJ226MG-TT
2012
TAIYO YUDEN
COUT2
(Note 4)
22 μF (25 V, X5R, ±20 %)
TMK212BBJ226MG-TT
2012
TAIYO YUDEN
(Note 5)
2.2 μF (25 V, X5R, ±20 %)
TMK105CBJ225MV-F
1005
TAIYO YUDEN
CIN1
(Note 1)
CIN2
(Note 2)
CBOOT
CREG
CFB
82 pF (50 V, C0G, ±5 %)
GRM0335C1H820JA01
0603
Murata
CSS
-
-
-
-
R1A
1.5 kΩ (1 %, 1/16 W)
MCR01MZPF1500
1005
ROHM
R1B
120 kΩ (1 %, 1/16 W)
MCR01MZPF1203
1005
ROHM
R2
27 kΩ (1 %, 1/16 W)
MCR01MZPF2702
1005
ROHM
RPGD
100 kΩ (1 %, 1/16 W)
MCR01MZPF1003
1005
ROHM
RS1U
-
-
-
-
RS1D
Short
-
-
-
RS2U
-
-
-
-
RS2D
Short
-
-
-
Short
-
-
-
R0
(Note 6)
(Note 1) In order to reduce the influence of high frequency noise, connect a 0.1 μF ceramic capacitor CIN1 as close as possible to the VIN pin and the PGND pin.
(Note 2) For the input capacitor CIN2, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance of no less
than 3 μF.
(Note 3) For the bootstrap capacitor CBOOT, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance of no
less than 0.022 μF.
(Note 4) In case of changing the actual capacitance value due to temperature characteristics, DC bias characteristics, etc. of the output capacitor COUT1 and COUT2,
the loop response characteristics may change. Confirm with the actual application.
(Note 5) For the VREG capacitor CREG, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance of no less
than 0.82 μF.
(Note 6) R0 is an option, used for feedback’s frequency response measurement. By inserting a resistor at R 0, it is possible to measure the frequency response
(phase margin) using a FRA. However, the resistor is not used in actual application, use this resistor pattern in short-circuit mode.
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BD9F500QUZ
1. VIN = 12 V to 24 V, VOUT = 3.3 V, fSW = 1 MHz – continued
100
Time: 1 µs/div
90
VOUT: 30 mV/div
Efficiency [%]
80
70
VSW: 5 V/div
60
50
VIN = 12 V
VIN = 24 V
40
0.001
0.01
0.1
1
Output Current : IOUT [A]
10
Figure 68. Efficiency vs Output Current
80
Figure 69. Output Ripple Voltage (VIN = 12 V, IOUT = 5 A)
180
Time: 200 µs/div
Gain
Phase
135
40
90
20
45
0
0
-20
-45
-40
-90
-60
-135
-80
1
10
100
Frequency [kHz]
VOUT: 50 mV/div
Phase [°]
Gain [dB]
60
IOUT: 1 A/div
-180
1000
Figure 70. Frequency Characteristics (VIN = 12 V, IOUT = 3 A)
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Figure 71. Load Transient Response
(VIN = 12 V, IOUT = 0.1 A to 3.0 A)
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BD9F500QUZ
Application Examples – continued
2. VIN = 12 V to 24 V, VOUT = 3.3 V, fSW = 600 kHz
Table 7. Specification of Application
Symbol
Parameter
Input Voltage
Output Voltage
Maximum Output Current
Switching Frequency
Operation Mode
Temperature
EN
VIN
EN
VIN
CIN2
12 V to 24 V (Typ)
VOUT
3.3 V (Typ)
IOUTMAX
5A
fSW
600 kHz (Typ)
-
Light Load Mode
Ta
25 °C
BD9F500QUZ
BOOT
CIN1
PGND
RS1U
RS2D
RS1D
CBOOT
VOUT
SW
L
VREG
RS2U
Specification Value
VIN
R0
SEL1
RPGD
COUT1
COUT2
CFB
CREG
PGD
R1A
R1B
SEL2
PGD
SS
CSS
FB
R2
AGND
Figure 72. Application Circuit
Part No.
Value
L
3.3 μH
Table 8. Recommended Component Values
Part Name
Size Code (mm)
Manufacturer
1217AS-H-3R3N
8080
Murata
0.1 μF (50 V, X5R, ±10 %)
UMK105BJ104KV-F
1005
TAIYO YUDEN
10 μF (50 V, X5R, ±20 %)
UMK325BJ106MM-P
3225
TAIYO YUDEN
(Note 3)
0.1 μF (50 V, X5R, ±10 %)
UMK105BJ104KV-F
1005
TAIYO YUDEN
COUT1
(Note 4)
22 μF (25 V, X5R, ±20 %)
TMK212BBJ226MG-TT
2012
TAIYO YUDEN
COUT2
(Note 4)
22 μF (25 V, X5R, ±20 %)
TMK212BBJ226MG-TT
2012
TAIYO YUDEN
(Note 5)
2.2 μF (25 V, X5R, ±20 %)
TMK105CBJ225MV-F
1005
TAIYO YUDEN
CIN1
(Note 1)
CIN2
(Note 2)
CBOOT
CREG
CFB
82 pF (50 V, C0G, ±5 %)
GRM0335C1H820JA01
0603
Murata
CSS
-
-
-
-
R1A
1.5 kΩ (1 %, 1/16 W)
MCR01MZPF1500
1005
ROHM
R1B
120 kΩ (1 %, 1/16 W)
MCR01MZPF1203
1005
ROHM
R2
27 kΩ (1 %, 1/16 W)
MCR01MZPF2702
1005
ROHM
RPGD
100 kΩ (1 %, 1/16 W)
MCR01MZPF1003
1005
ROHM
RS1U
-
-
-
-
RS1D
-
-
-
-
RS2U
-
-
-
-
RS2D
Short
-
-
-
Short
-
-
-
R0
(Note 6)
(Note 1) In order to reduce the influence of high frequency noise, connect a 0.1 μF ceramic capacitor CIN1 as close as possible to the VIN pin and the PGND pin.
(Note 2) For the input capacitor CIN2, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance of no less
than 3 μF.
(Note 3) For the bootstrap capacitor CBOOT, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance of no
less than 0.022 μF.
(Note 4) In case of changing the actual capacitance value due to temperature characteristics, DC bias characteristics, etc. of the output capacitor COUT1 and COUT2,
the loop response characteristics may change. Confirm with the actual application.
(Note 5) For the VREG capacitor CREG, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance of no less
than 0.82 μF.
(Note 6) R0 is an option, used for feedback’s frequency response measurement. By inserting a resistor at R 0, it is possible to measure the frequency response
(phase margin) using a FRA. However, the resistor is not used in actual application, use this resistor pattern in short-circuit mode.
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BD9F500QUZ
2. VIN = 12 V to 24 V, VOUT = 3.3 V, fSW = 600 kHz – continued
100
Time: 1 µs/div
90
VOUT: 30 mV/div
Efficiency [%]
80
70
VSW: 5 V/div
60
50
VIN = 12 V
VIN = 24 V
40
0.001
0.01
0.1
1
Output Current : IOUT [A]
10
Figure 73. Efficiency vs Output Current
80
Figure 74. Output Ripple Voltage (VIN = 12 V, IOUT = 5 A)
180
Time: 200 µs/div
Gain
Phase
135
40
90
20
45
0
0
-20
-45
-40
-90
-60
-135
-80
1
10
100
Frequency [kHz]
VOUT: 50 mV/div
Phase [°]
Gain [dB]
60
IOUT: 1 A/div
-180
1000
Figure 75. Frequency Characteristics (VIN = 12 V, IOUT = 3 A)
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Figure 76. Load Transient Response
(VIN = 12 V, IOUT = 0.1 A to 3.0 A)
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BD9F500QUZ
Application Examples – continued
3. VIN = 5 V, VOUT = 3.3 V, fSW = 1 MHz
Table 9. Specification of Application
Symbol
Parameter
Input Voltage
Output Voltage
Maximum Output Current
Switching Frequency
Operation Mode
Temperature
EN
VIN
EN
VIN
CIN2
5 V (Typ)
VOUT
3.3 V (Typ)
IOUTMAX
5A
fSW
1 MHz (Typ)
-
Light Load Mode
Ta
25 °C
BD9F500QUZ
BOOT
CIN1
PGND
RS1U
RS2D
RS1D
CBOOT
VOUT
SW
L
VREG
RS2U
Specification Value
VIN
R0
SEL1
RPGD
CREG
PGD
CSS
R1A
COUT1
COUT2
CFB
R1B
SEL2
PGD
SS
FB
R2
AGND
Figure 77. Application Circuit
Part No.
Value
L
1.0 μH
Table 10. Recommended Component Values
Part Name
Size Code (mm)
Manufacturer
FDSD0518-H-1R0M
5249
Murata
0.1 μF (50 V, X5R, ±10 %)
UMK105BJ104KV-F
1005
TAIYO YUDEN
10 μF (50 V, X5R, ±20 %)
UMK325BJ106MM-P
3225
TAIYO YUDEN
(Note 3)
0.1 μF (50 V, X5R, ±10 %)
UMK105BJ104KV-F
1005
TAIYO YUDEN
COUT1
(Note 4)
22 μF (25 V, X5R, ±20 %)
TMK212BBJ226MG-TT
2012
TAIYO YUDEN
COUT2
(Note 4)
22 μF (25 V, X5R, ±20 %)
TMK212BBJ226MG-TT
2012
TAIYO YUDEN
(Note 5)
2.2 μF (25 V, X5R, ±20 %)
TMK105CBJ225MV-F
1005
TAIYO YUDEN
CIN1
(Note 1)
CIN2
(Note 2)
CBOOT
CREG
CFB
33 pF (50 V, C0G, ±5 %)
GRM0335C1H330JA01
0603
Murata
CSS
-
-
-
-
R1A
120 kΩ (1 %, 1/16 W)
MCR01MZPF1203
1005
ROHM
R1B
330 kΩ (1 %, 1/16 W)
MCR01MZPF3303
1005
ROHM
R2
100 kΩ (1 %, 1/16 W)
MCR01MZPF1003
1005
ROHM
RPGD
100 kΩ (1 %, 1/16 W)
MCR01MZPF1003
1005
ROHM
RS1U
-
-
-
-
RS1D
Short
-
-
-
RS2U
-
-
-
-
RS2D
Short
-
-
-
Short
-
-
-
R0
(Note 6)
(Note 1) In order to reduce the influence of high frequency noise, connect a 0.1 μF ceramic capacitor CIN1 as close as possible to the VIN pin and the PGND pin.
(Note 2) For the input capacitor CIN2, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance of no less
than 3 μF.
(Note 3) For the bootstrap capacitor CBOOT, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance of no
less than 0.022 μF.
(Note 4) In case of changing the actual capacitance value due to temperature characteristics, DC bias characteristics, etc. of the output capacitor COUT1 and COUT2,
the loop response characteristics may change. Confirm with the actual application.
(Note 5) For the VREG capacitor CREG, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance of no less
than 0.82 μF.
(Note 6) R0 is an option, used for feedback’s frequency response measurement. By inserting a resistor at R 0, it is possible to measure the frequency response
(phase margin) using a FRA. However, the resistor is not used in actual application, use this resistor pattern in short-circuit mode.
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BD9F500QUZ
3. VIN = 5 V, VOUT = 3.3 V, fSW = 1 MHz – continued
100
Time: 1 µs/div
90
Efficiency [%]
80
VOUT: 30 mV/div
70
VSW: 2 V/div
60
50
40
0.001
0.01
0.1
1
Output Current : IOUT [A]
10
Figure 78. Efficiency vs Output Current
80
Figure 79. Output Ripple Voltage (IOUT = 5 A)
180
Time: 200 µs/div
Gain
Phase
135
40
90
20
45
0
0
-20
-45
-40
-90
-60
-135
-80
1
10
100
Frequency [kHz]
VOUT: 50 mV/div
Phase [°]
Gain [dB]
60
IOUT: 1 A/div
-180
1000
Figure 80. Frequency Characteristics (IOUT = 3 A)
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Figure 81. Load Transient Response (IOUT = 0.1 A to 3.0 A)
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BD9F500QUZ
Application Examples – continued
4. VIN = 5 V, VOUT = 3.3 V, fSW = 600 kHz
Table 11. Specification of Application
Symbol
Parameter
Input Voltage
Output Voltage
Maximum Output Current
Switching Frequency
Operation Mode
Temperature
EN
VIN
EN
VIN
CIN2
5 V (Typ)
VOUT
3.3 V (Typ)
IOUTMAX
5A
fSW
600 kHz (Typ)
-
Light Load Mode
Ta
25 °C
BD9F500QUZ
BOOT
CIN1
PGND
RS1U
RS2D
RS1D
CBOOT
VOUT
SW
L
VREG
RS2U
Specification Value
VIN
R0
SEL1
RPGD
CREG
PGD
CSS
R1A
COUT1
COUT2
CFB
R1B
SEL2
PGD
SS
FB
R2
AGND
Figure 82. Application Circuit
Part No.
Value
L
2.2 μH
Table 12. Recommended Component Values
Part Name
Size Code (mm)
Manufacturer
FDSD0630-H-2R2M
7066
Murata
0.1 μF (50 V, X5R, ±10 %)
UMK105BJ104KV-F
1005
TAIYO YUDEN
10 μF (50 V, X5R, ±20 %)
UMK325BJ106MM-P
3225
TAIYO YUDEN
(Note 3)
0.1 μF (50 V, X5R, ±10 %)
UMK105BJ104KV-F
1005
TAIYO YUDEN
COUT1
(Note 4)
22 μF (25 V, X5R, ±20 %)
TMK212BBJ226MG-TT
2012
TAIYO YUDEN
COUT2
(Note 4)
22 μF (25 V, X5R, ±20 %)
TMK212BBJ226MG-TT
2012
TAIYO YUDEN
(Note 5)
2.2 μF (25 V, X5R, ±20 %)
TMK105CBJ225MV-F
1005
TAIYO YUDEN
CIN1
(Note 1)
CIN2
(Note 2)
CBOOT
CREG
CFB
39 pF (50 V, C0G, ±5 %)
GRM0335C1H390JA01
0603
Murata
CSS
-
-
-
-
R1A
120 kΩ (1 %, 1/16 W)
MCR01MZPF1203
1005
ROHM
R1B
330 kΩ (1 %, 1/16 W)
MCR01MZPF3303
1005
ROHM
R2
100 kΩ (1 %, 1/16 W)
MCR01MZPF1003
1005
ROHM
RPGD
100 kΩ (1 %, 1/16 W)
MCR01MZPF1003
1005
ROHM
RS1U
-
-
-
-
RS1D
-
-
-
-
RS2U
-
-
-
-
RS2D
Short
-
-
-
Short
-
-
-
R0
(Note 6)
(Note 1) In order to reduce the influence of high frequency noise, connect a 0.1 μF ceramic capacitor CIN1 as close as possible to the VIN pin and the PGND pin.
(Note 2) For the input capacitor CIN2, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance of no less
than 3 μF.
(Note 3) For the bootstrap capacitor CBOOT, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance of no
less than 0.022 μF.
(Note 4) In case of changing the actual capacitance value due to temperature characteristics, DC bias characteristics, etc. of the output capacitor COUT1 and COUT2,
the loop response characteristics may change. Confirm with the actual application.
(Note 5) For the VREG capacitor CREG, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance of no less
than 0.82 μF.
(Note 6) R0 is an option, used for feedback’s frequency response measurement. By inserting a resistor at R 0, it is possible to measure the frequency response
(phase margin) using a FRA. However, the resistor is not used in actual application, use this resistor pattern in short-circuit mode.
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4. VIN = 5 V, VOUT = 3.3 V, fSW = 600 kHz – continued
100
Time: 1 µs/div
90
VOUT: 30 mV/div
Efficiency [%]
80
70
VSW: 2 V/div
60
50
40
0.001
0.01
0.1
1
Output Current : IOUT [A]
10
Figure 83. Efficiency vs Output Current
80
Figure 84. Output Ripple Voltage (IOUT = 5 A)
180
Time: 200 µs/div
Gain
Phase
135
40
90
20
45
0
0
-20
-45
-40
-90
-60
-135
-80
1
10
100
Frequency [kHz]
VOUT: 50 mV/div
Phase [°]
Gain [dB]
60
IOUT: 1 A/div
-180
1000
Figure 85. Frequency Characteristics (IOUT = 3 A)
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Figure 86. Load Transient Response (IOUT = 0.1 A to 3.0 A)
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Application Examples – continued
5. VIN = 12 V, VOUT = 1 V, fSW = 1 MHz
Table 13. Specification of Application
Symbol
Parameter
Input Voltage
Output Voltage
Maximum Output Current
Switching Frequency
Operation Mode
Temperature
EN
VIN
EN
VIN
CIN2
12 V (Typ)
VOUT
1 V (Typ)
IOUTMAX
5A
fSW
1 MHz (Typ)
-
Fixed PWM Mode
Ta
25 °C
BD9F500QUZ
BOOT
CIN1
PGND
RS1U
RS2D
RS1D
CBOOT
VOUT
SW
L
VREG
RS2U
Specification Value
VIN
R0
SEL1
RPGD
CREG
PGD
CSS
R1A
COUT1
COUT2
CFB
R1B
SEL2
PGD
SS
FB
R2
AGND
Figure 87. Application Circuit
Table 14. Recommended Component Values
Part Name
Size Code (mm)
Part No.
Value
L
0.68 μH
Manufacturer
FDSD0518-H-R68M
5249
Murata
0.1 μF (50 V, X5R, ±10 %)
UMK105BJ104KV-F
1005
TAIYO YUDEN
10 μF (50 V, X5R, ±20 %)
UMK325BJ106MM-P
3225
TAIYO YUDEN
(Note 3)
0.1 μF (50 V, X5R, ±10 %)
UMK105BJ104KV-F
1005
TAIYO YUDEN
COUT1
(Note 4)
22 μF (25 V, X5R, ±20 %)
TMK212BBJ226MG-TT
2012
TAIYO YUDEN
COUT2
(Note 4)
22 μF (25 V, X5R, ±20 %)
TMK212BBJ226MG-TT
2012
TAIYO YUDEN
(Note 5)
2.2 μF (25 V, X5R, ±20 %)
TMK105CBJ225MV-F
1005
TAIYO YUDEN
CIN1
(Note 1)
CIN2
(Note 2)
CBOOT
CREG
CFB
27 pF (50 V, C0G, ±5 %)
GRM0335C1H270JA01
0603
Murata
CSS
-
-
-
-
R1A
Short
-
-
-
R1B
180 kΩ (1 %, 1/16 W)
MCR01MZPF1803
1005
ROHM
R2
270 kΩ (1 %, 1/16 W)
MCR01MZPF2703
1005
ROHM
RPGD
100 kΩ (1 %, 1/16 W)
MCR01MZPF1003
1005
ROHM
RS1U
-
-
-
-
RS1D
Short
-
-
-
RS2U
-
-
-
-
-
-
-
-
Short
-
-
-
RS2D
R0
(Note 6)
(Note 1) In order to reduce the influence of high frequency noise, connect a 0.1 μF ceramic capacitor CIN1 as close as possible to the VIN pin and the PGND pin.
(Note 2) For the input capacitor CIN2, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance of no less
than 3 μF.
(Note 3) For the bootstrap capacitor CBOOT, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance of no
less than 0.022 μF.
(Note 4) In case of changing the actual capacitance value due to temperature characteristics, DC bias characteristics, etc. of the output capacitor COUT1 and COUT2,
the loop response characteristics may change. Confirm with the actual application.
(Note 5) For the VREG capacitor CREG, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance of no less
than 0.82 μF.
(Note 6) R0 is an option, used for feedback’s frequency response measurement. By inserting a resistor at R 0, it is possible to measure the frequency response
(phase margin) using a FRA. However, the resistor is not used in actual application, use this resistor pattern in short-circuit mode.
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5. VIN = 12 V, VOUT = 1 V, fSW = 1 MHz – continued
100
Time: 1 µs/div
90
Efficiency [%]
80
VOUT: 30 mV/div
70
VSW: 5 V/div
60
50
40
0
1
2
3
Output Current : IOUT [A]
4
5
Figure 88. Efficiency vs Output Current
80
Figure 89. Output Ripple Voltage (IOUT = 5 A)
180
Time: 200 µs/div
Gain
Phase
135
40
90
20
45
0
0
-20
-45
-40
-90
-60
-135
-80
1
10
100
Frequency [kHz]
VOUT: 50 mV/div
Phase [°]
Gain [dB]
60
IOUT: 1 A/div
-180
1000
Figure 90. Frequency Characteristics (IOUT = 3 A)
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Figure 91. Load Transient Response (IOUT = 0 A to 3 A)
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Application Examples – continued
6. VIN = 12 V, VOUT = 1 V, fSW = 600 kHz
Table 15. Specification of Application
Symbol
Parameter
Input Voltage
Output Voltage
Maximum Output Current
Switching Frequency
Operation Mode
Temperature
EN
VIN
EN
VIN
CIN2
12 V (Typ)
VOUT
1 V (Typ)
IOUTMAX
5A
fSW
600 kHz (Typ)
-
Fixed PWM Mode
Ta
25 °C
BD9F500QUZ
BOOT
CIN1
PGND
RS1U
RS2D
RS1D
CBOOT
VOUT
SW
L
VREG
RS2U
Specification Value
VIN
R0
SEL1
RPGD
CREG
PGD
CSS
R1A
COUT1
COUT2
CFB
R1B
SEL2
PGD
SS
FB
R2
AGND
Figure 92. Application Circuit
Part No.
Value
L
1.5 μH
Table 16. Recommended Component Values
Part Name
Size Code (mm)
Manufacturer
FDSD0630-H-1R5N
7066
Murata
0.1 μF (50 V, X5R, ±10 %)
UMK105BJ104KV-F
1005
TAIYO YUDEN
10 μF (50 V, X5R, ±20 %)
UMK325BJ106MM-P
3225
TAIYO YUDEN
(Note 3)
0.1 μF (50 V, X5R, ±10 %)
UMK105BJ104KV-F
1005
TAIYO YUDEN
COUT1
(Note 4)
22 μF (25 V, X5R, ±20 %)
TMK212BBJ226MG-TT
2012
TAIYO YUDEN
COUT2
(Note 4)
22 μF (25 V, X5R, ±20 %)
TMK212BBJ226MG-TT
2012
TAIYO YUDEN
(Note 5)
2.2 μF (25 V, X5R, ±20 %)
TMK105CBJ225MV-F
1005
TAIYO YUDEN
CIN1
(Note 1)
CIN2
(Note 2)
CBOOT
CREG
CFB
33 pF (50 V, C0G, ±5 %)
GRM0335C1H330JA01
0603
Murata
CSS
-
-
-
-
R1A
Short
-
1005
ROHM
R1B
180 kΩ (1 %, 1/16 W)
MCR01MZPF1803
1005
ROHM
R2
270 kΩ (1 %, 1/16 W)
MCR01MZPF2703
1005
ROHM
RPGD
100 kΩ (1 %, 1/16 W)
MCR01MZPF1003
1005
ROHM
RS1U
-
-
-
-
RS1D
-
-
-
-
RS2U
-
-
-
-
-
-
-
-
Short
-
-
-
RS2D
R0
(Note 6)
(Note 1) In order to reduce the influence of high frequency noise, connect a 0.1 μF ceramic capacitor CIN1 as close as possible to the VIN pin and the PGND pin.
(Note 2) For the input capacitor CIN2, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance of no less
than 3 μF.
(Note 3) For the bootstrap capacitor CBOOT, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance of no
less than 0.022 μF.
(Note 4) In case of changing the actual capacitance value due to temperature characteristics, DC bias characteristics, etc. of the output capacitor COUT1 and COUT2,
the loop response characteristics may change. Confirm with the actual application.
(Note 5) For the VREG capacitor CREG, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance of no less
than 0.82 μF.
(Note 6) R0 is an option, used for feedback’s frequency response measurement. By inserting a resistor at R0, it is possible to measure the frequency response
(phase margin) using a FRA. However, the resistor is not used in actual application, use this resistor pattern in short-circuit mode.
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6. VIN = 12 V, VOUT = 1 V, fSW = 600 kHz – continued
100
Time: 1 µs/div
90
Efficiency [%]
80
VOUT: 30 mV/div
70
VSW: 5 V/div
60
50
40
0
1
2
3
4
Output Current : IOUT [A]
5
Figure 93. Efficiency vs Output Current
80
Figure 94. Output Ripple Voltage (IOUT = 5 A)
180
Time: 200 µs/div
Gain
Phase
135
40
90
20
45
0
0
-20
-45
-40
-90
-60
-135
-80
1
10
100
Frequency [kHz]
VOUT: 50 mV/div
Phase [°]
Gain [dB]
60
IOUT: 1 A/div
-180
1000
Figure 95. Frequency Characteristics (IOUT = 3 A)
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Figure 96. Load Transient Response (IOUT = 0 A to 3 A)
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Application Examples – continued
7. VIN = 12 V, VOUT = 3.3 V, fSW = 2.2 MHz
Table 17. Specification of Application
Symbol
Parameter
Input Voltage
Output Voltage
Maximum Output Current
Switching Frequency
Operation Mode
Temperature
EN
VIN
EN
VIN
CIN2
12 V (Typ)
VOUT
3.3 V (Typ)
IOUTMAX
3A
fSW
2.2 MHz (Typ)
-
Fixed PWM Mode
Ta
25 °C
BD9F500QUZ
BOOT
CIN1
PGND
RS1U
RS2D
RS1D
CBOOT
VOUT
SW
L
VREG
RS2U
Specification Value
VIN
R0
SEL1
RPGD
CREG
PGD
CSS
R1A
COUT1
COUT2
CFB
R1B
SEL2
PGD
SS
FB
R2
AGND
Figure 97. Application Circuit
Part No.
Value
L
1.0 μH
Table 18. Recommended Component Values
Part Name
Size Code (mm)
Manufacturer
FDSD0518-H-1R0M
5249
Murata
0.1 μF (50 V, X5R, ±10 %)
UMK105BJ104KV-F
1005
TAIYO YUDEN
10 μF (50 V, X5R, ±20 %)
UMK325BJ106MM-P
3225
TAIYO YUDEN
(Note 3)
0.1 μF (50 V, X5R, ±10 %)
UMK105BJ104KV-F
1005
TAIYO YUDEN
COUT1
(Note 4)
22 μF (25 V, X5R, ±20 %)
TMK212BBJ226MG-TT
2012
TAIYO YUDEN
COUT2
(Note 4)
22 μF (25 V, X5R, ±20 %)
TMK212BBJ226MG-TT
2012
TAIYO YUDEN
(Note 5)
2.2 μF (25 V, X5R, ±20 %)
TMK105CBJ225MV-F
1005
TAIYO YUDEN
CIN1
(Note 1)
CIN2
(Note 2)
CBOOT
CREG
CFB
33 pF (50 V, C0G, ±5 %)
GRM0335C1H330JA01
0603
Murata
CSS
-
-
-
-
R1A
1.5 kΩ (1 %, 1/16 W)
MCR01MZPF1500
1005
ROHM
R1B
120 kΩ (1 %, 1/16 W)
MCR01MZPF1203
1005
ROHM
R2
27 kΩ (1 %, 1/16 W)
MCR01MZPF2702
1005
ROHM
RPGD
100 kΩ (1 %, 1/16 W)
MCR01MZPF1003
1005
ROHM
RS1U
Short
-
-
-
RS1D
-
-
-
-
RS2U
Short
-
-
-
-
-
-
-
Short
-
-
-
RS2D
R0
(Note 6)
(Note 1) In order to reduce the influence of high frequency noise, connect a 0.1 μF ceramic capacitor CIN1 as close as possible to the VIN pin and the PGND pin.
(Note 2) For the input capacitor CIN2, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance of no less
than 3 μF.
(Note 3) For the bootstrap capacitor CBOOT, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance of no
less than 0.022 μF.
(Note 4) In case of changing the actual capacitance value due to temperature characteristics, DC bias characteristics, etc. of the output capacitor COUT1 and COUT2,
the loop response characteristics may change. Confirm with the actual application.
(Note 5) For the VREG capacitor CREG, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance of no less
than 0.82 μF.
(Note 6) R0 is an option, used for feedback’s frequency response measurement. By inserting a resistor at R 0, it is possible to measure the frequency response
(phase margin) using a FRA. However, the resistor is not used in actual application, use this resistor pattern in short-circuit mode.
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7. VIN = 12 V, VOUT = 3.3 V, fSW = 2.2 MHz – continued
100
Time: 1 µs/div
90
Efficiency [%]
80
VOUT: 30 mV/div
70
VSW: 5 V/div
60
50
40
0
1
2
Output Current : IOUT [A]
3
Figure 98. Efficiency vs Output Current
80
Figure 99. Output Ripple Voltage (IOUT = 3 A)
180
Time: 200 µs/div
Gain
Phase
135
40
90
20
45
0
0
-20
-45
-40
-90
-60
-135
-80
1
10
100
Frequency [kHz]
VOUT: 50 mV/div
Phase [°]
Gain [dB]
60
IOUT: 1 A/div
-180
1000
Figure 100. Frequency Characteristics (IOUT = 2 A)
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Figure 101. Load Transient Response (IOUT = 0 A to 2 A)
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Selection of Components Externally Connected
Contact us if not use the recommended component values in Application Examples.
1. Input Capacitor
Use ceramic type capacitor for the input capacitor. The input capacitor is used to reduce the input ripple noise and it is
effective by being placed as close as possible to the VIN pin. Set the capacitor value so that it does not fall to 3 μF
considering the capacitor value variances, temperature characteristics, DC bias characteristics, aging characteristics, and
etc. The PCB layout and the position of the capacitor may lead to IC malfunction. Refer to the notes on the PCB layout on
PCB Layout Design when designing PCB layout. In addition, the capacitor with value 0.1 μF can be connected as close as
possible to the VIN pin and the PGND pin in order to reduce the high frequency noise.
2. Output LC Filter
In order to supply a continuous current to the load, the DC/DC converter requires an LC filter for smoothing the output
voltage. For recommended inductance, use the values listed in Table 19.
VIN
IL
Inductor saturation current > IOUTMAX + ∆IL/2
L
∆IL
Driver
Maximum Output Current IOUTMAX
VOUT
COUT
t
Figure 102. Waveform of Inductor Current
Figure 103. Output LC Filter Circuit
For example, given that VIN = 12 V, VOUT = 3.3 V, L = 1.5 μH, and the switching frequency fSW = 1.0 MHz, Inductor current
ΔIL can be represented by the following equation.
∆𝐼𝐿 = 𝑉𝑂𝑈𝑇 × (𝑉𝐼𝑁 − 𝑉𝑂𝑈𝑇 ) × 𝑉
1
𝐼𝑁 ×𝑓𝑆𝑊 ×𝐿
= 1.595 [A]
The rated current of the inductor (Inductor saturation current) must be larger than the sum of the maximum output current
IOUTMAX and 1/2 of the inductor ripple current ΔIL.
Use ceramic type capacitor for the output capacitor COUT. For recommended actual capacitance, use the values listed in
Table 19. COUT affects the output ripple voltage. Select COUT so that it must satisfy the required ripple voltage
characteristics.
The output ripple voltage can be estimated by the following equation.
∆𝑉𝑅𝑃𝐿 = ∆𝐼𝐿 × (𝑅𝐸𝑆𝑅 + 8×𝐶
1
𝑂𝑈𝑇 ×𝑓𝑆𝑊
) [V]
where:
𝑅𝐸𝑆𝑅 is the Equivalent Series Resistance (ESR) of the output capacitor.
For example, given that COUT = 44 μF and RESR = 3 mΩ, ΔVRPL can be calculated as below.
1
∆𝑉𝑅𝑃𝐿 = 1.595 𝐴 × (3 𝑚𝛺 + 8×44 𝜇𝐹×1 𝑀𝐻𝑧) = 9.3 [mV]
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2. Output LC Filter – continued
In addition, the total capacitance connected to VOUT needs to satisfy the value obtained by the following equation.
𝐶𝑂𝑈𝑇𝑀𝐴𝑋 <
𝑡𝑆𝑆𝑀𝐼𝑁
𝑉𝑂𝑈𝑇
× (𝐼𝑂𝑈𝑇𝑀𝐴𝑋 +
∆𝐼𝐿
2
− 𝐼𝑂𝑈𝑇𝑆𝑆 ) [F]
where:
𝑡𝑆𝑆𝑀𝐼𝑁 is the minimum soft start time.
𝑉𝑂𝑈𝑇 is the output voltage.
𝐼𝑂𝑈𝑇𝑀𝐴𝑋 is the maximum output current.
∆IL is the inductor current.
IOUTSS is the maximum output current during soft start.
For example, given that VIN = 12 V, VOUT = 3.3 V, L = 1.5 µH, fSW = 1 MHz (Typ), tSSMIN = 1.4 ms (CSS = OPEN), IOUTMAX = 5
A, and IOUTSS = 5 A, COUTMAX can be calculated as below.
𝐶𝑂𝑈𝑇𝑀𝐴𝑋 <
1.4 𝑚𝑠
3.3 𝑉
× (5 𝐴 +
1.595 𝐴
2
− 5 𝐴) = 338 [µF]
If the total capacitance connected to VOUT is larger than COUTMAX, over current protection may be activated by the inrush
current at startup and prevented to turn on the output. Confirm this on the actual application.
Table 19. Recommended inductance and output capacitance
Frequency
[MHz]
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2.2
2.2
VIN [V]
VOUT [V]
IOUTMAX [A]
Inductor L[μH]
12
12
24
24
5
5
12
12
5
5
12
12
24
24
24
24
12
12
24
24
5
5
12
12
5
5
12
12
24
24
24
24
12
24
3.3
3.3
3.3
3.3
3.3
3.3
1
1
1
1
5
5
5
5
12
12
3.3
3.3
3.3
3.3
3.3
3.3
1
1
1
1
5
5
5
5
12
12
3.3
3.3
5
3
5
3
5
3
5
3
5
3
5
3
5
3
5
3
5
3
5
3
5
3
5
3
5
3
5
3
5
3
5
3
3
3
3.3
4.7
3.3
4.7
2.2
2.2
1.5
1.5
1.5
1.5
4.7
5.6
4.7
5.6
6.8
8.2
1.5
2.2
1.5
2.2
1
1.5
0.68
1
0.68
1
3.3
3.3
3.3
3.3
4.7
5.6
1
1
(Note 1)
COUT_EFF
[μF]
25 to 50
25 to 50
25 to 50
25 to 50
25 to 50
25 to 50
35 to 50
35 to 50
35 to 50
35 to 50
30 to 50
30 to 50
30 to 50
30 to 50
45 to 60
45 to 60
25 to 50
25 to 50
25 to 50
25 to 50
25 to 50
25 to 50
25 to 50
25 to 50
25 to 50
25 to 50
20 to 50
20 to 50
20 to 50
20 to 50
30 to 50
30 to 50
20 to 50
20 to 50
(Note 1) COUT_EFF is the sum of actual output capacitance.
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Selection of Components Externally Connected – continued
3. Output Voltage Setting, FB Capacitor
The output voltage can be set by the feedback resistance ratio connected to the FB pin. For recommended R1 and R2, use
the values listed in Table 20.
VOUT
The output voltage VOUT can be calculated as below.
CFB
R1
Error Amplifier
𝑉𝑂𝑈𝑇 =
𝑅1 +𝑅2
𝑅2
× 0.6 [V]
FB
R2
0.6 ≤ 𝑉𝑂𝑈𝑇 ≤ 14 [V]
0.6 V
(Typ)
𝑉𝑂𝑈𝑇 ≤ (𝑉𝐼𝑁 × 0.8) [V]
Figure 104. Feedback Resistor Circuit
The Constant On-Time control required the sufficient ripple voltage on FB voltage for the operation stability. This device is
designed to correspond to low ESR output capacitors by injecting the ripple voltage to FB voltage inside the IC. The FB
capacitor CFB should be set with the following expression as typical value in order to inject an appropriate ripple. For
recommended CFB, use the values listed in Table 20.
600 kHz setting
𝐶𝐹𝐵 =
𝑉𝑂𝑈𝑇 ×(1−𝑉𝑂𝑈𝑇 ⁄𝑉𝐼𝑁 )
𝑓𝑆𝑊 ×5.25×104
[F]
where:
𝑉𝐼𝑁 is the input voltage.
𝑉𝑂𝑈𝑇 is the output voltage.
fSW is the switching frequency 600 kHz (Typ).
1MHz, 2.2MHz setting
𝐶𝐹𝐵 =
𝑉𝑂𝑈𝑇 ×(1−𝑉𝑂𝑈𝑇 ⁄𝑉𝐼𝑁 )
𝑓𝑆𝑊 ×3.5×104
[F]
where:
𝑉𝐼𝑁 is the input voltage.
𝑉𝑂𝑈𝑇 is the output voltage.
fSW is the switching frequency 1 MHz, 2.2 MHz (Typ).
Load transient response and the loop stability depends on L, C OUT, R1, R2, and CFB. Actually, these characteristics may
change depending on PCB layout, wiring, the type of components, and the conditions (temperature, etc.). Be sure to
check them on the actual application.
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3. Output Voltage Setting, FB Capacitor – continued
Table 20. Recommended feedback resistance, CFB capacitance
Frequency
[MHz]
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
1
1
1
1
1
1
1
1
2.2
2.2
VIN [V]
VOUT [V]
R1 [kΩ]
R2 [kΩ]
CFB [pF]
12
24
5
12
5
12
24
24
12
24
5
12
5
12
24
24
12
24
3.3
3.3
3.3
1
1
5
5
12
3.3
3.3
3.3
1
1
5
5
12
3.3
3.3
1.5 + 120
1.5 + 120
120 + 330
180
180
220
220
68 + 560
1.5 + 120
1.5 + 120
120 + 330
180
180
220
220
68 + 560
1.5 + 120
1.5 + 120
27
27
100
270
270
30
30
33
27
27
100
270
270
30
30
33
27
27
82
82
39
33
27
100
100
180
82
82
33
27
22
100
100
180
33
33
4. Soft Start Capacitor (Soft Start Time Setting)
The soft start time tSS depends on the value of the capacitor connected to the SS pin. The tSS is 2 ms (Typ) when the SS
pin is left floating. The capacitor connected to the SS pin makes t SS more than 2 ms. The tSS and CSS can be calculated
using below equation. The CSS should be set in the range between 0.01 μF and 0.1 μF.
𝑡𝑆𝑆 =
𝐶𝑆𝑆 ×0.6×1.3
𝐼𝑆𝑆
[s]
where:
𝐼𝑆𝑆 is the Soft Start Charge Current 2.0 µA (Typ).
With CSS = 0.022 μF, tSS can be calculated as below.
𝑡𝑆𝑆 =
0.022 𝜇𝐹×0.6×1.3
2.0 𝜇𝐴
= 8.58 [ms]
5. VREG Capacitor
The VREG capacitor 2.2 μF is recommended. Connect the capacitor between the VREG pin and the AGND pin. For the
capacitance, take temperature characteristics, DC bias characteristics, and etc. into consideration to set to the actual
capacitance of no less than 0.82 μF.
6. Bootstrap Capacitor
The bootstrap capacitor 0.1 μF is recommended. Connect the capacitor between the SW pin and the BOOT pin. For the
capacitance, take temperature characteristics, DC bias characteristics, and etc. into consideration to set to the actual
capacitance of no less than 0.022 μF.
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PCB Layout Design
PCB layout design for DC/DC converter is very important. Appropriate layout can avoid various problems concerning power
supply circuit. Figure 105-a to Figure 105-c show the current path in a buck DC/DC converter circuit. The Loop 1 in Figure
105-a is a current path when H-side switch is ON and L-side switch is OFF, the Loop 2 in Figure 105-b is when H-side switch is
OFF and L-side switch is ON. The thick line in Figure 105-c shows the difference between Loop1 and Loop2. The current in
thick line change sharply each time the switching element H-side and L-side switch change from OFF to ON, and vice versa.
These sharp changes induce a waveform with harmonics in this loop. Therefore, the loop area of thick line that is consisted by
input capacitor and IC should be as small as possible to minimize noise. For more details, refer to application note of switching
regulator series “PCB Layout Techniques of Buck Converter”.
Loop1
VIN
H-side Switch
VOUT
L
CIN
COUT
L-side Switch
GND
GND
Figure 105-a. Current Path when H-side Switch = ON, L-side Switch = OFF
VIN
VOUT
L
H-side Switch
CIN
COUT
Loop2
L-side Switch
GND
GND
Figure 105-b. Current Path when H-side Switch = OFF, L-side Switch = ON
VIN
VOUT
L
CIN
COUT
High-Side FET
Low-Side FET
GND
GND
Figure 105-c. Difference of Current and Critical Area in Layout
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PCB Layout Design – continued
When designing the PCB layout, pay attention to the following points:
•
•
•
•
•
•
•
•
•
Connect the input capacitor CIN1 and CIN2 as close as possible to the VIN pin and the PGND pin on the same plane as
the IC.
Switching nodes such as SW are susceptible to noise due to AC coupling with other nodes. Route the inductor pattern L
as thick and as short as possible.
The feedback line connected to the FB pin should be as far away from the SW nodes as possible.
Place the output capacitor COUT away from input capacitor CIN1 and CIN2 to avoid harmonics noise from the input.
Separate the reference ground and the power ground and connect them through VIA. The reference ground should be
connected to the power ground that is close to the output capacitor COUT. It is because COUT has less high frequency
switching noise.
To provide excellent heat dissipation characteristics connect the VIN pins to the PCB VIN pattern by using thermal vias.
Place the bypass capacitor between the VREG and AGND pins at a position as close as possible to the pin.
When the SEL1 and SEL2 pins are left open, the parasitic capacitance with the VIN, SW, and BOOT pins should be 0.2
pF or less.
R0 is provided for the measurement of feedback frequency characteristics (optional). By inserting a resistor into R 0, it is
possible to measure the frequency characteristics of feedback (phase margin) using FRA etc. R0 is short-circuited for
normal use.
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PCB Layout Design – continued
R0
CREG
(2.2 μF)
RS2U
FB
CFB
12
RS2D
11
10
RS1U
RS1D
SEL1
R1A
SEL2
R1B
VREG
R2
9
CSS
AGND
13
8
VIN
SS
RPGD
18
EN
PGD
SW
15
6
VIN
BOOT
17
16
VIN
L
COUT1
PGND
4
PGND
3
2
PGND
1
GND
VOUT
SW
PGND
CIN1
(0.1 μF)
CBOOT
(0.1 μF)
5
VIN
CIN2
(10 μF)
PGD
7
14
EN
COUT2
GND
Figure 106. Application Circuit
Signal VIA
CSS
RPG D
CREG
R1A
CFB
R2
R1B
R0
Thermal VIA
BD9F500QUZ
VIN
L
CIN 1
CIN 2
CBO OT
VOUT
COUT2
COUT1
Pin 1
GND
GND
RS1D
RS1U
RS2D
Inner1 Layer
RS2U
Top Layer
VIN
VIN
GND
Inner2 Layer
Bottom Layer
Figure 107. Example of PCB Layout
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I/O Equivalence Circuits
5, 17. SW
VIN
6. BOOT
BOOT
VREG
VIN
BOOT
SW
30 Ω
350 Ω
SW
7. PGD
8. SS
VREG
PGD
10 kΩ
100 Ω
100 kΩ
3 kΩ
SS
25 kΩ
300 Ω
9. SEL1, 10. SEL2
11. VREG
VREG
VREG
VIN
BOOT
10 kΩ
20 kΩ
SEL1
SEL2
VREG
2.5 MΩ
10 kΩ
5 MΩ
1.5 MΩ
12. FB
14.EN
VREG
20 kΩ
EN
10 kΩ
10 kΩ
50 kΩ
100 kΩ
FB
10 kΩ
(Note) Resistor values are typical.
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Operational Notes
1.
Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power
supply pins.
2.
Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Furthermore, connect a capacitor to ground at
all power supply pins. Consider the effect of temperature and aging on the capacitance value when using electrolytic
capacitors.
3.
Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition. However,
pins that drive inductive loads (e.g. motor driver outputs, DC-DC converter outputs) may inevitably go below ground
due to back EMF or electromotive force. In such cases, the user should make sure that such voltages going below
ground will not cause the IC and the system to malfunction by examining carefully all relevant factors and conditions
such as motor characteristics, supply voltage, operating frequency and PCB wiring to name a few.
4.
Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5.
Recommended Operating Conditions
The function and operation of the IC are guaranteed within the range specified by the recommended operating
conditions. The characteristic values are guaranteed only under the conditions of each item specified by the electrical
characteristics.
6.
Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow
instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power
supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and
routing of connections.
7.
Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may
subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply
should always be turned off completely before connecting or removing it from the test setup during the inspection
process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during
transport and storage.
8.
Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and
unintentional solder bridge deposited in between pins during assembly to name a few.
9.
Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small
charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and
cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the
power supply or ground line.
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Operational Notes – continued
10. Regarding the Input Pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be
avoided.
Resistor
Transistor (NPN)
Pin A
Pin B
C
E
Pin A
N
P+
P
N
N
P+
N
Pin B
B
Parasitic
Elements
N
P+
N P
N
P+
B
N
C
E
Parasitic
Elements
P Substrate
P Substrate
GND
GND
Parasitic
Elements
GND
Parasitic
Elements
GND
N Region
close-by
Figure 108. Example of Monolithic IC Structure
11. Ceramic Capacitor
When using a ceramic capacitor, determine a capacitance value considering the change of capacitance with
temperature and the decrease in nominal capacitance due to DC bias and others.
12. Thermal Shutdown Circuit (TSD)
This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always
be within the IC’s maximum junction temperature rating. If however the rating is exceeded for a continued period, the
junction temperature (Tj) will rise which will activate the TSD circuit that will turn OFF power output pins. When the Tj
falls below the TSD threshold, the circuits are automatically restored to normal operation.
Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no
circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from
heat damage.
13. Over Current Protection Circuit (OCP)
This IC incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. This
protection circuit is effective in preventing damage due to sudden and unexpected incidents. However, the IC should
not be used in applications characterized by continuous operation or transitioning of the protection circuit.
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Ordering Information
B
D
9
F
5
0
0
Q
U
Z
Package
VMMP16LZ3030
-
E2
Packaging and forming specification
E2: Embossed tape and reel
Marking Diagram
VMMP16LZ3030 (TOP VIEW)
Part Number Marking
D9F
LOT Number
5 0 0
Pin 1 Mark
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Physical Dimension and Packing Information
Package Name
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Revision History
Date
Revision
02.Apr.2020
001
Changes
New Release
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Notice
Precaution on using ROHM Products
1.
Our Products are designed and manufactured for application in ordinary electronic equipment (such as AV equipment,
OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you
intend to use our Products in devices requiring extremely high reliability (such as medical equipment (Note 1), transport
equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car
accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or
serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.
Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any
damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific
Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅣ
CLASSⅢ
2.
ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3.
Our Products are designed and manufactured for use under standard conditions and not under any special or
extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any
special or extraordinary environments or conditions. If you intend to use our Products under any special or
extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of
product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used.
However, recommend sufficiently about the residue.) ; or Washing our Products by using water or water-soluble
cleaning agents for cleaning residue after soldering
[h] Use of the Products in places subject to dew condensation
4.
The Products are not subject to radiation-proof design.
5.
Please verify and confirm characteristics of the final or mounted products in using the Products.
6.
In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7.
De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in
the range that does not exceed the maximum junction temperature.
8.
Confirm that operation temperature is within the specified range described in the product specification.
9.
ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1.
When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2.
In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PGA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.004
Precautions Regarding Application Examples and External Circuits
1.
If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2.
You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1.
Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl 2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2.
Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3.
Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4.
Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
trade act, please consult with ROHM in case of export.
Precaution Regarding Intellectual Property Rights
1.
All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data.
2.
ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the
Products with other articles such as components, circuits, systems or external equipment (including software).
3.
No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM
will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to
manufacture or sell products containing the Products, subject to the terms and conditions herein.
Other Precaution
1.
This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2.
The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3.
In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4.
The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice-PGA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.004
Datasheet
General Precaution
1. Before you use our Products, you are requested to carefully read this document and fully understand its contents.
ROHM shall not be in any way responsible or liable for failure, malfunction or accident arising from the use of any
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this document is current as of the issuing date and subject to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the latest information with a ROHM sales
representative.
3.
The information contained in this document is provided on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate and/or error-free. ROHM shall not be in any way responsible or
liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccuracy or errors of or
concerning such information.
Notice – WE
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.001
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