Datasheet
12V to 76V input voltage range 3A output current
1ch Buck Converter Integrated FET
BD9G341AEFJ
General Description
The BD9G341AEFJ is a buck switching regulator with
integrated 150mΩ power MOSFET. Current mode
architecture provides fast transient response and a simple
phase compensation setup. The operating frequency is
programmable from 50kHz to 750kHz. Additional
protection features are included such as Over Current
Protection, Thermal shutdown and Under voltage lockout.
The under voltage lockout and hysteresis can be set by
external resistor.
Key specifications
■ Input voltage
■ Ref voltage(Ta=25°C)
(Ta=-40 to 85°C)
■ Max output current
■ Operating Temperature
■ Max junction temperature
Package(s)
Features
◼
◼
◼
◼
◼
◼
◼
◼
◼
12 to 76[V]
±1.5[%]
±2.0[%]
3 [A] (Max.)
-40°C to 85°C
150°C
HTSOP-J8
Wide input voltage range from 12V to 76V.
Integrated 80V/3.5A/150mΩ NchFET.
Current mode.
Variable frequency from 50kHz to 750kHz.
Accurate reference voltage. (1.0 V±1.5 %).
Precision ENUVLO threshold (±3%).
Soft-start function
0uA Standby current
Over Current Protection (OCP), Under Voltage
Lockout(UVLO), Thermal-Shutdown(TSD), Over
Voltage Protection (OVP)
Thermally enhanced HTSOP-J8 package
4.90mm x 6.00mm x 1.00mm
Applications
◼ Industrial distributed power applications.
◼ Battery powered equipment.
Typical Application Circuit
0.1uF
Vin=12～76V
VCC
C1:
10uF/100V
L : 33uH
BST
VOUT=5.0V /3A
LX
R1 Ω
D1
3.0kΩ
EN
C2:
100uF/6.3V
FB
VC
R2 Ω
GND
RT
0.75kΩ
6800pF
47kΩ
10kΩ
Figure 1. Typical Application Schematic
〇Product structure : Silicon monolithic integrated circuit
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BD9G341AEFJ
Pin Configuration
LX 1
8 VCC
GND 2
7 BST
Thermal Pad
VC 3
6 EN
FB 4
5 RT
Figure 2. Pin Configuration (TOP VIEW)
Pin Description
Pin No.
Pin Name
1
LX
Switching node. It should be connected as near as possible to the schottky
barrier diode, and inductor.
2
GND
Ground pin. GND pattern is kept from the current line of input capacitor to
output capacitor.
3
VC
The output of the internal error amplifier. The phase compensation
implementation is connected between this pin to GND.
4
FB
Voltage feedback pin. This pin is the error-amp input with the DC voltage is
set at 1.0V with feed-back operation.
5
RT
6
EN
7
BST
8
VCC
-
Thermal Pad
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Description
The internal oscillator frequency set pin. The internal oscillator is set with a
single resistor connected between this pin and the GND pin.
Recommended frequency range is 50kHz to 750kHz
Shutdown pin. If the voltage of this pin is below 1.3V, the regulator will be in a
low power state. If the voltage of this pin is between 1.3V and 2.4V. The IC
will be in standby mode. If the voltage of this pin is above 2.6V, the regulator
is operational. An external voltage divider can be used to set under voltage
threshold. If this pin is left open circuit. when converter is operating. This pin
output 10uA source current. If this pin is left open circuit, a 10uA pull up
current source configures the regulator fully operational.
Boost input for bootstrap capacitor
The external capacitor is required between the BST and the Lx pin.
A 0.1uF ceramic capacitor is recommended.
Input supply voltage pin.
Connect to GND.
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BD9G341AEFJ
Block Diagram
ON/OFF
EN
10uA
VCC
STANBY
↓
TSD
UVLO
Reference
+
REG
VREF
2.6V
shutdown
VC
OCP
Current Sense
AMP
OVP
FB
1.0V
BST
+
+
Error
AMP
Σ
Current
Comparator
R Q
+
S
0.15Ω
LX
Soft
Start
VOUT
20Ω
Soft Start
Oscillator
Oscillator
20Ω
GND
RT
Figure 3. Block Diagram
Description of Blocks
1.
Reference
This block generates inner reference voltage.
2.
REG
This block generates 8V reference voltage for bootstrap.
3.
OSC
This block generates inner CLK.
The internal oscillator is set with a single resistor connected between this pin and the GND pin.
Recommended frequency range is 50 kHz to 750 kHz. If RT pin connect to 47kohm, frequency is set 200 kHz.
4.
Soft Start
Soft Start of the output voltage of regulator prevents in-rush current during Start-up.
Soft Start time is 20msec (typ)
5.
ERROR AMP
This is an error amplifier what detects output signal, and outputs PWM control signal.
Internal reference voltage is set to 1.0V.
6.
ICOMP
This is a comparator that outputs PWM signal from current feed-back signal and error-amp output for current-mode.
7.
Nch FET SW
This is a 80V/150mΩ-Power Nch MOSFET SW that converts inductor current of DC/DC converter
Since the current rating of this FET is 3.5A, it should be used within 3.5A including the DC current and ripple current of the coil.
8.
UVLO
This is a Low Voltage Error Prevention Circuit.
This prevents internal circuit error during increase of Power Supply Voltage and during decline of Power supply Voltage.
It monitors VCC Pin Voltage and internal REG Voltage, When VCC Voltage becomes 11V and below, UVLO turns OFF
all Output FET and turns OFF the DC/DC Comparator Output, and the Soft Start Circuit resets.
Now this Threshold has Hysteresis of 200mV.
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BD9G341AEFJ
9.
EN
Shutdown function. If the voltage of this pin is below 1.3V, the regulator will be in a low power state. If the voltage of this
pin is between 1.3V and 2.4V will be standby mode. If the voltage of this pin is above 2.6V, the regulator is operational.
An external voltage divider can be used to set under voltage threshold. If this pin is left open circuit. when converter is
operating. This pin output 10uA source current. If this pin is left open circuit, a 10uA pull up current source configures the
regulator fully operational. When IC turn off, EN pin is pulled down by pull down resistor that sink above 10uA.
10. OCP
Over current protection
If the current of power MOSFET is over 6.0A (typ), this function reduces duty pulse –by- pulse and restricts the
over current. If IC detects OCP 2 times sequentially, the device will stop and after 20 msec restart.
11. TSD
This is Thermal Shutdown Detection
When it detects an abnormal temperature exceeding Maximum Junction Temperature (Tj=150°C), it turns OFF all Output
FETs, and turns OFF the DC/DC Comparator Output. When Temperature falls, and the IC automatically returns
12. OVP
Over voltage protection.
Output voltage is monitored with FB terminal, and output FET is turned off when it becomes 120% of set-point
voltage.
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BD9G341AEFJ
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Maximum input voltage
VCC
80
V
BST to GND
VBST
85
V
Maximum input current
Imax
3.5
A
BST to LX
⊿VBST
15
V
EN to GND
VEN
80
V
LX to GND
VLX
80
V
VC to GNF
VVC
7
V
FB to GND
VFB
7
V
RT to GND
VRT
7
V
Operating Temperature
Topr
-40 to +85
°C
Storage Temperature
Tstg
-55 to +150
°C
Junction Temperature
Tjmax
150
°C
Caution1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an
open circuit between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in
case the IC is operated over the absolute maximum ratings.
Caution 2: Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in
deterioration of the properties of the chip. In case of exceeding this absolute maximum rating, design a PCB with thermal resistance taken into
consideration by increasing board size and copper area so as not to exceed the maximum junction temperature rating.
Thermal Resistance (Note 1)
Parameter
Thermal Resistance (Typ)
Symbol
1s(Note 3)
2s2p(Note 4)
Unit
HTSOP-J8
Junction to Ambient
θJA
125.3
27.6
°C/W
Junction to Top Characterization Parameter(Note 2)
ΨJT
21
13
°C/W
(Note 1) Based on JESD51-2A(Still-Air)
(Note 2) The thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside
surface of the component package.
(Note 3) Using a PCB board based on JESD51-3.
(Note 4) Using a PCB board based on JESD51-5, 7.
Layer Number of
Measurement Board
Single
Material
Board Size
FR-4
114.3mm x 76.2mm x 1.57mmt
Top
Copper Pattern
Thickness
Footprints and Traces
70μm
Layer Number of
Measurement Board
4 Layers
Thermal Via(Note5)
Material
Board Size
FR-4
114.3mm x 76.2mm x 1.6mmt
Top
Pitch
1.20mm
2 Internal Layers
Diameter
Φ0.30mm
Bottom
Copper Pattern
Thickness
Copper Pattern
Thickness
Copper Pattern
Thickness
Footprints and Traces
70μm
74.2mm x 74.2mm
35μm
74.2mm x 74.2mm
70μm
(Note 5) This thermal via connects with the copper pattern of all layers.
Recommended Operating Ratings(Ta=25°C)
Item
Rating
Symbol
Unit
Min
Typ
Max
VCC
12
―
76
V
Output voltage
VOUT
1.0(Note6)
―
VCC(Note7)
V
Output current
IOUT
-
―
3.0
A
Oscillator frequency
Fosc
50
―
750
kHz
Power Supply Voltage
(Note6) Restricted by minduty=f×MinOn Time ( f :frequency)
If the voltage of Vcc×minduty [V] lower than 1V, this value is minimum output.
(Note7) Restricted by maxduty =1-f×forced off time
The maximum output is (Vcc– Iout*Ron)×maxduty
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BD9G341AEFJ
Electrical Characteristics (Unless otherwise specified Ta=25°C, VCC=48V, Vo=5V, EN=3V, RT=47kΩ )
Parameter
Symbol
Limit
Min
Typ
Max
Unit
Condition
【Circuit Current】
Stand-by current of VCC
Ist
―
0
10
µA
VEN=0V
Circuit current of VCC
Icc
―
1.5
2.0
mA
FB=1.5V
Detect Voltage
Vccuv
10.4
11
11.6
V
Hysteresis width
Vuvhy
―
200
300
mV
VFBN
0.985
1.000
1.015
V
VFBA
IFB
Isource
Isink
Tsoft
AVEA
1.000
0
40
-40
20
10000
300
1.020
1
65
-15
25
―
―
V
uA
uA
uA
msec
V/V
GEA
0.980
-1
15
-65
15
―
―
GCS
―
10
―
A/V
Iocp
3.5
6.0
―
A
【Under Voltage Lock Out (UVLO)】
【Error Amp】
FB threshold voltage
FB Input bias current
VC source current
VC sink current
Soft start time
Error amplifier DC gain
Trans conductance
Ta=25°C
Ta=-40 to 85°C
VFB=2.0V
µA/V
【Current Sense Amp 】
VC to switch current trans conductance
【OCP】
Detect current
OCP latch count
NOCP
―
2
―
count
OCP latch hold time
TOCP
15
20
25
msec
RonH
―
150
―
mΩ
VENON
1.3
―
2.4
V
Venuv
IEN
2.52
9.0
2.6
10.0
2.68
11.0
V
µA
Fosc
Toff
180
―
200
―
220
500
kHz
nsec
【Output】
Lx NMOS ON resistance
【CTL】
EN Pin inner REG on voltage
EN Pin IC output on threshold
EN pin
【Oscillator】
Oscillator frequency
Forced off time
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ON
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IC on or off threshold
VEN=3V
RTR=47kΩ
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BD9G341AEFJ
Typical Performance Characteristics
220
1.02
215
1.015
210
1.01
FB THRESHOLD [V]
FREQUENCY [kHz]
(Unless otherwise specified, Ta=25°C，VCC=24V, VOUT=5V)
205
200
195
190
1.005
1
0.995
0.99
185
0.985
180
0.98
-50
0
50
12
100
Fig.4 Oscillator Frequency - Temperature
72
Fig.5 FB Threshold Voltage- Input Voltage
500
1.02
480
FORCED OFF TIME [n sec]
1.015
FB THRESHOLD [V]
52
INPUT VOLTAGE[V]
TEMPERATURE [℃ ]
1.01
1.005
1
0.995
0.99
0.985
460
440
420
400
380
360
340
320
300
0.98
-50
0
50
-50
100
Fig.6 FB Threshold Voltage - Temperature
11.8
7.5
11.6
7
OCP THRESHOLD [A]
8
11.4
11.2
11
10.8
10.6
10.4
6
5.5
5
4.5
4
10
3.5
50
-50
100
0
50
100
TEMPERATURE [℃ ]
TEMPERATURE [℃ ]
Fig.8 UVLO Threshold Voltage - Temperature
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100
6.5
10.2
0
50
Fig.7 Forced off time - Temperature
12
-50
0
TEMPERATURE [℃ ]
TEMPERATURE [℃ ]
UVLO THRESHOLD [V]
32
Fig.9 OCP Detect Current - Temperature
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EN PIN INNER REG THRESHOLD [V]
25
SOFT START TIME [msec]
24
23
22
21
20
19
18
17
16
15
-50
0
50
2.3
2.1
1.9
1.7
1.5
1.3
-50
100
50
100
TEMPERATURE [℃ ]
TEMPERATURE [℃ ]
Fig.11 EN Pin Inner REG ON
Threshold - Temperature
Fig.10 Soft Start Time - Temperature
11
EN UVLO SOURCE CURRENT[uA]
2.7
EN UVLO THRESHOLD [V]
0
2.65
2.6
2.55
10.8
10.6
10.4
10.2
10
9.8
9.6
9.4
9.2
9
2.5
-50
0
50
-50
100
0
50
100
TEMPERATURE [℃ ]
TEMPERATURE [℃ ]
Fig.12 ENUVLO Threshold - Temperature
Fig.13 EN Source Current - Temperature
Fig.14 NMOS ON Resistance -Temperature
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BD9G341AEFJ
Reference Characteristics of Typical Application Circuits
Vout=5V, f=200kHz
(All the external components can be substituted by equivalents)
0.1uF
Vin=12～76V
VCC
C1:
10uF/100V
L : 33uH
BST
VOUT=5.0V /3A
LX
R1 Ω
D1
3.0kΩ
EN
C2:
100uF/6.3V
FB
VC
R2 Ω
GND
0.75kΩ
RT
6800pF
10kΩ
47kΩ
Parts ：
L
：SUMIDA
CDRH129HF
33μH
C1
：TDK
C5750X7S2A106K
10μF/100V
C2
：TDK
C4532X5R0J107M
100μF/6.3V
D1
：Rohm
RB095BGE-90TL
100
90
VCC=24V
80
48V
EFFICIENCY [%]
70
60
50
60V
40
76V
30
20
10
0
1
10
100
1000
OUTPUT CURRENT[mA]
Fig.15 Efficiency – Output Current
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BD9G341AEFJ
VEN [5V/div]
Io [500mA/div]
Vout [2V/div]
Overshoot Voltage: 150mV
VLx [10V/div]
Vout [100mV/div]
ILx [0.5A/div]
Undershoot Voltage: 230mV
5msec/div
2msec/div
Fig.16 Start-up Characteristics
Fig.17 Load Response
Iout:100mA ⇔1A
Vout:offset 5V
40mV/div
Vout:offset 5V
40mV/div
Vout Ripple :24mV
Vout Ripple :32mV
5usec/div
10usec/div
Fig.18 Lx Switching/Vout Ripple
Io = 100mA
Fig.19 Lx Switching/Vout Ripple
Io=1A
Phase
Phase
Gain
Gain
Fig.20 Frequency Response
Io=100mA
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Fig.21 Frequency Response
Io=3.0A
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BD9G341AEFJ
Reference Characteristics of Typical Application Circuits
Vout=3.3V, f=200kHz
(All the external components can be substituted by equivalents)
0.1uF
Vin=12～76V
VCC
C1:
10uF/100V
L : 33uH
BST
VOUT=3.3V /3A
LX
R1 Ω
D1
1.3kΩ
EN
C2:
100uF/6.3V
FB
0.56kΩ
VC
R2 Ω
GND
0.01uF
RT
47kΩ
Parts ：
L
6.2kΩ
：SUMIDA
CDRH129HF
33μH
C1
：TDK
C5750X7S2A106K
10μF/100V
C2
：TDK
C4532X5R0J107M
100μF/6.3V
D1
：Rohm
RB095BGE-90TL
100
90
VCC=24V
80
EFFICIENCY [%]
70
48V
60
50
60V
40
30
76V
20
10
0
1
10
100
1000
OUTPUT CURRENT[mA]
Fig.22 Efficiency – Output Current
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Io [500mA/div]
VEN [5V/div]
Vout [2V/div]
Vout [100mV/div]
VLx [10V/div]
ILx [0.5A/div]
Overshoot Voltage: 140mV
Undershoot Voltage: 200mV
5msec/div
2msec/div
Fig.23 Start-up Characteristics
Fig.24 Load Response
Iout:100mA ⇔1A
Vout:offset 3.3V
40mV/div
Vout:offset 3.3V
40mV/div
Vout Ripple :32mV
10usec/div
5usec/div
Fig.25 Lx Switching/Vout Ripple
Io = 100mA
Fig.26 Lx Switching/Vout Ripple
Io=1A
Phase
Phase
Gain
Gain
Fig.27 Frequency Response
Io=100mA
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Fig.28 Frequency Response
Io=3A
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BD9G341AEFJ
Detailed Description
◇Frequency setting
Arbitrary internal oscillator frequency setup is possible by connecting RT resistance. Recommended frequency range is 50
kHz to 750 kHz.
For setting frequency f [Hz] 、RT resistance is looked for using the following formula.
1
− 400 10−9
f
RT =
[Ω]
96.48 10−12
Frequency [kHz]
If setting frequency is 200kHz, RT is 47kΩ.
RT resistance is related to frequency as shown in Figure 26.
1000
900
800
700
600
500
400
300
200
100
0
1
10
100
RT Resistance [kohm]
Fig.29 Oscillator Frequency - RT resistance
◇External UVLO threshold
The high precision reset function is built in EN terminal of BD9G341AEFJ, and arbitrary low-voltage malfunction prevention
setup is possible by connecting EN pin to resistance division of input voltage.
When you use, please set R1 and R2 to arbitrary voltage of IC turned on (Vuv) and hysteresis (Vuvhys) like below.
0.1uF
Vin=Vuv～76V
VCC
C1:
10uF/100V
L : 33uH
BST
VOUT=5.0V /3A
LX
R1 Ω
D1
C2:
100uF/6.3V
3.0kΩ
EN
FB
VC
R2 Ω
GND
RT
0.75kΩ
6800pF
47kΩ
10kΩ
Fig.30 External UVLO setup
R1=
Vuvhys
IEN
[ohm]
R2=
VEN×R1
Vuv-VEN
[ohm]
IEN: EN pin source current 10uA(typ) VEN: EN pin output on threshold 2.6V(typ)
As an example in typical sample, When Vcc voltage which IC turned on 15V, Hysteresis width 1V, The resistance divider
set to R1=100kΩ,R2=20kΩ.
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◇OCP operation
The device has over current protection for protecting the FET from over current.
To detect OCP 2 times sequentially, the device will stop and after 20msec restart.
OCP threshold
VC
VC voltage discharged
by OCP latch
VC voltage rising by
output connect to GND
force the High side FET OFF
by detecting OCP current
(pulse by pulse protection)
Lx
output connect to GND
VOUT
OCP
set the OCP latch by detecting
the OCP current 2 times sequencially
OCP latch reset after 1320msec
msec
(300ｋHz 4000 counts)
OCP_LATCH
Fig.31 Timing chart at OCP operation
◇start up with output pre-bias voltage
It starts in the state that the voltage remains in the output , in the cases that big capacitor is connected to output ,
IC discharge output voltage min 7.5V by FET ON 300nsec in period to charge bootstrap capacitor between BST to LX.
When it is necessary to make a startup sequence, please forcibly discharge the output voltage.
Vout 5.0V/div
Discharge output
LX
20V/div
5msec /div
Figure 32. pre-bias start up waveform
VCC=48V, Vout=24V
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◇Restriction of output Bias application
The application that output connects to the other power supply is not recommended because the output voltage is not
discharged in startup.
Vin
VCC
BST
Vout
Vbias
LX
R1 Ω
Load
EN
FB
VC
R2 Ω
GND
RT
Figure 33. Output Bias NG application
When output connect to voltage supply, please insert a diode to the IC output side.
Vin
VCC
BST
Vout
Vbias
LX
R1 Ω
Load
EN
FB
VC
R2 Ω
GND
RT
Figure 34. Output Bias OK application
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Application Components Selection Method
(1) Inductors
Something of the shield type that fulfills the current rating (Current value
Ipeak below), with low DCR is recommended. Value of Inductance influences
Inductor Ripple Current and becomes the cause of Output Ripple.
In the same way as the formula below, this Ripple Current can be made small
for as big as the L value of Coil or as high as the Switching Frequency.
IL
・・・ (1)
2
VCC − VOUT VOUT 1
IL =
L
VCC
f
ΔIL
Ipeak = IOUT +
Fig.35 inductor Current
・・・ (2)
(⊿IL: Output Ripple Current, VCC: Input Voltage, VOUT: Output Voltage, f: Switching Frequency)
For design value of Inductor Ripple Current, please carry out design tentatively with about 20% to 50% of Maximum Output
Current.
In the BD9G341AEFJ, it is recommended the below series of 4.7μH to 33μH inductance value.
Recommended Inductor：SUMIDA CDRH129HF Series
(2) Output Capacitor
In order for capacitor to be used in output to reduce output ripple, Low ceramic capacitor of ESR is recommended.
Also, for capacitor rating, on top of putting into consideration DC Bias characteristics, please use something whose maximum
rating has sufficient margin with respect to the Output Voltage.
Output ripple voltage is looked for using the following formula.
VPP = IL
1
+ IL RESR
2 f COUT
・・・ (3)
Please design in a way that it is held within Capacity Ripple Voltage.
In the BD9G341AEFJ, it is recommended a ceramic capacitor over 10μF.
The maximum value of the output capacitor is limited by Start Up Rush current
The rush current is expressed by the following
(Rush Current )=（Current of the error amplifier reply delay）+
Cout Vout
Tsoftstart _ min
+Ripple Current
+Output Current
(Output Capacitor Charge current)
Current of the error amplifier reply delay depend on the phase compensation element and output capacitor.
As output capacitor big, Rush Current grows big.
Please verify actual equipment that the Rush Current become smaller than OCP Threshold(min3.5A).
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VOUT
(3) Output voltage setting
ERROR AMP
R1
The internal reference voltage of ERROR AMP is 1.0V.
Output voltage is determined like (4) types.
FB
R2
VOUT =
R1 + R2
R2
・・・ (4)
VREF
1.0 V
Fig.36 Output voltage setting
(4) Bootstrap Capacitor
Please connect from 0.1uF (Laminate Ceramic Capacitor) between BST Pin and Lx Pins.
(5) Catch Diode
BD9G341AEFJ should be taken to connect external catch diode between Lx Pin and GND Pin. The diode require adherence to
absolute maximum Ratings of application. Opposite direction voltage should be higher than maximum voltage of Lx Pin
(VCCMAX + 0.5V). The peak current is required to be higher than IOUTMAX +⊿IL.
(6) Input Capacitor
BD9G341AEFJ needs an input decoupling capacitor. It is recommended a low ceramic capacitor ESR over 4.7μF. Additionally, it
should be located as close as possible.
Capacitor should be selected by maximum input voltage with input ripple voltage.
Input ripple voltage is calculated by using the following formula.
VCC =
IOUT
VOUT VOUT
・・・
1f CVCC VCC VCC
(5)
CVCC: Input capacitor
RMS ripple current is calculated by using the following formula.
ICVCC = IOUT
VOUT
VOUT
(1 −
)
VCC
VCC
・・・ (6)
If VCC=2VOUT, RMS ripple current is maximum. That is determined by (9).
ICVCC_max =
IOUT
2
・・・ (7)
(7) About Adjustment of DC/DC Comparator Frequency Characteristics
Role of Phase compensation element C1, C2, R3
0.1uF
VCC
L : 33uH
BST
VOUT=5.0V /3A
LX
10uF/100V
R1 Ω
D1
3.0kΩ
100uF/6.3V
EN
FB
VC
R2 Ω
GND
RT
0.75kΩ
C1
47kΩ
C2
R3
Fig.37 Feedback voltage resistance setting method
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Stability and Responsiveness of Loop are controlled through VC Pin which is the output of Error Amp.
The combination of zero and pole that determines Stability and Responsiveness is adjusted by the combination of resistor and
capacitor that are connected in series to the VC Pin.
DC Gain of Voltage Return Loop can be calculated for using the following formula.
Adc = Rl G CS A VEA
VFB
VOUT
・・・ (8)
Here, VFB is Feedback Voltage (1.0V).AEA is Voltage Gain of Error amplifier (typ: 80dB),
Gcs is the Trans-conductance of Current Detect (typ: 10A/V), and Rl is the Output Load Resistance value.
There are 2 important poles in the Control Loop of this DC/DC.
The first occurs with/ through the output resistance of Phase compensation Capacitor (C1) and Error amplifier.
The other one occurs with/through the Output Capacitor and Load Resistor.
These poles appear in the frequency written below.
fp1 =
G EA
2 C1 A VEA
fp2 =
1
2 COUT Rl
・・・ (9)
・・・ (10)
Here, GEA is the trans-conductance of Error amplifier (typ: 300 µA/V).
Here, in this Control Loop, one zero becomes important. With the zero which occurs because of Phase compensation Capacitor
C1 and Phase compensation Resistor R3, the Frequency below appears.
fz1 =
1
2 C1 R3
・・・ (11)
Also, if Output Capacitor is big, and that ESR (RESR) is big, in this Control Loop, there are cases when it has an important,
separate zero (ESR zero).
This ESR zero occurs due to ESR of Output Capacitor and Capacitance, and exists in the Frequency below.
fz ESR =
1
2 COUT RESR
・・・ (12)
(ESR zero)
In this case, the 3rd pole determined with the 2nd Phase compensation Capacitor (C2) and Phase Correction Resistor (R3) is used
in order to correct the ESR zero results in Loop Gain.
This pole exists in the frequency shown below.
fp3 =
1
2 C2 R3
・・・ (13)
(Pole that corrects ESR zero)
The target of Phase compensation design is to create a communication function in order to acquire necessary band and Phase
margin.
Cross-over Frequency (band) at which Loop gain of Return Loop becomes “0” is important.
When Cross-over Frequency becomes low, Power supply Fluctuation Response, Load Response etc. worsens.
On the other hand, when Cross-over Frequency is too high, instability of the Loop can occur.
Tentatively, Cross-over Frequency is targeted to be made 1/20 or below of Switching Frequency.
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Selection method of Phase Compensation constant is shown below.
1.
Phase Compensation Resistor (R3) is selected in order to set to the desired Cross-over Frequency.
Calculation of RC is done using the formula below.
R3 =
2 COUT fc VOUT
G EA G CS
VFB
・・・ (14)
Here, fc is the desired Cross-over Frequency. It is made about 1/20 and below of the Normal Switching Frequency (fs).
2.
Phase compensation Capacitor (C1) is selected in order to achieve the desired phase margin.
In an application that has a representative Inductance value (about several 4.7µH to 33µH), by matching zero of
compensation to 1/4 and below of the Cross-over Frequency, sufficient Phase margin can be acquired. C1 can be
calculated using the following formula.
C1
3.
4
2 R3 fc
・・・ (15)
Examination whether the second Phase compensation Capacitor C2 is necessary or not is done.
If the ESR zero of Output Capacitor exists in a place that is smaller than half of the Switching Frequency, a second Phase
compensation Capacitor is necessary. In other words, it is the case wherein the formula below happens.
1
fs
2 COUT RESR 2
・・・ (16)
In this case, add the second Phase compensation Capacitor C2, and match the frequency of the third pole to the
Frequency fp3 of ESR zero.
C2 =
COUT RESR
R3
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PCB Layout
Layout is a critical portion of good power supply design. There are several signals paths that conduct fast changing currents
or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies
performance. To help eliminate these problems, the VCC pin should be bypassed to ground with a low ESR ceramic bypass
capacitor with B dielectric. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the
VCC pin, and the anode of the catch diode. See Fig.28 for a PCB layout example. The GND pin should be tied directly to the
thermal pad under the IC and the thermal pad. In order to reduce the influence of the impedance and L of the parasitic, the
high current line is thick and short.
Input decoupling capacitor should be located as close to the VCC pins
In order to minimize the parasitic capacitor and impedance of pattern, catch diode and inductance should be located as close
to the Lx pin.
The thermal pad should be connected to any internal PCB ground planes using multiple VIAs directly under the IC.
GND feedback resistor, phase compensation element and RT resistor don’t give the common impedance resistor against
high current line.
VOUT
Output
Capacitor
Inductor
Topside
Ground
Area
Catch
Diode
Compensation
Network
LX
VCC
GND
BST
VC
EN
FB
RT
Input Bypass
Capacitor
VCC
Route BST Capacitor
Trace on another layer to
provide with wide path for
topside ground
Resistor
Divider
Signal VIA
Thermal VIA
Figure 38. Evaluation Board Pattern
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Power Dissipation Estimate
The following formulas show how to estimate the device power dissipation under continuous mode operations. They should
not be used if the device is working in the discontinuous conduction mode.
The device power dissipation includes:
1) Conduction loss：Pcon = IOUT2 × RonH × VOUT/VCC
2) Switching loss： Psw = 16n × VCC × IOUT × fsw
3) Gate charge loss：Pgc = 500p×7×7×fsw
4) Quiescent current loss：Pq = 1.5m × VCC
Where:
IOUT is the output current (A）, RonH is the on-resistance of the high-side MOSFET（Ω）, VOUT is the output voltage
(V).
VCC is the input voltage (V) fsw is the switching frequency (Hz).
Therefore
Power dissipation of IC is the sum of above dissipation.
Pd = Pcon + Psw + Pgc + Pq
For given Tj, Tj =Ta + θja × Pd
Where:
Pd is the total device power dissipation (W), Ta is the ambient temperature (°C)
Tj is the junction temperature (°C), θja is the thermal resistance of the package (°C)
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I/O Equivalent Schematic
Pin.
No
Pin.
Name
1
Lx
2
GND
7
BST
8
VCC
Pin Equivalent Schematic
Pin.
No
Pin.
Name
5
RT
Pin Equivalent Schematic
RT
GND
VCC
3
VC
VC
6
GND
EN
EN
GND
FB
4
FB
GND
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Operational Notes
1.
Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power supply
pins.
2.
Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the
digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog
block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and
aging on the capacitance value when using electrolytic capacitors.
3.
Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.
4.
Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5.
Recommended Operating Conditions
These conditions represent a range within which the expected characteristics of the IC can be approximately obtained.
The electrical characteristics are guaranteed under the conditions of each parameter.
6.
Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush
current may flow instantaneously due to the internal powering sequence and delays, especially if the IC
has more than one power supply. Therefore, give special consideration to power coupling capacitance,
power wiring, width of ground wiring, and routing of connections.
7.
Operation Under Strong Electromagnetic Field
Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction.
8.
Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may subject
the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply should
always be turned off completely before connecting or removing it from the test setup during the inspection process. To
prevent damage from static discharge, ground the IC during assembly and use similar precautions during transport and
storage.
9.
Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and
unintentional solder bridge deposited in between pins during assembly to name a few.
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10. Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small charge
acquired in this way is enough to produce a significant effect on the conduction through the transistor and cause
unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the power
supply or ground line.
11. Regarding the Input Pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be
avoided.
Resistor
Transistor (NPN)
Pin A
Pin B
C
E
Pin A
N
P+
P
N
N
P+
N
Pin B
B
Parasitic
Elements
N
P+
N P
N
P+
B
N
C
E
Parasitic
Elements
P Substrate
P Substrate
GND
GND
Parasitic
Elements
GND
Parasitic
Elements
GND
N Region
close-by
Figure 39. Example of monolithic IC structure
12. Ceramic Capacitor
When using a ceramic capacitor, determine the dielectric constant considering the change of capacitance with
temperature and the decrease in nominal capacitance due to DC bias and others.
13. Area of Safe Operation (ASO)
Operate the IC such that the output voltage, output current, and power dissipation are all within the Area of Safe
Operation (ASO).
14. Thermal Shutdown Circuit(TSD)
This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always
be within the IC’s power dissipation rating. If however the rating is exceeded for a continued period, the junction
temperature (Tj) will rise which will activate the TSD circuit that will turn OFF all output pins. When the Tj falls below
the TSD threshold, the circuits are automatically restored to normal operation.
Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no
circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from heat
damage.
15. Over Current Protection Circuit (OCP)
This IC incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. This
protection circuit is effective in preventing damage due to sudden and unexpected incidents. However, the IC should
not be used in applications characterized by continuous operation or transitioning of the protection circuit.
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Ordering Information
B D
9
G
3
4
1
A
E
F
J
-
Package
EFJ: HTSOP-J8
Part Number
E2
Packaging and forming specification:
Embossed tape and reel
Marking Diagrams
HTSOP-J8(TOP VIEW)
Part Number Marking
9 G 3 4 1 A
LOT Number
1PIN MARK
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Physical Dimension, Tape and Reel Information
Package Name
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Revision History
Date
Revision
Changes
15.Jun.2015
06.Oct.2015
001
002
16.Dec.2015
003
28.Sep.2016
004
24.Dec.2020
005
New Release
P16 Correct error in writing
P13 start up with output pre-bias voltage
P14 Restriction of output Bias application
P15 Output Capacitor maximum value
Correct error in writing
P20 Fig39
P20 calculation of Gate charge loss
Pgc = 500p×7×fsw ⇒Pgc = 500p×7×7×fsw
P5 Removed power dissipation in absolute maximum ratings
Added thermal resistance based on JEDEC standard.
Added VC-GND and RT-GND absolute maximum ratings.
Added Caution under the absolute maximum ratings.
P9, 11 Added the comment “All the external components can be substituted by equivalents”
P13 Fig.29 Modified the horizontal axis.
P16 (1)Inductors l.9 Corrected error in writing (“Maximum Input Current” ⇒ “Maximum
Output Current).
P20 Removed power dissipation characteristic.
P22 Modified I/O Equivalent Schematic of Pin No.1, 2, 7, 8.
P23 Deleted 5. Thermal Consideration in Operational notes
P25 Fixed Marking Diagram
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Notice
Precaution on using ROHM Products
1.
Our Products are designed and manufactured for application in ordinary electronic equipment (such as AV equipment,
OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you
intend to use our Products in devices requiring extremely high reliability (such as medical equipment (Note 1), transport
equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car
accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or
serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.
Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any
damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific
Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅣ
CLASSⅢ
2.
ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
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a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
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Our Products are designed and manufactured for use under standard conditions and not under any special or
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[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
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H2S, NH3, SO2, and NO2
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[g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used.
However, recommend sufficiently about the residue.) ; or Washing our Products by using water or water-soluble
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[h] Use of the Products in places subject to dew condensation
4.
The Products are not subject to radiation-proof design.
5.
Please verify and confirm characteristics of the final or mounted products in using the Products.
6.
In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7.
De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in
the range that does not exceed the maximum junction temperature.
8.
Confirm that operation temperature is within the specified range described in the product specification.
9.
ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1.
When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2.
In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PGA-E
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Rev.004
Precautions Regarding Application Examples and External Circuits
1.
If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2.
You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1.
Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl 2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2.
Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
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3.
Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4.
Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
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2.
The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3.
In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4.
The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice-PGA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.004
Datasheet
General Precaution
1. Before you use our Products, you are requested to carefully read this document and fully understand its contents.
ROHM shall not be in any way responsible or liable for failure, malfunction or accident arising from the use of any
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this document is current as of the issuing date and subject to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the latest information with a ROHM sales
representative.
3.
The information contained in this document is provided on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate and/or error-free. ROHM shall not be in any way responsible or
liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccuracy or errors of or
concerning such information.
Notice – WE
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.001
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