BH6173GUL_11

1/4 Structure Product Type Functions Silicon Monolithic Integrated Circuit Power Management LSI for Multimedia LSI on Cellular BH6173GUL ・1ch 500mA, high efficiency Step-down Converter. (16 steps adjustable Vout by I2C) ・3-channel CMOS-type LDOs. (16 steps adjustable Vout by I2C) ・LDO and Stepdown converter Power ON/OFF control enabled by I2C interface ・I2C compatible Interface. (Selectable device address is “1001010”and “1001111”) ・Wafer Level CSP package(2.05mm×2.05mm) for space-constrained applications. Absolute Maximum Ratings（Ta=25C） Parameter Symbol Rating Unit Maximum Supply Voltage (VBAT1,PVCC, PBAT) VBATMAX 6.0 Maximum Supply Voltage (VIO) VIOMAX 4.5 Maximum Input Voltage 1 VINMAX1 VBAT + 0.3 (LX, FB, OUT1, OUT2, OUT3, ADRS) Maximum Input Voltage 2 VINMAX2 VIO + 0.3 (NRST, CLK, DATA) Power Dissipation Pd 690*1 Operating Temperature Range Topr -35 ～ +85 Storage Temperature Range Tstg -55 ～ +125 *1 This is the allowable loss of when it is mounted on a ROHM specification board 50mm×58mm. To use at temperature higher than 25C , derate 1% per 1C. Recommended Operating Conditions (Ta=25C) Parameter VBAT, PBAT Voltage Symbol VBAT * 2 3 V V V V mW ℃ ℃ Range 2.20 ～ 5.20 Unit V V VIO Voltage VIO * 1.70 ～ 4.20 *2 Whenever the VBAT, PVCC and PBAT voltage is under the LDO, SWREG output voltage, the LDO and SWREG output is not guaranteed to meet its published specifications. *3 The VIO Voltage must be under the Battery Voltage VBAT, PBAT at any times. *This product is not especially designed to be protected from radioactivity. REV. B 2/4 ● Overview Dimensions (VCSP50L2) 1PIN MARK Lot. No. ● Ball Descriptions Ball No. B2 C3 D3 D1 A1 A2 A3 A4 C2 C1 D2 D4 C4 B1 B4 B3 PIN Name DATA CLK VBAT1 PVCC PBAT LX PGND FB NRST OUT1 OUT2 OUT3 REFC VIO GND ADRS 6173 2.05±0.05 0.1±0.05 2.05±0.05 0.55MAX S P=0.5×3 0.275±0.05 B 4 S 0.06 16-φ0.25±0.05 0.05 AB D C (φ0.15)INDEX POST B A 1 2 3 A 0.275±0.05 P=0.5×3 Unit (mm) ● Block Diagram VBAT1 VIO DATA CLK ADRS NRST I2C IF LDO1 1.00-3.30V 0.1V step init 1.80V OUT1 300mA PBAT PVCC LDO2 LX init 2.80V OUT2 300mA S WREG PGND FB 0.80-2.40V init 1.00V 500mA 1.00-3.30V 0.1V step LDO3 1.20-3.30V 0.1V step init 2.80V OUT3 300mA REFC REF REV. B GND 3/4 Electrical Characteristics (Unless otherwise specified, Ta=25C, VBAT=PVCC=PBAT=3.6Ｖ, VIO=2.6V) Parameter ●Circuit Current VBAT Circuit Current 1 (OFF) Circuit Current 2 (Standby) IQ1 IQ2 0.4 0.7 1 1.4 μA μA LDO1~3=OFF, SWREG1=OFF, NRST=L, VIO=0V LDO1~3=OFF, SWREG1=OFF, NRST=H, VIO=2.6V LDO1~3=ON(no load, initial voltage) SWREG1=ON (no load、initial voltage Addres06h="00" PWM/PFM AUTO MODE) NRST=H, VIO=2.6V Condition Symbol Min. Typ. Max. Unit Condition Circuit Current 3 (Active) IQ3 - 170 350 μA Electrical Characteristics (Unless otherwise specified, Ta=25C, VBAT=PVCC=PBAT=3.6Ｖ, VIO=2.6V) Parameter Symbol Min. Typ. Max. ●Logic pin character VIO+ VIO× Input high level VIH1 0.3 0.7 NRST VIO× Input low level VIL1 -0.3 (CMOS input) 0.3 Logic input current IIC1 0 0.3 1 VBAT+ VBAT× Input high level VIH2 0.3 0.7 ADRS VBAT× Input low level VIL2 -0.3 (CMOS input) 0.3 Logic input current IIC2 -1 0 1 VIO+ VIO× Input high level VIH3 0.3 0.8 CLK, DATA VIO× Input low level VIL3 -0.3 (CMOS input) 0.2 Logic input IIC3 -1 0 1 current DATA Output low level VOL 0.4 (CMOS input) ●SWREG SWREG ●LDOs LDO1 LDO2 LDO3 Output voltage Output voltage Output voltage VOM1 VOM2 VOM3 1.746 2.716 2.716 1.800 2.800 2.800 1.854 2.884 2.884 Output Voltage VOSW 0.942 1.000 1.058 Unit V V μA V V μA V V μA V Pin Voltage: VIO Pin Voltage: VBAT Pin Voltage: VIO IOL=6mA V Initial value, Io=100mA Initial value Io=1mA Initial value Io=1mA Initial value Io=1mA V V V REV. B 4/4 ●Use-related Cautions (1) Absolute maximum ratings If applied voltage (VBAT1, VBAT2, PBAT, , VIO), operating temperature range (Topr), or other absolute maximum ratings are exceeded, there is a risk of damage. Since it is not possible to identify short, open, or other damage modes, if special modes in which absolute maximum ratings are exceeded are assumed, consider applying fuses or other physical safety measures. (2) Recommended operating range This is the range within which it is possible to obtain roughly the expected characteristics. For electrical characteristics, it is those that are guaranteed under the conditions for each parameter. Even when these are within the recommended operating range, voltage and temperature characteristics are indicated. (3) Reverse connection of power supply connector There is a risk of damaging the LSI by reverse connection of the power supply connector. For protection from reverse connection, take measures such as externally placing a diode between the power supply and the power supply pin of the LSI. (4) Power supply lines In the design of the board pattern, make power supply and GND line wiring low impedance. When doing so, although the digital power supply and analog power supply are the same potential, separate the digital power supply pattern and analog power supply pattern to deter digital noise from entering the analog power supply due to the common impedance of the wiring patterns. Similarly take pattern design into account for GND lines as well. Furthermore, for all power supply pins of the LSI, in conjunction with inserting capacitors between power supply and GND pins, when using electrolytic capacitors, determine constants upon adequately confirming that capacitance loss occurring at low temperatures is not a problem for various characteristics of the capacitors used. (5) GND voltage Make the potential of a GND pin such that it will be the lowest potential even if operating below that. In addition, confirm that there are no pins for which the potential becomes less than a GND by actually including transition phenomena. (6) Shorts between pins and misinstallation When installing in the set board, pay adequate attention to orientation and placement discrepancies of the LSI. If it is installed erroneously, there is a risk of LSI damage. There also is a risk of damage if it is shorted by a foreign substance getting between pins or between a pin and a power supply or GND. (7) Operation in strong magnetic fields Be careful when using the LSI in a strong magnetic field, since it may malfunction. (8) Inspection in set board When inspecting the LSI in the set board, since there is a risk of stress to the LSI when capacitors are connected to low impedance LSI pins, be sure to discharge for each process. Moreover, when getting it on and off of a jig in the inspection process, always connect it after turning off the power supply, perform the inspection, and remove it after turning off the power supply. Furthermore, as countermeasures against static electricity, use grounding in the assembly process and take appropriate care in transport and storage. (9) Input pins Parasitic elements inevitably are formed on an LSI structure due to potential relationships. Because parasitic elements operate, they give rise to interference with circuit operation and may be the cause of malfunctions as well as damage. Accordingly, take care not to apply a lower voltage than GND to an input pin or use the LSI in other ways such that parasitic elements operate. Moreover, do not apply a voltage to an input pin when the power supply voltage is not being applied to the LSI. Furthermore, when the power supply voltage is being applied, make each input pin a voltage less than the power supply voltage as well as within the guaranteed values of electrical characteristics. (10) Ground wiring pattern When there is a small signal GND and a large current GND, it is recommended that you separate the large current GND pattern and small signal GND pattern and provide single point grounding at the reference point of the set so that voltage variation due to resistance components of the pattern wiring and large currents do not cause the small signal GND voltage to change. Take care that the GND wiring pattern of externally attached components also does not change. (11) Externally attached capacitors When using ceramic capacitors for externally attached capacitors, determine constants upon taking into account a lowering of the rated capacitance due to DC bias and capacitance change due to factors such as temperature. (12) Thermal shutdown circuit (TSD) When the junction temperature reaches the defined value, the thermal shutdown circuit operates and turns the switch OFF. The thermal shutdown circuit, which is aimed at isolating the LSI from thermal runaway as much as possible, is not aimed at the protection or guarantee of the LSI. Therefore, do not continuously use the LSI with this circuit operating or use the LSI assuming its operation. (13) Thermal design Perform thermal design in which there are adequate margins by taking into account the permissible dissipation (Pd) in actual states of use. (14) Rush Current Extra care must be taken on power coupling, power, ground line impedance, and PCB design while excess amount of rush current might instantly flow through the power line when powering-up a LSI which is equipped with several power supplies, depending on on/off sequence, and ramp delays. REV. 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