BM81810MUV-ME2

Datasheet Power Supply IC Series for TFT-LCD Panels Automotive Panel Power Management IC BM81810MUV-M General Description Features ◼AEC-Q100 Qualified(Note 1) ◼Alternative Synchronous Buck DC/DC converter or LDO for VDD output ◼Synchronous Boost DC/DC converter for AVDD output with integrated load switch. ◼VCOM amplifier with 7bit calibrator ◼Positive charge pump (Integrated diode, x2/x3) for VGH output ◼Negative charge pump for VGL output ◼VGH and VCOM temperature compensation ◼Gate Pulse Modulation(GPM) ◼I2C Interface Output Voltage Setting Control Function (Integrated EEPROM) ◼Switching frequency switching function (525kHz, 1.05MHz, 2.1MHz) ◼Protection circuits ➢ Under-Voltage Lockout ➢ Thermal Shut Down ➢ Over-Current Protection ➢ Over-Voltage Protection ➢ Under Voltage Protection (Timer Latch type) ◼Input tolerant (SCL, SDA, EN, GSIN) (Note1: Grade 2) BM81810MUV-M is a power management IC for TFT-LCD panels which are used in car navigation, in-vehicle center panel, and instrument cluster. This IC incorporates VCOM amplifier, Gate Pulse Modulation (GPM) in addition to the power supply for panel driver (SOURCE, GATE, and LOGIC power supplies). Moreover, this IC has a built-in EEPROM for sequence and output voltage setting retention. Key Specifications ◼Input voltage range: 2.6V to 5.5V ◼AVDD Output voltage range: 5.0V to 17.0V ◼VGH Output voltage range: 8.0V to 35.0V ◼VGL Output voltage range: -4.0V to -14.0V ◼VDD Output voltage range: 0.9V to 3.4V ◼VCOM Output current: 200 mA (Typ) ◼Switching Frequency: 525KHz, 1.05MHz, 2.1MHz ◼Operating temperature range: -40°C to +105°C ◼Standby current: 2.0 μA (Typ) Special Characteristics ◼AVDD output voltage accuracy: ◼Oscillator Frequency: ±2% ±10% Package Applications W(Typ) x D(Typ) x H(Max) VQFN32SV5050 TFT-LCD Panels which are used in car navigation, in-vehicle center panel, and instrument cluster. 5.0mm x 5.0mm x 1.0mm Typical Application Circuit (TOP VIEW) R_NTC2 R_NTC3 WPN R_NTC1 R_FLT VIN R_RE GSOUT VIN Θ R_PG VGH FAULT C_VCP RE 17 18 19 20 21 22 23 24 RST SWB L_SWB C_VDD EN VCP C_DRP1 D_VGL CPP1 DRP DRN C_DRN VGL VCOM 9 SCL 2 3 VREG 1 4 5 6 7 C_VCOM 8 C_VGL AVDD SW R_RST VLSO SDA 25 26 27 28 29 30 31 32 GSIN 10 11 12 13 14 15 16 VIN C_VGH CPP2 NTC PG / LDSW VDD C_DRP2 AVDD C_VINB C_REG (D_SW) L_SW VIN C_VIN C_AVD C_LSO Figure 1. 〇Product structure : Silicon integrated circuit .www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 14 • 001 Application Circuit 〇This product has no designed protection against radioactive rays. 1/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M Contents General Description ........................................................................................................................................................................ 1 Key Specifications .......................................................................................................................................................................... 1 Special Characteristics ................................................................................................................................................................... 1 Applications .................................................................................................................................................................................... 1 Features.......................................................................................................................................................................................... 1 Package .......................................................................................................................................................................................... 1 Typical Application Circuit (TOP VIEW) .......................................................................................................................................... 1 Pin Configuration (TOP VIEW)........................................................................................................................................................ 3 Pin Descriptions .............................................................................................................................................................................. 3 Absolute Maximum Ratings ............................................................................................................................................................ 4 Thermal Resistance (Note 1)............................................................................................................................................................... 5 Recommended Operating Ratings (Ta=-40 °C to +105 °C) ............................................................................................................ 5 Electrical Characteristics (Unless otherwise specified, Ta=25°C, VIN, VINB=3.3V) ....................................................................... 6 Typical Performance Curves ......................................................................................................................................................... 10 Application Example 1 (when operated by EN control) ................................................................................................................. 25 Timing Chart1 ............................................................................................................................................................................... 27 Application Example 2 (when operated with EN= VCC condition) ................................................................................................ 29 Timing Chart2 ............................................................................................................................................................................... 29 Application Example 3 (using LDSW mode) ................................................................................................................................. 31 Timing Chart3 ............................................................................................................................................................................... 33 Serial communication ................................................................................................................................................................... 35 WPN Timing .................................................................................................................................................................................. 36 I2C Timing Diagram ...................................................................................................................................................................... 37 Automatic EEPROM Read Function at Start-up ........................................................................................................................... 38 EEPROM Parameter Setting ........................................................................................................................................................ 39 Register Map ................................................................................................................................................................................ 40 Command Table ............................................................................................................................................................................ 41 Check Sum ................................................................................................................................................................................... 45 Soft Start Time .............................................................................................................................................................................. 46 Block Diagram .............................................................................................................................................................................. 47 AVDD Block Function.................................................................................................................................................................... 48 VGH Block Function ..................................................................................................................................................................... 51 VGL Block Function ...................................................................................................................................................................... 54 VCOM Block Function .................................................................................................................................................................. 55 VDD Block Function ...................................................................................................................................................................... 56 GPM Block Function ..................................................................................................................................................................... 58 RESET Block Function ................................................................................................................................................................. 59 PG/LDSW Block Function ............................................................................................................................................................. 60 NTC Block Function ...................................................................................................................................................................... 61 EN Block Function ........................................................................................................................................................................ 61 VGH and VCOM temperature compensation ................................................................................................................................ 62 FAULT Block Function .................................................................................................................................................................. 63 Fail Register Function ................................................................................................................................................................... 63 Protection function explanation of POWER MANAGEMENT block .............................................................................................. 64 Double Register ............................................................................................................................................................................ 65 Data Refresh................................................................................................................................................................................. 65 PCB Layout Guide ........................................................................................................................................................................ 66 EMC Layout Guide ....................................................................................................................................................................... 67 I/O Equivalence Circuit ................................................................................................................................................................. 68 Operation Notes............................................................................................................................................................................ 71 Ordering Information ..................................................................................................................................................................... 73 Marking Diagram .......................................................................................................................................................................... 73 Physical Dimension, Tape and Reel Information ........................................................................................................................... 74 Revision History ............................................................................................................................................................................ 75 .www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 2/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M Pin Configuration (TOP VIEW) CPP2 VGH GSOUT RE WPN NTC FAULT PG/LDSW (TOP VIEW) PGNDB EN EXP-PAD 9 SWB 2 3 4 5 VREG VIN VLSO PGND VINB 1 6 7 VCP CPP1 DRP DRN VGL CGND VCOM NEG 8 AVDD VDD PAVDD RST SW SCL 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SDA 25 26 27 28 29 30 31 32 GSIN Figure 2. Pin Configuration Pin Descriptions Pin No. Pin Name Pin No Pin Name Function 1 VINB Buck DC/DC power supply input 17 CPP2 Built-in Positive charge pump switching Di output 3 2 VREG Inner power supply output 18 VGH Positive charge pump feedback & Power Input of Gate Pulse Modulation 3 VIN Boost DC/DC load switch input 19 GSOUT 4 VLSO Boost DC/DC load switch output 20 RE 5 PGND Boost DC/DC ground 21 WPN Active Low of EEPROM Writing protection. 6 SW Boost DC/DC switching pin 22 NTC Slope setting pin for temperature compensation of the VON and VCOM 7 PAVDD Boost DC/DC output & output feedback Power Input of DRN 23 FAULT FAULT signal output 8 AVDD Power Input of VCOM , DRP 24 PG/ LDSW Power Good signal output or Load SW of PAVDD. 9 NEG Negative Input of VCOM Amplifier 25 GSIN Input of Gate Pulse Modulation 10 VCOM VCOM amplifier output 26 SDA Serial clock data input (I2C) 11 CGND Charge pump ground 27 SCL Serial clock input (I2C) 12 VGL Negative charge pump feedback 28 RST Reset output 13 DRN Negative charge pump driver pin 29 VDD Buck DC/DC or LDO output feedback input 14 DRP Positive charge pump driver pin 30 SWB Buck DC/DC switching pin or LDO output pin 15 CPP1 Built-in Positive charge pump switching Di output 1 31 PGNDB 16 VCP Built-in Positive charge pump switching Di output 2 32 EN - EXP -PAD Function .www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 3/75 Output of Gate Pulse Modulation Slope Setting Pin for Gate Pulse Modulation Buck DC/DC ground Enable input Connect to Ground. TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M Absolute Maximum Ratings Parameter Limits Symbol Unit Min Typ Max VIN, VINB -0.3 - +6.5 V SWB -0.3 - VINB+0.3 V VDD -0.3 - +6.5 V AVDD, PAVDD, SW -0.3 - +19 V VLSO -0.3 - +6.5 V VCOM -0.3 - AVDD+0.3 V DRP -0.3 - AVDD+0.3 V DRN -0.3 - PAVDD+0.3 V CPP1,CPP2,VCP -0.3 - +36 V VGH,GSOUT,RE -0.3 - +36 V VGL -15 - +0.3 V VREG -0.3 - VIN+0.3 V FAULT -0.3 - +6.5 V PG/LDSW -0.3 +19 V RST, NTC -0.3 - VIN+0.3 V NEG -0.3 - AVDD+0.3 V SCL, SDA, EN, GSIN -0.3 - +6.5 V WPN -0.3 - VIN+0.3 V Maximum Junction temperature Tjmax (Note 1) - - +150 °C Storage Temperature Range Tstg -55 - +150 °C Power Supply Voltage Output Pin Input Pin Functional Pin Voltage (Note 1) Junction temperature at storage time. Caution : Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated over the absolute maximum ratings. .www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 4/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M Thermal Resistance (Note 1) Symbol Parameter Thermal Resistance (Typ) 1s(Note 3) 2s2p(Note 4) Unit VQFN32SV5050 Junction to Ambient θJA 138.9 39.1 °C/W Junction to Top Characterization Parameter(Note 2) ΨJT 11 5 °C/W (Note 1)Based on JESD51-2A(Still-Air). (Note 2)The thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside surface of the component package. (Note 3)Using a PCB board based on JESD51-3. Layer Number of Material Board Size Measurement Board Single FR-4 114.3mm x 76.2mm x 1.57mm Top Copper Pattern Thickness Footprints and Traces 70µm (Note 4)Using a PCB board based on JESD51-5, 7. Layer Number of Material Board Size Measurement Board 4 Layers FR-4 Top Thermal Via(Note 5) Pitch Diameter 114.3mm x 76.2mm x 1.6mmt 1.20mm 2 Internal Layers Φ0.30mm Bottom Copper Pattern Thickness Copper Pattern Thickness Copper Pattern Thickness Footprints and Traces 70µm 74.2mm x 74.2mm 35µm 74.2mm x 74.2mm 70µm (Note 5) This thermal via connects with the copper pattern of all layers. Recommended Operating Ratings (Ta=-40 °C to +105 °C) Parameter Symbol Min Typ Max Unit VIN,VINB 2.6 - 5.5 V ISWB - - 1.0 A ISW - - 2.0 A EN,GSIN,WPN -0.1 - +5.5 V 2 Line Serial Pin Voltage SDA, SCL -0.1 - +5.5 V 2 Line Serial Frequency FCLK - - 400 kHz Operating Ambient Temperature TA -40 - +105 °C Operating Junction Temperature TJ -40 - +125 °C Power Supply Voltage SWB Current SW Current Functional Pin Voltage .www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 5/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M Electrical Characteristics (Unless otherwise specified, Ta=25°C, VIN, VINB=3.3V) 1. VDD regulator block (Alternative Buck converter or LDO) Symbol Parameter Limits Unit Condition Min Typ Max VDD 0.9 - 3.4 V 50 mV step Output Voltage Accuracy 1 VDD_R1 2.462 2.5 2.538 V VDD=2.5 V setting Output Voltage Accuracy 2 VDD_R2 -2.0 - +2.0 % VDD=2.5 V to 3.4 V setting (Ta=-40 to +105 °C) Output Voltage Accuracy 3 VDD_R3 -3.0 - +3.0 % VDD=0.9 V to 2.45 V setting (Ta=-40 to +105 °C) Soft Start time VDD_SS 0.85 1 1.15 msec Output Voltage Range Under-Voltage Protection voltage VDD=1.2 V setting VDD_UVP VDD×0.7 VDD×0.8 VDD×0.9 V SWB H Side ON Resistance RONH_SWB - 300 480 mΩ DCDC mode SWB L Side ON Resistance RONL_SWB - 300 480 mΩ DCDC mode SWB H Side ON Resistance RON_SWB - 1.0 2.0 Ω LDO mode SWB H Side Leak Current IL_ SWBH - 0 20 µA (Ta=-40 to +105 °C) SWB L Side Leak Current IL_ SWBL - 0 20 µA (Ta=-40 to +105 °C) Current Limit ILMT_SWB1 1.0 1.7 2.7 A Buck DCDC mode Current Limit ILMT_SWB2 0.3 0.5 0.7 A Maximum Duty DMAX_SWB 87 95 - % DISR_VDD - 25 50 Ω Discharge Resistance LDO mode Freq=1.05 MHz (Freq=0.525 MHz:98%typ) (Freq=2.10 MHz:87%typ) 2. Boost DC/DC converter block (AVDD) Parameter Symbol Limits Unit Condition Min Typ Max AVDD 5.0 - 17.0 V 0.1 V step Output Voltage Accuracy1 AVDD_R1 10.342 10.5 10.66 V Output Voltage Accuracy2 AVDD_R2 10.29 10.5 10.71 V AVDD=10.5 V setting AVDD=10.5 V setting (Ta=-40 to +105 °C) Load Switch Soft Start time LS_SS 1.7 2 2.3 msec AVDD_SS 4.25 5 5.75 msec Under-Voltage Protection voltage AVDD_UVP AVDD×0.7 AVDD×0.8 AVDD×0.9 V Over-Voltage Protection voltage AVDD_OVP AVDD×1.03 AVDDx1.1 AVDD×1.2 V SW H Side On Resistance RON_SW - 250 480 mΩ SW L Side On Resistance RON_SW - 200 350 mΩ SW H Side Leak Current IL_SWH - 0 20 µA (Ta=-40 to +105 °C) Output Voltage Range Soft Start Time SW L Side Leak Current AVDD=10.5 V setting 5 ms setting IL_SWL - 0 20 µA (Ta=-40 to +105 °C) Current Limit ILMT_SW 2.0 4.0 6.0 A AVDD OCP=2 A setting Current Limit ILMT_SW 1.0 2.0 2.5 A AVDD OCP=1 A setting Load Switch ON Resistance RON_LS - 200 350 mΩ DMAX_SW 83 90 - % DISR_AVDD - 25 50 Ω Maximum Duty Discharge Resistance .www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 6/75 Freq=1.05 MHz (Freq=0.525 MHz:95%typ) (Freq=2.10 MHz:80%typ) TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M Electrical Characteristics (Unless otherwise specified, Ta=25°C, VIN, VINB=3.3V) – continued 3. VCOM amplifier block (VCOM) Parameter Output Voltage Range1 Output Voltage Range2 Output Voltage Range3 Output Voltage Range4 Limits Symbol Min 0.5x VCOM_HOT AVDD - 4.0 VCOM VCOM_COLD HOT - 0.63 VCOM VCOM_CAL HOT - 0.63 VCOM_RNG 0.2xAVDD Calibration Resolution Integral Non-Linearity Error (INL) Differential Non-Linearity Error (DNL) Output Current Ability (Source) Output Current Ability (Sink) Load Stability Slew Rate Typ 0.5x AVDD - Max 0.5x AVDD + 4.0 VCOM HOT - VCOM HOT +0.63V 0.7x AVDD VCOM HOT Unit Condition V 40 mV step V 10 mV step V 10 mV step V RES_CAL - 7 - Bit INL_CAL -1 - +1 LSB DNLCAL -1 - +1 LSB ISOURCE - 200 - mA ISINK - 200 - mA VLOAD - 10 70 mV SR 30 60 80 V/µsec Io=-15 mA to +15 mA 4. Positive charge pump block (VGH) Parameter Symbol Limits Unit Typ Max V 0.2 V step V 0.2 V step *Max = 35 V Output Voltage Range 1 VGH_HOT 8.0 - Output Voltage Range 2 VGH_COLD VGH HOT - Output Voltage Accuracy 1 VGH_R1 17.46 18 35 VGH HOT +15V 18.54 Output Voltage Accuracy 2 VGH_R2 17.1 18 18.9 V Soft Start time VGH_SS 4.25 5 5.75 msec VGH_UVP VGH×0.7 VGH×0.8 VGH×0.9 V DRP H Side On Resistance RON_DRPH - 10 20 Ω DRP L Side On Resistance RON_DRPL - 10 20 Ω AVDD-CPP1 On Resistance RON_CPP1 - 10 20 Ω CPP1-VCP On Resistance RON_CPP2 - 10 20 Ω VCP-CPP2 On Resistance RON_CPP3 - 10 20 Ω CPP2-VGH On Resistance RON_CPP4 - 10 20 Ω Discharge Resistance DISR_VGH - 150 300 Ω Under-Voltage Protection voltage Condition Min V VGH=18 V setting VGH=18 V setting (Ta=-40 to +105 °C) VGH=18 V setting 5. Negative charge pump block (VGL) Parameter Symbol Limits Unit Condition Min Typ Max VGL -14.0 - -4.0 V 0.1 V step Output Voltage Accuracy 1 VGL_R1 -6.18 -6 -5.82 V Output Voltage Accuracy 2 VGL_R2 -6.3 -6 -5.7 V VGL=-6.0 V setting VGL=-6.0 V setting (Ta=-40 to +105 °C) Soft Start time VGL_SS 4.25 5 5.75 msec Output Voltage Range VGL_UVP VGL×0.7 VGL×0.8 VGL×0.9 V DRN H Side On Resistance RON_DRNH - 10 20 Ω DRN L Side On Resistance RON_DRNN - 10 20 Ω DISR_VGL - 250 500 Ω Under-Voltage Protection voltage Discharge Resistance .www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 7/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M Electrical Characteristics (Unless otherwise specified, Ta=25°C, VIN, VINB=3.3V) – continued 6. Temperature compensation block (NTC) Symbol Parameter Limits Min Typ Max Unit NTC HOT Voltage VNTC_H 0.475 0.5 0.525 V NTC COLD Voltage VNTC_H 1.1875 1.25 1.3125 V INTC 36 40 44 µA RES_NTC - 4 - Bit NTC Current NTC Resolution Condition 7. Gate Pulse Modulation block (GPM) Symbol Parameter Limits Unit Condition Min Typ Max RON_GPMH - 15 30 Ω RON_GPML - 30 - Ω GPM Propagation Delay1 T_GPM1 - 0.1 0.3 µsec No Capacitive Load 0.1 µS setting GPM Propagation Delay2 T_GPM2 - 0.5 1.0 µsec No Capacitive Load 0.5 µS setting GPM Propagation Delay3 T_GPM3 - 1.0 1.75 µsec No Capacitive Load 1.0 µS setting GPM Propagation Delay4 T_GPM4 - 1.5 2.5 µsec No Capacitive Load 1.5 µS setting RGSIN 70 100 130 kΩ GSIN Input High Voltage VGSINH 1.5 - - V GSIN Input Low Voltage VGSINL - - 0.6 V GPM High Switch On Resistance GPM Low Switch On Resistance GSIN Pull Down Resistance .www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 8/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M Electrical Characteristics (Unless otherwise specified, Ta=25°C, VIN, VINB=3.3V) – continued 8. Overall (Entire device) Symbol Parameter Limits Unit Condition Min Typ Max VREG 2.15 2.3 2.45 V ΔV - 20 100 mV Oscillating Frequency 1 FOSC1 475 525 575 KHz Oscillating Frequency 2 FOSC2 950 1050 1150 KHz Oscillating Frequency 3 FOSC3 1900 2100 2300 KHz UVLO release voltage VUVLO1 2.5 2.55 2.6 V UVLO detection voltage VUVLO2 2.0 2.1 2.2 V VHYS_UVL - 0.45 - V VRST 0.6 * 3.3 V 0.1 V step VRST_R1 1.9 2.0 2.1 V VRST=2.0 V setting VHYS_RST - 0.1 - V T_Delay2 0 - 40 msec IL - 0 10 µA RON_O - 1 2 kΩ VSDA - - 0.4 V VIH 1.5 - - V Inside Regulator Voltage VREG Output Voltage Load Stability IVREG=5 mA Oscillator Block Under Voltage Lock Out (UVLO) Circuit Hysteresis Reset Circuit Block Reset Voltage Range Reset Voltage Accuracy Hysteresis Reset Delay time Range FAULT/ PG / RST Signal Output Block Output Off Leak Current Output On Resistance Control Signal Block1 SDA, SCL, WPN Minimum Output Voltage H Level Input Voltage L Level Input Voltage ISDA=3 mA VIL - - 0.6 V RWPN 70 100 130 kΩ REN_L 280 400 520 kΩ EN=Low REN_H 420 600 780 kΩ EN=High H Level Input Voltage VENH 1.5 - - V L Level Input Voltage VENL - - 0.6 V Standby Current1 ISTB1 - 2.0 5.0 µA EN=GND Standby Current2 ISTB2 - - 20 µA EN=GND (Ta=-40 to +105 °C) Consumption Current ICC1 - 2.0 5.0 mA EN=VIN, No switching Unit Condition WPN Pull Down Resistance Control Signal Block2 EN Pull-Down Resistance Value Overall 9. EEPROM Parameter Symbol Limits Min Typ Max Rewritable cycle Cyc 100 - - Times Programmable time Twr - - 50 msec Data hold years DHY 20 - - Years .www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 9/75 TJ VGH, changing the application contracture to following make is possible. In this case please set Register08h (Function Select) of the EEPROM to "1". R_NTC2 R_NTC3 WPN R_NTC1 VIN R_RE R_FLT GSOUT Θ VGH FAULT C_VCP RE 17 18 19 20 21 22 23 24 C_VDD EN CPP1 C_DRP1 D_VGL DRP DRN C_DRN VGL VCOM 9 SWB L_SWB 1 3 VREG 2 4 5 6 SW SCL RST VLSO SDA R_RST VCP 25 26 27 28 29 30 31 32 GSIN 10 11 12 13 14 15 16 VIN C_VGH CPP2 NTC PG / LDSW VDD C_DRP2 7 AVDD PAVDD C_VINB C_VGL C_VCOM 8 AVDD M_LDSW C_REG VIN L_SW C_VIN R_LDSW C_LSO C_GD C_PAV C_LDSW C_AVD R_LSGATE LDSW (D_SW) Figure 67. Application Circuit (Function Select = LDSW) . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 31/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M Application Example 3 (using LDSW mode) - continued Application circuit components list (Unless otherwise specified VIN=3.3V, VDD=2.5V, AVDD=10.5V, VGH=18V, VGL=-6.0V, VCOM=5.25V and Ta=25°C) Value Parts name Min (Note 1) Typ Max Unit Company Parts Number Comment C_VIN 10 10 x 2 - μF MURATA GRT21BC81A106KE01 C_VINB 4.7 10 - μF MURATA GRT21BC81A106KE01 C_REG 0.047 0.1 0.47 μF MURATA GRT188R71H104KE13 No need @ VDD LDO mode C_LSO 10 10 x 2 - μF MURATA GRT21BC81A106KE01 C_PAVD 5.0 10 x 2 10 x 5 μF MURATA GRT31CC81E106KE01 See p.49 in detail. C_AVD 2.2 4.7 10 μF MURATA GRT31CC81E475KE01 See p.49 in detail. L_SW - 4.7 - μH TDK LTF5022T-4R7N2R0-H See p.49 in detail. D_SW - - - - ROHM (RB060M-30DD) Please insert D_SW when improving the efficiency is necessary. M_LDSW - - - - ROHM RTR030P02FHA R_LDSW - 100 - kΩ ROHM MCR03 C_LDSW - 0.47 - μF MURATA GRT21BR71H474KE01 C_GD - 33 - nF MURATA GRT155R71H333KE01 R_LSGATE - 100 - kΩ ROHM MCR03 C_VDD 10 10 x 2 47 μF MURATA GRT21BC81A106KE01 L_SWB - 4.7 - μH TDK LTF5022T-4R7N2R0-H C_VCOM - - - μF MURATA - C_VGL 0.47 1.0 4.7 μF MURATA GRT21BC81E105KE13 C_DRN - 0.1 - μF MURATA GRT188R71H104KE13 - ROHM RB558WFH C_VGH 0.47 2.2 4.7 μF MURATA GRT21BC8YA225KE13 C_CPP1 - 0.1 - μF MURATA GRT188R71H104KE13 C_VCP - 1.0 - μF MURATA GRT188C81E105KE13 C_CPP2 - 0.1 - μF MURATA GRT188R71H104KE13 D_VGL - R_RE 0.2 2.0 - kΩ ROHM MCR03 R_NTC1 - 4.7 - kΩ ROHM MCR03 R_NTC2 - 33 - kΩ ROHM MCR03 R_NTC3 - 10 - kΩ MURATA NCU18XH103F6SRB R_FLT 47 100 200 kΩ ROHM MCR03 R_RST 47 100 200 kΩ ROHM MCR03 (Note 1)Please set in consideration of temperature properties and DC bias properties not to become less than the minimum. Please consider it based on enough evaluations with the actual model. . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 32/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M Timing Chart3 Start-up Sequence (when operated with LDSW function) Vcc UVLO release Vcc=2.55V (Inner logic, reset EEPROM) VIN, VINB Enable=L⇒H EN VREG EEROM EEPROM Auto Read Discharge 0～5ms Discharge 1ms (when VDD=1.2V) VDD VDD 90% Soft Start time 5ms (when 10.5V is set) delay1 (0～300ms) AVDD load SW ON AVDD PAVDD VIN level VGL VGL Soft Start time 5ms (when -6V is set) VCOM ⇒ Start up by following to AVDD voltage VCOM Soft Start time 5ms (when 18V is set) VGH AVDD level delay3 (0～40ms) EEPROM Register Data write-able zone GSOUT delay4 (0～40ms) RST delay2 (0～40ms) Reset monitor is setting VDD. LDSW FAULT Figure 68. Start-Up Sequence Diagram (when operated with LDSW Function) . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 33/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M Timing Chart3 - continued OFF Sequence (when operated with LDSW function) Vcc UVLO detect　Vcc=2.1V (Inner logic, reset EEPROM) VIN, VINB VREG EEROM Discharge Enable=H⇒L EN delay5 (0～10ms) VDD Discharge VDD AVDD Discharge AVDD VGL VGL Hi-Z VGL Discharge VCOM Discharge VCOM VGH Hi-Z VGH Discharge VGH EEPROM Register Data write-able zone GSOUT RST LDSW FAULT Figure 69. OFF Sequence Diagram (when operated with LDSW Function) . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 34/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M Serial communication This IC has two device-address-differential EEPROM installed and data is send or received to/from EEPROM using 2-line serial interface (SCL, SDA). Communication format for data sending or receiving to/from each EEPROM is shown below. EEPROM I2C Format for DVR (VCOM calibrator) Device address Write operation Start Read operation Start R/W ACK 0 0 R/W ACK 1 0 DATA ACK STOP 1 0 1 0 0 1 1 1 1 1 1 Device address D6 D5 D4 D3 D6 D5 D4 D3 D2 D1 D0 P D1 D0 X DATA 0 ACK STOP 0 1 1 D2 1 When Device Address = 1001111(R/W) is selected, Data is Read or Write EEPROM for DVR(VCOM calibrator). During Write mode •When P=1, the sending data is written only to Register. •When WPN=Low and P=0, the sending data is written only to Register. •When WPN=High and P=0, the sending data is written both to Register and EEPROM. During Read mode The last bit of received data is “Don’t care”. “D6” is ± select bit: 0 = “+”, 1=”-” from VCOM(HOT) value. [D5:D0] are voltage band from VCOM(HOT). The voltage band is calculated; 10mV x [D5:D0], For example, [D6:D0,P] = 82h(D6=1, [D5:D0]=1’d, P=0) ••• VCOM = VCOM(HOT) – 1 x 10mV; [D6:D0,P] = 7Eh(D6=0, [D5:D0]=63’d, P=0) ••• VCOM = VCOM(HOT) + 63 x 10mV; Sequence of DVR side EEPROM during Read/Write mode is shown in below chart. Figure 70 . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 Figure 71 35/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M Serial communication - continued EEPROM I2C Format for Power Management IC (PMIC) Write operation Read operation Start Start 1 1 Device address 0 0 0 0 Device address 0 0 0 0 0 0 R/W ACK 0 0 0 R/W ACK 0 0 0 Register Address 00h ～ 0Dh, 10h, 11h Register Address 00h ～ 0Dh, 10h, 11h ACK ACK Repeated Start 0 ACK N-bytes Data 0 1 0 Device Address 0 0 0 0 0 ACK 0 1 0 N-bytes Data ACK 1 Stop Stop Device Address of BM81810MUV-M is 1000 000x. Multi write is possible until Register 00h to 0Dh. EN WPN Start-up( 0Ch[7] ) PMIC ( 00h to 0Dh) Output Function 1 Low Low - - Shutdown 2 High Low - Register Active 3 High High 0* Register & EEPROM Shutdown 4 High High 1 Register & EEPROM Active * In the mass production shipment process, please write Start-up ( 0Ch[7] ) to "1" in EEPROM. The following are the settings if you want to send the Data by I2C. Device Address? 1000_0000 Receive register address Read Yes No Write Restart? Device Address 1000_0001 Input data to register Output register data Low WPN High Write data to EEPROM End process Figure 72 WPN Timing WPN is normally fixed as Low. In case of writing to EEPROM, WPN is set to High, and the timing will be as below. Because the maximum of the auto-read time from EEPROM is 5ms, please between EN signal and I2C input than 5ms. Also, because the maximum of writing time to EEPROM is 50ms, please between I2C STOP signal and EN falling signal than 50ms. VIN EEPROM Data Auto Read > 5msec EEPROM　Write Time > 50msec EN WPN SCL SDA tSU;WPN > 0usec S T A R T Device Address A C K Register Address A C K DATA A C K DATA A C K ・・・・・ DATA A C K S T O P tHD;WPN > 10usec Figure 73 . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 36/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M I2C Timing Diagram tR tHIGH tF 70% SCL 30% tLOW tHD: STA tSU; DAT tPD tHD; DAT 70% SDA (IN) 30% tBUF tDH 70% SDA ( OUT) 30% 70% SCL tHD; STA tSU; STA tSU; STO 70% SDA 30% tl S S： START Bit P： STOP Bit P Figure 74. I2C Timing Diagram Timing standard values Parameter SCL frequency SCL high time SCL low time Rise Time Fall Time Start condition hold time Start condition setup time SDA hold time SDA setup time Acknowledge delay time Acknowledge hold time Stop condition setup time Bus release time Noise spike width Symbol fSCL tHIGH tLOW tR tF tHD;STA tSU;STA tHD;DAT tSU;DAT tPD tDH tSU;STO tBUF Tl . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 Min 4.0 4.7 4.0 4.7 0 200 4.0 4.7 - NORMAL MODE Typ Max Min FAST MODE Typ Max 100 1.0 0.3 0.9 - 0.6 1.2 0.6 0.6 0 100 0.6 1.2 - 0.1 0.1 400 0.3 0.3 0.9 - 0.1 0.1 37/75 Unit kHz μs μs μs μs μs μs ns ns μs μs μs μs μs TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M Automatic EEPROM Read Function at Start-up Upon BM81810MUV-M start-up, a reset signal is generated and each register is initialized. After VREG activation is finished, data which is stored in the EEPROM is copied to the registers. The automatic EEPROM read function at start-up is further explained by the flow chart below. VREG ACTIVE EEPROM READ TRANSFER DATA REGISTER NO CHECK SUM NG OK 3times NG? YES START OPERATION SHUT DOWN Figure 75. Automatic EEPROM Read Function at Start-up . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 38/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M EEPROM Parameter Setting ■EEPRO M / Main Re giste r Map ( de vic e addre ss : 1 0 0 0 0 0 0 x ) Device Address: 1000000x (PMIC) Register Address Bits 00h 8 AVDD Output voltage 0.1V [5.0V to 17.0V] AVDD Output voltage setting 01h 8 VGH(HOT) Output voltage 0.2V [8.0V to 35.0V] VGH(HOT) Output voltage setting 02h 8 03h Function ΔVGH(COLD) Voltage [6:0] Resolution 0.2V [VGH(HOT) + 15V] VGH NTC Enalbe [7] 0:Disable, 1:Enable 8 VGL Output voltage 0.1V [-14.0V to -4.0V] 04h 8 VCOM(HOT) Output voltage 05h 8 06h 8 ΔVCOM(COLD) Voltage [6:0] 08h 8 8 8 0.05V [0.9V to 3.4V] VDD Output voltage setting VDD mode select [6] 0 : DC/DC, 1 : LDO Select VDD operation mode DC/DC or LDO Reset Voltage [4:0] Reset monitor select [5] 0Bh 0Ch 8 8 See P.56 page. 0.1V [0.6V to 3.3V] 0:VDD, 1:VIN GPM input delay [7:6] 00: 0.1usec, 01: 0.5usec, 10: 1.0usec, 11: 1.5usec Discharge time [2:0] Delay1 time [6:3] 1msec [0 to 5msec] [0 to 300msec] 0: PG, 1: LDSW select VDD Phase Reset voltage setting Select monitor pin of reset function GPM input propagation delay time setting Pre-discharge time setting Load sw itch of AVDD start-up delay time setting 24pin function select Delay2 time [2:0] DoubleReg [3] 5msec [0 to 30msec, 40msec] 0: Disable, 1: Enable Reset start delay time setting Double Register Function Delay3 time [6:4] 5msec [0 to 30msec, 40msec] VGL or VGH start-up delay time setting Delay4 time [2:0] 8 10mV [VCOM(HOT) - 0.63V] 0:Disable, 1:Enable DataRef [7] 0Ah VCOM(HOT) Output voltage setting VDD Output voltage [5:0] Function Select [7] 09h 40mV [0.5xAVDD ±4.0V] VGL Output voltage setting VCOM NTC Enalbe [7] VDD Phase [7] 07h Comments AR_Time [3] Delay5 time [6:4] VGH Discharge enable [7] 0: Disable, 1: Enable 5msec [0 to 30msec, 40msec] 0: 0.5sec, 1: 1.0sec 2msec [0 to 10msec] 0: Enable, 1: Disable AVDD Coil[1:0] See p.49 page. AVDD SW Slew Rate [3:2] See p.48 page. AVDD SS time [5:4] 5msec [5msec to 20msec] Data Refresh Function GPM start delay time setting Data Refresh Time VDD stop delay time setting VGH Discharge function enable select AVDD Coil indactance 4step slew rate setting (11:fast → 00:slow) AVDD softstart time setting AVDD OCP Select [6] AVDD COMP [7] 0: 2A, 1: 1A See p.49 page. AVDD Frequecy [1:0] 00:2.1MHz, 01:1.05MHz, 10:525KHz, 11:525KHz Seletc AVDD switching frequency VDD Frequecy [3:2] 00:2.1MHz, 01:1.05MHz, 10:525KHz, 11:525KHz Select VDD switching frequency Select VGH and VGL switching frequency. Choose only "00". Select VGH charge pump mode VGH / VGL Frequecy [5:4] VGH mode select [6] start-up bit [7] AVDD Freqency ( 00: x1, 01: --, 10: --, 11: -- ) 0: x3 mode, 1: x2 or x4 mode AVDD OCP min value select AVDD phase compensation setting 0:Disable, 1:Enable Device Address: 1001111x (VCOM) Register Address Bits - 7 Function VCOM Calibrator Resolution +/- 0.01V [ VCOM +/- 0.63V] Comments VCOM Calibrator When Start-up bit(REG0Ch[7]) is ”1”, below Register cannot be modified. VGH NTC Enable VCOM NTC Enable VDD mode select Function select VGH mode select REG02h[7] REG05h[7] REG06h[6] REG08h[7] REG0Ch[6] To change those Register setting, start-up bit(REG0Ch[7]) should be in ”0”. After changing the register value, set the Start-up bit(REG0Ch[7]) to “1” again to start up with the changed setting. . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 39/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M Register Map Device Address : 1000000x (PMIC) Register Address D7 D6 D5 D4 00h 01h 02h D3 D2 D1 D0 Default AVDD Output Voltage 68h VGH HOT Output Voltage 59h VGH NTC Enable ⊿VGH COLD Voltage 83h 03h VGL Output Voltage 3Bh 04h VCOM HOT Output Voltage 80h 05h 06h 07h 08h VCOM NTC Enable VDD VDD Phase Select MODE GPM Input Delay Function Select ⊿VCOM COLD Votlage 99h VDD Output Voltage Reset Monitor Select 20h Reset Voltage Delay1 time 04h Discharge time 09h 09h Data Refresh Delay3 time DoubleReg Delay2 time 13h 0Ah VGH Discharge Enable Delayt5 time AR_Time Delay4 time 87h 0Bh AVDD COMP Start-up Bit 0Ch AVDD OCP Select VGH mode select AVDD SS Time VGH/VGL Frequency AVDD SW Slew Rate VDD Frequency 0Dh 10h AVDD Coil Select AVDD Frequency 3Ch 05h 60h Check Sum AVDD UVP VDD UVP VGH UVP VGL UVP Double Register Error AVDD OCP TSD Check sum Error 00h Device Address : 1001111x (VCOM) Register Address D6 D5 - . www.rohm.com © 2016 ROHM Co., Ltd. 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TSZ22111 • 15 • 001 D4 D3 D2 VCOM Calibration Voltage 40/75 D1 D0 P Default P 80h TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M Register Map - continued Command Table Regitser Address 00h DATA (HEX) 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 60h 61h 62h 63h 64h 65h 66h 67h 68h 69h 6Ah 6Bh 6Ch 6Dh 6Eh 6Fh 70h 71h 72h 73h 74h 75h 76h 77h 78h 79h 7Ah 7Bh 7Ch 7Dh 7Eh 7Fh AVDD Output Voltage [7:0] 02h 01h VGH HOT VGH ⊿VGH COLD Output NTC Enable Voltage Voltage [7] [6:0] [7:0] 8.0 V 5.0 V 5.1 V 5.2 V 5.3 V 5.4 V 5.5 V 5.6 V 5.7 V 5.8 V 5.9 V 6.0 V 6.1 V 6.2 V 6.3 V 6.4 V 6.5 V 6.6 V 6.7 V 6.8 V 6.9 V 7.0 V 7.1 V 7.2 V 7.3 V 7.4 V 7.5 V 7.6 V 7.7 V 7.8 V 7.9 V 8.0 V 8.1 V 8.2 V 8.3 V 8.4 V 8.5 V 8.6 V 8.7 V 8.8 V 8.9 V 9.0 V 9.1 V 9.2 V 9.3 V 9.4 V 9.5 V 9.6 V 9.7 V 9.8 V 9.9 V 10.0 V 10.1 V 10.2 V 10.3 V 10.4 V 10.5 V 10.6 V 10.7 V 10.8 V 10.9 V 11.0 V 11.1 V 11.2 V 11.3 V 11.4 V 11.5 V 11.6 V 11.7 V 11.8 V 11.9 V 12.0 V 12.1 V 12.2 V 12.3 V 12.4 V 12.5 V 12.6 V 12.7 V 12.8 V 03h 8.2 V 8.4 V 8.6 V 8.8 V 9.0 V 9.2 V 9.4 V 9.6 V 9.8 V 10.0 V 10.2 V 10.4 V 10.6 V 10.8 V 11.0 V 11.2 V 11.4 V 11.6 V 11.8 V 12.0 V 12.2 V 12.4 V 12.6 V 12.8 V 13.0 V 13.2 V 13.4 V 13.6 V 13.8 V 14.0 V 14.2 V 14.4 V 14.6 V 14.8 V 15.0 V 15.2 V 15.4 V 15.6 V 15.8 V 16.0 V 16.2 V 16.4 V 16.6 V 16.8 V 17.0 V 17.2 V 17.4 V 17.6 V 17.8 V 18.0 V 18.2 V 18.4 V 18.6 V 18.8 V 19.0 V 19.2 V 19.4 V 19.6 V 19.8 V 20.0 V 20.2 V 20.4 V 20.6 V 20.8 V 21.0 V 21.2 V 21.4 V 21.6 V 21.8 V 22.0 V 22.2 V 22.4 V 22.6 V 22.8 V 23.0 V 23.2 V 23.4 V 23.6 V 23.8 V 24.0 V 24.2 V 24.4 V 24.6 V 24.8 V 25.0 V 25.2 V 25.4 V 25.6 V Disable VGL Output Voltage [7:0] 05h 04h VCOM HOT VCOM Output NTC Enable Voltage [7] [7:0] 06h ⊿VCOM COLD Voltage [6:0] +0.0V AVDD/2 -0.00V +0.2V +0.4V +0.6V +0.8V +1.0V +1.2V +1.4V +1.6V +1.8V +2.0V +2.2V +2.4V +2.6V +2.8V +3.0V +3.2V +3.4V +3.6V +3.8V +4.0V +4.2V +4.4V +4.6V +4.8V +5.0V +5.2V +5.4V +5.6V +5.8V +6.0V +6.2V +6.4V +6.6V +6.8V +7.0V +7.2V +7.4V +7.6V +7.8V +8.0V +8.2V +8.4V +8.6V +8.8V +9.0V +9.2V +9.4V +9.6V +9.8V +10.0V +10.2V +10.4V +10.6V +10.8V +11.0V +11.2V +11.4V +11.6V +11.8V +12.0V +12.2V +12.4V +12.6V +12.8V +13.0V +13.2V +13.4V +13.6V +13.8V +14.0V +14.2V +14.4V +14.6V +14.8V AVDD/2 +0.04V -0.01V -0.02V -0.03V -0.04V -0.05V -0.06V -0.07V -0.08V -0.09V -0.10V -0.11V -0.12V -0.13V -0.14V -0.15V -0.16V -0.17V -0.18V -0.19V -0.20V -0.21V -0.22V -0.23V -0.24V -0.25V -0.26V -0.27V -0.28V -0.29V -0.30V -0.31V -0.32V -0.33V -0.34V -0.35V -0.36V -0.37V -0.38V -0.39V -0.40V -0.41V -0.42V -0.43V -0.44V -0.45V -0.46V -0.47V -0.48V -0.49V -0.50V -0.51V -0.52V -0.53V -0.54V -0.55V -0.56V -0.57V -0.58V -0.59V -0.60V -0.61V -0.62V -0.63V -0.64V -0.65V -0.66V -0.67V -0.68V -0.69V -0.70V -0.71V -0.72V -0.73V -0.74V -0.75V -0.76V -0.77V -0.78V -0.79V -0.80V -0.81V -0.82V -0.83V -0.84V -0.85V -0.86V -0.87V -0.88V -0.89V -0.90V -0.91V -0.92V -0.93V -0.94V -0.95V -0.96V -0.97V -0.98V -0.99V -1.00V -1.01V -1.02V -1.03V -1.04V -1.05V -1.06V -1.07V -1.08V -1.09V -1.10V -1.11V -1.12V -1.13V -1.14V -1.15V -1.16V -1.17V -1.18V -1.19V -1.20V -1.21V -1.22V -1.23V -1.24V -1.25V -1.26V -1.27V +15.0V . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 AVDD/2 +0.08V AVDD/2 +0.12V AVDD/2 +0.16V AVDD/2 +0.20V AVDD/2 +0.24V AVDD/2 +0.28V AVDD/2 +0.32V AVDD/2 +0.36V AVDD/2 +0.40V AVDD/2 +0.44V AVDD/2 +0.48V AVDD/2 +0.52V AVDD/2 +0.56V AVDD/2 +0.60V AVDD/2 +0.64V AVDD/2 +0.68V AVDD/2 +0.72V -4.0 V AVDD/2 +0.76V AVDD/2 +0.80V AVDD/2 +0.84V AVDD/2 +0.88V AVDD/2 +0.92V AVDD/2 +0.96V AVDD/2 +1.00V AVDD/2 +1.04V AVDD/2 +1.08V AVDD/2 +1.12V AVDD/2 +1.16V AVDD/2 +1.20V AVDD/2 +1.24V AVDD/2 +1.28V AVDD/2 +1.32V AVDD/2 +1.36V AVDD/2 +1.40V AVDD/2 +1.44V AVDD/2 +1.48V AVDD/2 +1.52V AVDD/2 +1.56V -4.1 V -4.2 V -4.3 V -4.4 V -4.5 V -4.6 V -4.7 V -4.8 V -4.9 V -5.0 V -5.1 V -5.2 V -5.3 V -5.4 V -5.5 V -5.6 V -5.7 V -5.8 V -5.9 V -6.0 V -6.1 V -6.2 V -6.3 V -6.4 V -6.5 V -6.6 V -6.7 V -6.8 V -6.9 V -7.0 V -7.1 V -7.2 V -7.3 V -7.4 V -7.5 V -7.6 V -7.7 V -7.8 V -7.9 V -8.0 V -8.1 V -8.2 V -8.3 V -8.4 V -8.5 V -8.6 V -8.7 V -8.8 V -8.9 V -9.0 V -9.1 V -9.2 V -9.3 V -9.4 V -9.5 V -9.6 V -9.7 V -9.8 V -9.9 V -10.0 V -10.1 V -10.2 V -10.3 V -10.4 V -10.5 V -10.6 V -10.7 V -10.8 V -10.9 V -11.0 V -11.1 V -11.2 V -11.3 V -11.4 V -11.5 V -11.6 V -11.7 V -11.8 V -11.9 V -12.0 V -12.1 V -12.2 V -12.3 V -12.4 V -12.5 V -12.6 V -12.7 V -12.8 V AVDD/2 +1.60V AVDD/2 +1.64V AVDD/2 +1.68V AVDD/2 +1.72V AVDD/2 +1.76V AVDD/2 +1.80V AVDD/2 +1.84V AVDD/2 +1.88V AVDD/2 +1.92V AVDD/2 +1.96V AVDD/2 +2.00V AVDD/2 +2.04V AVDD/2 +2.08V AVDD/2 +2.12V AVDD/2 +2.16V AVDD/2 +2.20V AVDD/2 +2.24V AVDD/2 +2.28V AVDD/2 +2.32V AVDD/2 +2.36V AVDD/2 +2.40V AVDD/2 +2.44V AVDD/2 +2.48V AVDD/2 +2.52V AVDD/2 +2.56V AVDD/2 +2.60V AVDD/2 +2.64V AVDD/2 +2.68V AVDD/2 +2.72V AVDD/2 +2.76V AVDD/2 +2.80V AVDD/2 +2.84V AVDD/2 +2.88V AVDD/2 +2.92V AVDD/2 +2.96V AVDD/2 +3.00V AVDD/2 +3.04V AVDD/2 +3.08V AVDD/2 +3.12V AVDD/2 +3.16V AVDD/2 +3.20V AVDD/2 +3.24V AVDD/2 +3.28V AVDD/2 +3.32V AVDD/2 +3.36V AVDD/2 +3.40V AVDD/2 +3.44V AVDD/2 +3.48V AVDD/2 +3.52V AVDD/2 +3.56V AVDD/2 +3.60V AVDD/2 +3.64V AVDD/2 +3.68V AVDD/2 +3.72V AVDD/2 +3.76V AVDD/2 +3.80V AVDD/2 +3.84V AVDD/2 +3.88V AVDD/2 +3.92V AVDD/2 +3.96V AVDD/2 +4.00V AVDD/2 +4.04V AVDD/2 +4.08V AVDD/2 +4.12V AVDD/2 +4.16V AVDD/2 +4.20V AVDD/2 +4.24V AVDD/2 +4.28V AVDD/2 +4.32V AVDD/2 +4.36V AVDD/2 +4.40V AVDD/2 +4.44V AVDD/2 +4.48V AVDD/2 +4.52V AVDD/2 +4.56V AVDD/2 +4.60V AVDD/2 +4.64V AVDD/2 +4.68V AVDD/2 +4.72V AVDD/2 +4.76V AVDD/2 +4.80V AVDD/2 +4.84V AVDD/2 +4.88V AVDD/2 +4.92V AVDD/2 +4.96V AVDD/2 +5.00V AVDD/2 +5.04V AVDD/2 +5.08V Disable VDD Phase [7] VDD MODE [6] DC/DC 07h VDD Output Voltage [5:0] 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 2.10 2.15 2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90 2.95 3.00 3.05 3.10 3.15 3.20 3.25 3.30 3.35 V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V GPM Input Delay [7:6] 08h Reset Monitor Selecet [5] VDD Reset Voltage [4:0] 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 Function Select [7] V V V V V V V V V V V V V V V V V V V V V V V V V V V Delay1 time [6:3] 0 msec Discharge time [2:0] 0 msec 1 msec 2 msec 3 msec 4 msec 5 msec 5 msec 0 msec 1 msec 2 msec 3 msec 4 msec 5 msec 10 msec 0 msec 1 msec 2 msec 3 msec 4 msec 5 msec 15 msec 0 msec 1 msec 2 msec 3 msec 4 msec 3.3 V 5 msec 0.1 usec VIN 3.40 V 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 V V V V V V V V V V V V V V V V V V V V V V V V V V V 20 msec 0 msec 1 msec 2 msec 3 msec 4 msec 5 msec 25 msec 0 msec 1 msec 2 msec 3 msec 4 msec 5 msec 30 msec 0 msec 1 msec 2 msec 3 msec 4 msec 5 msec 35 msec 0 msec 1 msec 2 msec 3 msec 4 msec 3.3 V 5 msec VD_Phase_ Set 1 41/75 LDO 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 2.10 2.15 2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90 2.95 3.00 3.05 3.10 3.15 3.20 3.25 3.30 3.35 V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V 3.40 V VDD 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 V V V V V V V V V V V V V V V V V V V V V V V V V V V Disable 40 msec 0 msec 1 msec 2 msec 3 msec 4 msec 5 msec 60 msec 0 msec 1 msec 2 msec 3 msec 4 msec 5 msec 80 msec 0 msec 1 msec 2 msec 3 msec 4 msec 5 msec 100 msec 0 msec 1 msec 2 msec 3 msec 4 msec 3.3 V 5 msec 0.5 usec VIN 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 V V V V V V V V V V V V V V V V V V V V V V V V V V V 150 msec 0 msec 1 msec 2 msec 3 msec 4 msec 5 msec 200 msec 0 msec 1 msec 2 msec 3 msec 4 msec 5 msec 250 msec 0 msec 1 msec 2 msec 3 msec 4 msec 5 msec 300 msec 0 msec 1 msec 2 msec 3 msec 4 msec 3.3 V 5 msec TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M Command Table - continued Regitser Address 00h DATA (HEX) 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h A1h A2h A3h A4h A5h A6h A7h A8h A9h AAh ABh ACh ADh AEh AFh B0h B1h B2h B3h B4h B5h B6h B7h B8h B9h BAh BBh BCh BDh BEh BFh C0h C1h C2h C3h C4h C5h C6h C7h C8h C9h CAh CBh CCh CDh CEh CFh D0h D1h D2h D3h D4h D5h D6h D7h D8h D9h DAh DBh DCh DDh DEh DFh E0h E1h E2h E3h E4h E5h E6h E7h E8h E9h EAh EBh ECh EDh EEh EFh F0h F1h F2h F3h F4h F5h F6h F7h F8h F9h FAh FBh FCh FDh FEh FFh AVDD Output Voltage [7:0] 12.9 13.0 13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.9 14.0 14.1 14.2 14.3 14.4 14.5 14.6 14.7 14.8 14.9 15.0 15.1 15.2 15.3 15.4 15.5 15.6 15.7 15.8 15.9 16.0 16.1 16.2 16.3 16.4 16.5 16.6 16.7 16.8 16.9 02h 01h V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V 03h VGH HOT VGH ⊿VGH COLD Output NTC Enable Voltage Voltage [7] [6:0] [7:0] 25.8 26.0 26.2 26.4 26.6 26.8 27.0 27.2 27.4 27.6 27.8 28.0 28.2 28.4 28.6 28.8 29.0 29.2 29.4 29.6 29.8 30.0 30.2 30.4 30.6 30.8 31.0 31.2 31.4 31.6 31.8 32.0 32.2 32.4 32.6 32.8 33.0 33.2 33.4 33.6 33.8 34.0 34.2 34.4 34.6 34.8 V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V +0.0V Enable +0.2V +0.4V +0.6V +0.8V +1.0V +1.2V +1.4V +1.6V +1.8V +2.0V +2.2V +2.4V +2.6V +2.8V +3.0V +3.2V +3.4V +3.6V +3.8V +4.0V +4.2V +4.4V +4.6V +4.8V +5.0V +5.2V +5.4V +5.6V +5.8V +6.0V +6.2V +6.4V +6.6V +6.8V +7.0V +7.2V +7.4V +7.6V +7.8V +8.0V +8.2V +8.4V +8.6V +8.8V +9.0V +9.2V +9.4V +9.6V +9.8V +10.0V +10.2V +10.4V +10.6V +10.8V +11.0V +11.2V +11.4V +11.6V +11.8V +12.0V +12.2V +12.4V +12.6V +12.8V +13.0V +13.2V +13.4V +13.6V +13.8V +14.0V +14.2V +14.4V +14.6V +14.8V VGL Output Voltage [7:0] -12.9 -13.0 -13.1 -13.2 -13.3 -13.4 -13.5 -13.6 -13.7 -13.8 -13.9 V V V V V V V V V V V VCOM HOT VCOM Output NTC Enable Voltage [7] [7:0] AVDD/2 -0.00V -0.01V -0.02V -0.03V -0.04V -0.05V -0.06V -0.07V -0.08V -0.09V -0.10V -0.11V -0.12V -0.13V -0.14V -0.15V -0.16V -0.17V -0.18V -0.19V -0.20V -0.21V -0.22V -0.23V -0.24V -0.25V -0.26V -0.27V -0.28V -0.29V -0.30V -0.31V -0.32V -0.33V -0.34V -0.35V -0.36V -0.37V -0.38V -0.39V -0.40V -0.41V -0.42V -0.43V -0.44V -0.45V -0.46V -0.47V -0.48V -0.49V -0.50V -0.51V -0.52V -0.53V -0.54V -0.55V -0.56V -0.57V -0.58V -0.59V -0.60V -0.61V -0.62V -0.63V -0.64V -0.65V -0.66V -0.67V -0.68V -0.69V -0.70V -0.71V -0.72V -0.73V -0.74V -0.75V -0.76V -0.77V -0.78V -0.79V -0.80V -0.81V -0.82V -0.83V -0.84V -0.85V -0.86V -0.87V -0.88V -0.89V -0.90V -0.91V -0.92V -0.93V -0.94V -0.95V -0.96V -0.97V -0.98V -0.99V -1.00V -1.01V -1.02V -1.03V -1.04V -1.05V -1.06V -1.07V -1.08V -1.09V -1.10V -1.11V -1.12V -1.13V -1.14V -1.15V -1.16V -1.17V -1.18V -1.19V -1.20V -1.21V -1.22V -1.23V -1.24V -1.25V -1.26V -1.27V AVDD/2 -0.08V AVDD/2 -0.12V AVDD/2 -0.16V AVDD/2 -0.20V AVDD/2 -0.24V AVDD/2 -0.28V AVDD/2 -0.32V AVDD/2 -0.36V AVDD/2 -0.40V AVDD/2 -0.44V AVDD/2 -0.48V AVDD/2 -0.52V AVDD/2 -0.56V AVDD/2 -0.60V AVDD/2 -0.64V AVDD/2 -0.68V AVDD/2 -0.72V AVDD/2 -0.76V AVDD/2 -0.80V AVDD/2 -0.84V AVDD/2 -0.88V AVDD/2 -0.92V AVDD/2 -0.96V AVDD/2 -1.00V AVDD/2 -1.04V AVDD/2 -1.08V AVDD/2 -1.12V AVDD/2 -1.16V AVDD/2 -1.20V AVDD/2 -1.24V AVDD/2 -1.28V AVDD/2 -1.32V AVDD/2 -1.36V AVDD/2 -1.40V AVDD/2 -1.44V AVDD/2 -1.48V AVDD/2 -1.52V AVDD/2 -1.56V AVDD/2 -1.60V AVDD/2 -1.64V AVDD/2 -1.68V AVDD/2 -1.72V AVDD/2 -1.76V AVDD/2 -1.80V AVDD/2 -1.84V AVDD/2 -1.88V AVDD/2 -1.92V AVDD/2 -1.96V AVDD/2 -2.00V AVDD/2 -2.04V AVDD/2 -2.08V AVDD/2 -2.12V AVDD/2 -2.16V AVDD/2 -2.20V AVDD/2 -2.24V AVDD/2 -2.28V AVDD/2 -2.32V AVDD/2 -2.36V AVDD/2 -2.40V AVDD/2 -2.44V AVDD/2 -2.48V AVDD/2 -2.52V AVDD/2 -2.56V AVDD/2 -2.60V AVDD/2 -2.64V AVDD/2 -2.68V AVDD/2 -2.72V -14.0 V AVDD/2 -2.76V AVDD/2 -2.80V AVDD/2 -2.84V AVDD/2 -2.88V AVDD/2 -2.92V AVDD/2 -2.96V AVDD/2 -3.04V AVDD/2 -3.08V AVDD/2 -3.12V AVDD/2 -3.16V AVDD/2 -3.20V AVDD/2 -3.24V AVDD/2 -3.28V AVDD/2 -3.32V AVDD/2 -3.36V AVDD/2 -3.40V AVDD/2 -3.44V 35.0 V AVDD/2 -3.48V AVDD/2 -3.52V AVDD/2 -3.56V AVDD/2 -3.60V AVDD/2 -3.64V AVDD/2 -3.68V AVDD/2 -3.72V AVDD/2 -3.76V AVDD/2 -3.80V AVDD/2 -3.84V AVDD/2 -3.88V AVDD/2 -3.92V AVDD/2 -3.96V AVDD/2 -4.00V +15.0V . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 06h ⊿VCOM COLD Voltage [6:0] AVDD/2 -0.04V AVDD/2 -3.00V 17.0 V 05h 04h AVDD/2 -4.04V AVDD/2 -4.08V AVDD/2 -4.12V AVDD/2 -4.16V AVDD/2 -4.20V AVDD/2 -4.24V AVDD/2 -4.28V AVDD/2 -4.32V AVDD/2 -4.36V AVDD/2 -4.40V AVDD/2 -4.44V AVDD/2 -4.48V AVDD/2 -4.52V AVDD/2 -4.56V AVDD/2 -4.60V AVDD/2 -4.64V AVDD/2 -4.68V AVDD/2 -4.72V AVDD/2 -4.76V AVDD/2 -4.80V AVDD/2 -4.84V AVDD/2 -4.88V AVDD/2 -4.92V AVDD/2 -4.96V AVDD/2 -5.00V AVDD/2 -5.04V AVDD/2 -5.08V Enable VDD Phase [7] VDD MODE [6] DC/DC 07h VDD Output Voltage [5:0] 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 2.10 2.15 2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90 2.95 3.00 3.05 3.10 3.15 3.20 3.25 3.30 3.35 V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V GPM Input Delay [7:6] Reset Monitor Selecet [5] VDD 08h Reset Voltage [4:0] 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 Function Select [7] V V V V V V V V V V V V V V V V V V V V V V V V V V V Delay1 time [6:3] 0 msec Discharge time [2:0] 0 msec 1 msec 2 msec 3 msec 4 msec 5 msec 5 msec 0 msec 1 msec 2 msec 3 msec 4 msec 5 msec 10 msec 0 msec 1 msec 2 msec 3 msec 4 msec 5 msec 15 msec 0 msec 1 msec 2 msec 3 msec 4 msec 3.3 V 5 msec 1.0 usec VIN 3.40 V 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 V V V V V V V V V V V V V V V V V V V V V V V V V V V 20 msec 0 msec 1 msec 2 msec 3 msec 4 msec 5 msec 25 msec 0 msec 1 msec 2 msec 3 msec 4 msec 5 msec 30 msec 0 msec 1 msec 2 msec 3 msec 4 msec 5 msec 35 msec 0 msec 1 msec 2 msec 3 msec 4 msec 3.3 V 5 msec VD_Phase_ Set 2 42/75 LDO 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 2.10 2.15 2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90 2.95 3.00 3.05 3.10 3.15 3.20 3.25 3.30 3.35 V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V 3.40 V VDD 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 V V V V V V V V V V V V V V V V V V V V V V V V V V V Enable 40 msec 0 msec 1 msec 2 msec 3 msec 4 msec 5 msec 60 msec 0 msec 1 msec 2 msec 3 msec 4 msec 5 msec 80 msec 0 msec 1 msec 2 msec 3 msec 4 msec 5 msec 100 msec 0 msec 1 msec 2 msec 3 msec 4 msec 3.3 V 5 msec 1.5 usec VIN 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 V V V V V V V V V V V V V V V V V V V V V V V V V V V 150 msec 0 msec 1 msec 2 msec 3 msec 4 msec 5 msec 200 msec 0 msec 1 msec 2 msec 3 msec 4 msec 5 msec 250 msec 0 msec 1 msec 2 msec 3 msec 4 msec 5 msec 300 msec 0 msec 1 msec 2 msec 3 msec 4 msec 3.3 V 5 msec TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M Command Table - continued Regitser Address 09h DATA (HEX) 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 60h 61h 62h 63h 64h 65h 66h 67h 68h 69h 6Ah 6Bh 6Ch 6Dh 6Eh 6Fh 70h 71h 72h 73h 74h 75h 76h 77h 78h 79h 7Ah 7Bh 7Ch 7Dh 7Eh 7Fh DataRef [7] Delay3 time [6:4] 0Ah DoubleReg [3] Disable 0 msec Enable Disable 5 msec Enable Disable 10 msec Enable Disable 15 msec Enable Disable Disable 20 msec Enable Disable 25 msec Enable Disable 30 msec Enable Disable 40 msec Enable Delay2 time [2:0] 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 VGH Discharge Enable [7] Delay5 time [6:4] 0Bh AR_Time [3] 0.5 sec 0 msec 1.0 sec 0.5 sec 2 msec 1.0 sec 0.5 sec 4 msec 1.0 sec 0.5 sec 6 msec 1.0 sec Enable 0.5 sec 8 msec 1.0 sec 0.5 sec 1.0 sec 0.5 sec 10 msec 1.0 sec 0.5 sec 1.0 sec Delay4 time [2:0] 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec AVDD COMP [7] AVDD OCP Select [6] AVDD SS time [5:4] 0Ch AVDD SW Slew Rate [3:2] Slow2 Slow1 5 msec Fast1 Fast2 Slow2 Slow1 10 msec Fast1 Fast2 2.0 A Slow2 Slow1 15 msec Fast1 Fast2 Slow2 Slow1 20 msec Fast1 Fast2 AV_COM P_Set 1 43/75 Slow2 Slow1 5 msec Fast1 Fast2 Slow2 Slow1 10 msec Fast1 Fast2 1.0 A Slow2 Slow1 15 msec Fast1 Fast2 Slow2 Slow1 20 msec Fast1 Fast2 AVDD COIL [1:0] AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 Start-up Bit [7] VGH mode select [6] 0Dh VGH/VGL VDD AVDD Frequenc Frequenc Frequenc y y y [5:4] [3:2] [1:0] 2.1MHz 1.05MHz 2.1MHz 525KHz 2.1MHz 1.05MHz 525KHz 1.05MHz 525KHz 2.1MHz 1.05MHz 525KHz 525KHz 525KHz 525KHz 2.1MHz 1.05MHz 2.1MHz 256KHz 525KHz 1.05MHz 525KHz 2.1MHz 1.05MHz 1.05MHz 256KHz 525KHz 1.05MHz 525KHz 2.1MHz 1.05MHz 1.05MHz 525KHz 525KHz 525KHz 2.1MHz 1.05MHz 256KHz 525KHz 525KHz 256KHz 2.1MHz 1.05MHz 2.1MHz 128KHz 525KHz 525KHz 256KHz 2.1MHz 1.05MHz 1.05MHz 128KHz 525KHz 525KHz 256KHz 2.1MHz 1.05MHz 128KHz 525KHz 256KHz 525KHz 525KHz 128KHz 525KHz 256KHz 2.1MHz 1.05MHz 525KHz 2.1MHz 2.1MHz 1.05MHz 128KHz 525KHz 525KHz 256KHz 2.1MHz 1.05MHz 1.05MHz 128KHz 525KHz 525KHz 256KHz 2.1MHz 1.05MHz 128KHz 525KHz 256KHz 525KHz 525KHz 128KHz 2.1MHz 1.05MHz 2.1MHz 1.05MHz 525KHz 2.1MHz 525KHz 2.1MHz 1.05MHz 2.1MHz 1.05MHz 525KHz 1.05MHz 2.1MHz 1.05MHz 525KHz 525KHz 2.1MHz 1.05MHz 2.1MHz 1.05MHz 525KHz 2.1MHz 1.05MHz 525KHz 525KHz 2.1MHz 1.05MHz 525KHz 525KHz 1.05MHz 525KHz 2.1MHz 1.05MHz 525KHz 256KHz 1.05MHz 525KHz 525KHz 1.05MHz 2.1MHz 1.05MHz 256KHz 525KHz 1.05MHz 525KHz 2.1MHz 1.05MHz 256KHz 1.05MHz 525KHz x2 mode 2.1MHz 1.05MHz 1.05MHz 525KHz 256KHz Disable 2.1MHz 1.05MHz 2.1MHz 1.05MHz 525KHz x3 mode 2.1MHz 1.05MHz 525KHz 2.1MHz 1.05MHz 525KHz 2.1MHz 2.1MHz 1.05MHz 256KHz 525KHz 525KHz 256KHz 2.1MHz 1.05MHz 525KHz 128KHz 525KHz 525KHz 256KHz 2.1MHz 1.05MHz 1.05MHz 128KHz 525KHz 525KHz 256KHz 2.1MHz 1.05MHz 128KHz 525KHz 256KHz 525KHz 2.1MHz 2.1MHz 1.05MHz 128KHz 525KHz 525KHz 256KHz 2.1MHz 1.05MHz 525KHz 128KHz 525KHz 525KHz 256KHz 2.1MHz 1.05MHz 1.05MHz 128KHz 525KHz 525KHz 256KHz 2.1MHz 1.05MHz 128KHz 525KHz 256KHz 128KHz Check Sum [7:0] 525KHz 2.1MHz 2.1MHz 1.05MHz 525KHz TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M Command Table – continued Regitser Address 09h DATA (HEX) 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h A1h A2h A3h A4h A5h A6h A7h A8h A9h AAh ABh ACh ADh AEh AFh B0h B1h B2h B3h B4h B5h B6h B7h B8h B9h BAh BBh BCh BDh BEh BFh C0h C1h C2h C3h C4h C5h C6h C7h C8h C9h CAh CBh CCh CDh CEh CFh D0h D1h D2h D3h D4h D5h D6h D7h D8h D9h DAh DBh DCh DDh DEh DFh E0h E1h E2h E3h E4h E5h E6h E7h E8h E9h EAh EBh ECh EDh EEh EFh F0h F1h F2h F3h F4h F5h F6h F7h F8h F9h FAh FBh FCh FDh FEh FFh DataRef [7] Delay3 time [6:4] 0Ah DoubleReg [3] Disable 0 msec Enable Disable 5 msec Enable Disable 10 msec Enable Disable 15 msec Enable Enable Disable 20 msec Enable Disable 25 msec Enable Disable 30 msec Enable Disable 40 msec Enable Delay2 time [2:0] 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 VGH Discharge Enable [7] Delay5 time [6:4] 0Bh AR_Time [3] 0.5 sec 0 msec 1.0 sec 0.5 sec 2 msec 1.0 sec 0.5 sec 4 msec 1.0 sec 0.5 sec 6 msec 1.0 sec Disable 0.5 sec 8 msec 1.0 sec 0.5 sec 1.0 sec 0.5 sec 10 msec 1.0 sec 0.5 sec 1.0 sec Delay4 time [2:0] 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec 0 msec 5 msec 10 msec 15 msec 20 msec 25 msec 30 msec 40 msec AVDD COMP [7] AVDD OCP Select [6] AVDD SS time [5:4] 0Ch AVDD SW Slew Rate [3:2] Slow2 Slow1 5 msec Fast1 Fast2 Slow2 Slow1 10 msec Fast1 Fast2 2.0 A Slow2 Slow1 15 msec Fast1 Fast2 Slow2 Slow1 20 msec Fast1 Fast2 AV_COM P_Set 2 44/75 Slow2 Slow1 5 msec Fast1 Fast2 Slow2 Slow1 10 msec Fast1 Fast2 1.0 A Slow2 Slow1 15 msec Fast1 Fast2 Slow2 Slow1 20 msec Fast1 Fast2 AVDD COIL [1:0] AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 AVC_Set1 AVC_Set2 AVC_Set3 AVC_Set4 Start-up Bit [7] VGH mode select [6] 0Dh VGH/VGL VDD AVDD Frequenc Frequenc Frequenc y y y [5:4] [3:2] [1:0] 2.1MHz 1.05MHz 2.1MHz 525KHz 2.1MHz 1.05MHz 525KHz 1.05MHz 525KHz 2.1MHz 1.05MHz 525KHz 525KHz 525KHz 1.05MHz 525KHz 2.1MHz 1.05MHz 525KHz 1.05MHz 2.1MHz 1.05MHz 256KHz 525KHz 1.05MHz 525KHz 2.1MHz 1.05MHz 256KHz 1.05MHz 525KHz 525KHz 525KHz 2.1MHz 1.05MHz 256KHz 525KHz 525KHz 256KHz 2.1MHz 1.05MHz 2.1MHz 128KHz 525KHz 525KHz 256KHz 2.1MHz 1.05MHz 1.05MHz 128KHz 525KHz 525KHz 256KHz 2.1MHz 1.05MHz 128KHz 525KHz 256KHz 525KHz 525KHz 2.1MHz 1.05MHz 128KHz 525KHz 525KHz 256KHz 2.1MHz 1.05MHz 2.1MHz 128KHz 525KHz 525KHz 256KHz 2.1MHz 1.05MHz 1.05MHz 128KHz 525KHz 525KHz 256KHz 2.1MHz 1.05MHz 128KHz 525KHz 256KHz 525KHz 525KHz 2.1MHz 1.05MHz 128KHz 525KHz 2.1MHz 1.05MHz 2.1MHz 1.05MHz 2.1MHz 525KHz 525KHz 2.1MHz 1.05MHz 2.1MHz 1.05MHz 1.05MHz 525KHz 525KHz 2.1MHz 1.05MHz 2.1MHz 1.05MHz 525KHz 2.1MHz 1.05MHz 525KHz 525KHz 525KHz 1.05MHz 525KHz 1.05MHz 525KHz 2.1MHz 1.05MHz 525KHz 2.1MHz 256KHz 2.1MHz 1.05MHz 525KHz 1.05MHz 2.1MHz 1.05MHz 256KHz 525KHz 1.05MHz 525KHz 2.1MHz 1.05MHz 256KHz 1.05MHz 525KHz 525KHz 525KHz 256KHz x2 mode 2.1MHz 1.05MHz 525KHz 2.1MHz 256KHz 1.05MHz 525KHz Enable 2.1MHz 1.05MHz 2.1MHz 1.05MHz 525KHz x3 mode 2.1MHz 1.05MHz 525KHz 2.1MHz 1.05MHz 525KHz 256KHz 2.1MHz 1.05MHz 525KHz 2.1MHz 128KHz 525KHz 256KHz 2.1MHz 1.05MHz 525KHz 1.05MHz 2.1MHz 1.05MHz 128KHz 525KHz 525KHz 256KHz 2.1MHz 1.05MHz 128KHz 525KHz 256KHz 525KHz 525KHz 2.1MHz 1.05MHz 128KHz 525KHz 525KHz 256KHz 2.1MHz 1.05MHz 2.1MHz 128KHz 525KHz 525KHz 256KHz 2.1MHz 1.05MHz 1.05MHz 128KHz 525KHz 525KHz 256KHz 2.1MHz 1.05MHz 128KHz 525KHz 256KHz 128KHz Check Sum [7:0] 525KHz 525KHz 2.1MHz 1.05MHz 525KHz TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M Check Sum Check Sum which has been adopted in BM81810MUV-M is shown below. You will calculate the Check Sum that the sum of the data, including the Check Sum(CHK7 to CHK0) is 00h. Register 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh [7] A7 B7 C7 D7 E7 F7 G7 H7 I7 J7 K7 L7 M7 CHK7 [6] A6 B6 C6 D6 E6 F6 G6 H6 I6 J6 K6 L6 M6 CHK6 [5] A5 B5 C5 D5 E5 F5 G5 H5 I5 J5 K5 L5 M5 CHK5 [4] A4 B4 C4 D4 E4 F4 G4 H4 I4 J4 K4 L4 M4 CHK4 [3] A3 B3 C3 D3 E3 F3 G3 H3 I3 J3 K3 L3 M3 CHK3 [2] A2 B2 C2 D2 E2 F2 G2 H2 I2 J2 K2 L2 M2 CHK2 [1] A1 B1 C1 D1 E1 F1 G1 H1 I1 J1 K1 L1 M1 CHK1 [0] A0 B0 C0 D0 E0 F0 G0 H0 I0 J0 K0 L0 M0 CHK0 [A7:A0] + [B7:B0] + [C7:C0] + [D7:D0] + [E7:E0] + [F7:F0] + [G7:G0] + [H7:H0] + [I7:I0] + [J7:J0] + [K7:K0] + [L7:L0] + [M7:M0] + [CHK7:CHK0] = 00h . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 45/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M Soft Start Time BM81810MUV-M has soft start function on AVDD, VGH, VGL and VDD. Time of the soft start is up to the output voltage reaches the typ Value. The output voltage typ Value of each block is shown in the following table. BLOCK Soft Start Output Voltage Typ Value Soft Start Time AVDD 10.5 V Set Register VGH 18.0 V 5 msec VGL -6.0 V 5 msec VDD 1.2 V 1 msec The time setting Soft Start of AVDD is shown in the table below. Bit AVDD Soft Start Time 0 0 5 msec 0 1 10 msec 1 0 15 msec 1 1 20 msec The soft-start time of VGH and VGL are 5msec. The soft-start time of VDD is 1msec. The soft-start setting an example of AVDD and VGH are shown in the figure below. ex： ex： Case of VGH Case of AVDD Error of Soft-Start Time Error of Soft-Start Time Soft-Start Time Set Voltage＞ Typ. Soft-Start Time Set Voltage＞ Typ. VGH(Typ.) AVDD(Typ.) AVDD(Typ.) AVDD Error of Soft-Start Time Time Time Figure 76. Soft-Start Time If you change the setting voltage from typ values, occurs error in the soft-start time. •The setting voltage > Typ Value ••• Soft-start will be more slow. •The setting voltage < Typ Value ••• Soft-start will be more faster. No error of soft-start is occurred for change of frequency. . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 46/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M Block Diagram VDD REGISTER erramp DAC pwmcomp 30 driver VREF 31 29 VDD PGNDB VDD VINB 1 LDO SWB RST 16 28 VREG 2 VREG RESET VIN AVDD 3 load SW NTC VLSO 4 22 ADC SW 6 REGISTER erramp DAC PAVDD 7 AVDD pwmcomp Θ driver EEPROM SCL 27 SDA 26 PGND 5 VGL REGISTER LOGIC erramp DAC DRN CP_CLK driver 13 WPN 21 12 VGL VGL EN I/F 32 AVDD 8 OSC logic VCOM OSCGND REGISTER DAC VCOM 10 9 NEG VGH REGISTER erramp DAC driver 14 DRP 24 PG/LDSW VGH Power Good VGH 18 level shift CPP2 17 23 level shift FAULT VCP FAULT 16 level shift CGND CPP1 11 15 CP_CLK level shift GPM level shift GSOUT 19 GSIN 25 control level shift RE 20 Figure 77. Block Diagram . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 47/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M AVDD Block Function VIN LOAD SWITCH VLSO SW REGISTER PAVDD ERRAMP DAC PWM DRIVER PGND DISCHARGE Figure 78. AVDD Block Diagram AVDD Block (Boost DC / DC) can set the following functions by EEPROM. 1. AVDD Voltage (Register Address 00h [7:0]) AVDD voltage can be set in 0.1V step from 5.0V to 17.0V. 2. SW Switching Frequency (Register Address 0Ch [1:0]) The switching frequency can be set at 525KHz, 1.05MHz or 2.1MHz. 3. Soft Start Time (Register Address 0Bh [5:4]) Soft Start Time of AVDD can be set in 5msec step from 5msec to 20msec. 4. SW Switching Slew Rate (Register Address 0Bh [3:2]) SW pin switching Slew Rate can be controlled by the register setting. 11’b is the fastest slew rate setting, 00’b is the slowest slew rate setting. The slew rate by each setting is as follows. Slew Rate changes by the external part and load electric current conditions such as a coil or the diode, but adjustment is possible on a true set condition because Slew Rate changes by Slew Rate setting change like Figure.79. The EMI properties are improved by slowing a slew rate, but please do enough evaluations after a slew rate change because efficiency becomes the tendency to decrease. :AVDD Slew Rate setting Figure 79. AVDD Switching Slew Rate (VIN=3.3V, AVDD=10.5V, Freq=2.1MHz, L=4.7μH, IAVDD=100mA) . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 48/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M AVDD Block Function - continued AVDD Efficiency 90 85 80 Efficiency [%] 75 70 65 60 55 50 :AVDD Slew Rate setting 45 40 0 50 100 150 200 250 Load [mA] Figure 80. AVDD Efficiency (dependent on Slew Rate) (VIN=3.3V, AVDD=10.5V, Freq=2.1MHz, L=4.7μH, IAVDD=100mA) 5. OCP Detect Level (Register Address 0Bh [6]) SW pin Over Current Protection detection level can be set at 1.0A(Min) or 2.0A(Min). 6. COMP Adjust (Register Address 0B [7]) Phase Margin can be adjusted. 0’b: AV_COMP_SET1 1’b: AV_COMP_SET2 7. COIL Adjust (Register Address 0Bh [1:0]) You can adjust the settings to match the coil constant to be used. 00’b:AV_COIL_SET1 01’b:AV_COIL_SET2 10’b:AV_COIL_SET3 11’b:AV_COIL_SET4 Please set the setting of COIL Adjust by frequency setting (fs) and a coil to use. fOSC[kHz] Coil[μH] 525 525 1050 1050 2100 2100 4.7 10 4.7 10 4.7 10 Coil Adjust 0Bh[1:0] 00'b 11'b 00'b 11'b 00'b 11'b Comp Adjust 0Bh[7] 0'b 0'b 0'b 0'b 0'b 0'b *Please become more than 10μF/25V product (GRT31CC81E106KE01) x3 with AVDD output capacitor at the time of the use with a coil of 10μH. In addition, COMP Adjust coordinates phase constant of the ERRAMP output and is effective to shift to the zero point 25% low frequency side to produce by the ERRAMP output by making Comp Adjust 1'b and is effective in reducing ringing at the time of the load response by the responsiveness adjustment with the actual machine. . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 49/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M AVDD Block Function – continued About the phase characteristic, please consider it based on enough evaluations with the actual model. (1) Setting the Output L Constant (Boost Converter) The coil to use for output is decided by the rating current I LR and input current maximum value IINMAX of the coil. VIN IINMAX + 1/2 x ΔIL should not reach the rating value level IL L IL ILR AVDD IINMAX average current Figure 81. Coil Current Waveform Co Figure 82. Output Application Circuit Diagram Adjust so that IINMAX +∆IL does not reach the rating current value ILR. ∆IL can be obtained by the following equation. 1 AVDD - VIN 1 [A] Here, f is the switching frequency. ∆IL = VIN   L AVDD f Set with sufficient margin because the coil value may have the dispersion of 30%. If the coil current exceeds the rating current ILR of the coil, it may damage the IC internal element. BM81810MUV-M uses the current mode DC/DC converter control and has the optimized design at the coil value. A coil inductance (L) of 4.7 μH to 10 μH is recommended from viewpoints of electric power efficiency, response, and stability. (2) Output Capacity Settings For the capacitor to use for the output, select the capacitor which has the larger value in the ripple voltage V PP allowance value and the drop voltage allowance value at the time of sudden load change. Output ripple voltage is decided by the following equation. ∆VPP = ILMAX  RESR + 1  fCo VIN AVDD  (ILMAX - ∆IL 2 Here, f is the switching frequency and RESR is ESR of output capacitor. ) [V] Perform setting so that the voltage is within the allowable ripple voltage range. For the drop voltage during sudden load change; VDR, please perform the rough calculation by the following equation. VDR = ∆I Co  10 μs [V] However, 10 μs is the rough calculation value of the DC/DC response speed. Please set the capacitance considering the sufficient margin so that these two values are within the standard value range. (3) Selecting the Input Capacitor Since the peak current flows between the input and output at the DC/DC converter, a capacitor is required to install at the input side. For the reason, the low ESR capacitor is recommended as an input capacitor which has the value more than 10 μF and less than 100 mΩ. If a capacitor out of this range is selected, the excessive ripple voltage is superposed on the input voltage, accordingly it may cause the malfunction of IC. However these conditions may vary according to the load current, input voltage, output voltage, inductance and switching frequency. Be sure to perform the margin check using the actual product. . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 50/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M VGH Block Function AVDD REGISTER ERRAMP DAC DRIVER DRP VGH VGH level shift CPP2 DISCHARGE level shift VCP level shift CPP1 CP_CLK level shift Figure 83. VGH Block Diagram VGH Block (Positive Charge Pump) can set below functions by EEPROM. 1. VGH (HOT) Voltage (Register Address 01h [7:0]) VGH (HOT) voltage can be set in 0.2V step from 8.0V to 35.0V. 2. DRP Switching Frequency (Register Address 0Ch [5:4]) Switching frequency can be set at AVDD frequency x1, x1/2, or x1/4. 3. VGH (COLD) Voltage (Register Address 02h [6:0]) To set VGH (COLD) voltage can have the VGH voltage relates to NTC Pin voltage, when NTC Function is used. VGH (COLD) voltage range can be set in 0.2V step from VGH (HOT) + 0V to VGH (HOT) + 15.0V. Refer “NTC Block Function” for the detail description of NTC Function. 4. VGH Mode Select (Register Address 0Ch [6]) Boost Stage of Positive Charge Pump can be set by x2, x3, or x4. x2, x3 can be formed with internal element by EEPROM setting. x4 can be formed by connecting with external Diode. Since this function switch needs to change the application construction, input writing signal by I2C cannot perform Register writing. To write this Register setting, start-up bit(REG0Ch[7]) should be ”0”. The VGH voltage output range with the AVDD voltage is related, and may take UVP without being able to output the VGH voltage of the setting when do not choose appropriate constitution. Please choose appropriate constitution referring after the following pages. 5. VGH Discharge enable (Register Address 0Ah [7]) When OFF sequence, VGH pin Discharge function can be Enable/Disable. This function is to confirm when IC starts to operate. If read-and-write is performed after IC starts, the first time OFF sequence will not be reflected. . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 51/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M VGH Block Function - continued Application Example for VGH (3rd Stage Positive Charge Pump) Depending on the circuit construction, output voltage range of Charge Pump can be limited. Besides, increasing VGH negative current can lower the possible output voltage. Please consider the actual application need to select appropriate circuit construction. Below Figure shows the circuit construction of 3rd Stage Positive Charge Pump. Under this circuit, the possible setting range of VGH output voltage is (AVDD + 2) V to ( AVDD x 3 - 2 ) V. (When VGH negative current is 0mA) AVDD REGISTER ERRAMP DAC C_AVD DRIVER DRP VGH VGH C_VGH level shift CPP2 DISCHARGE C_DRP2 level shift VCP C_VCP level shift CPP1 CP_CLK C_DRP1 level shift Figure 84. 3rd Stage Positive Charge Pump Application Example for VGH (2nd Stage Positive Charge Pump) Below Figure shows the circuit construction of 2nd Stage Positive Charge Pump. Under this circuit, the possible setting range of VGH output voltage is (AVDD + 1) V to (AVDD x 2-1) V (When VGH negative current is 0mA) AVDD REGISTER ERRAMP DAC C_AVD DRIVER DRP VGH VGH C_VGH level shift CPP2 DISCHARGE level shift VCP level shift CPP1 CP_CLK C_DRP1 level shift Figure 85. 2nd Stage Positive Charge Pump . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 52/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M VGH Block Function - continued Application Example for VGH (4th Stage Positive Charge Pump) Below Figure shows the circuit construction of 4th Stage Positive Charge Pump. Under this circuit, the possible setting range of VGH output voltage is (AVDD + 3) V to (AVDD x 4 - 3) V (When VGH negative current is 0mA) AVDD REGISTER ERRAMP DAC C_AVD DRIVER DRP VGH VGH C_VGH D_VGH2 C_DRP3 level shift CPP2 C_VCP2 D_VGH1 DISCHARGE C_DRP2 level shift VCP C_VCP1 level shift CPP1 CP_CLK C_DRP1 level shift Figure 86. 4th Stage Positive Charge Pump . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 53/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M VGL Block Function PAVDD REGISTER ERRAMP DAC DRN DRIVER CP_CLK DISCHARGE VGL VGL Figure 87. VGL Block Diagram VGL Block (Negative Charge Pump) can set below functions by EEPROM. 1. VGL Voltage (Register Address 03h [7:0]) VGL voltage can be set by 0.1V step from -4.0V to -14.0V. 2. DRN Switching Frequency (Register Address 0Ch [5:4]) Switching frequency can set AVDD frequency x1, x1/2, or x1/4. Application Example for VGL (1st Stage Negative Charge Pump) Below Figure shows the circuit construction of 1st Stage Negative Charge Pump. Under this circuit, the possible setting range of VGL output voltage is -4 V to -(AVDD – 2Vf) V (When VGL positive current is 0mA) PAVDD REGISTER ERRAMP DAC C_DRN CP_CLK DRN DRIVER D_VGL DISCHARGE VGL VGL C_VGL Figure 88. 1st Stage Negative Charge Pump Application Example for VGL (2nd Stage Negative Charge Pump) Below Figure shows the circuit construction of 2nd Stage Negative Charge Pump. Under this circuit, the possible setting range of VGL output voltage is -4 V to -(AVDDx2 – 4Vf) V (When VGL positive current is 0mA) PAVDD REGISTER DAC ERRAMP CP_CLK DRN DRIVER C_DRN2 C_DRN1 D_VGL2 DISCHARGE D_VGL1 VGL C_VGL VGL C_VCN Figure 89. 2nd Stage Negative Charge Pump . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 54/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M VCOM Block Function AVDD VCOM REGISTER DAC NEG Figure 90. VCOM Block Diagram VCOM Block (VCOM Calibrator) can set below functions by EEPROM. 1. VCOM (HOT) Voltage (Register Address 04h [7:0]) VCOM (HOT) voltage can be set by 40mV step from AVDD/2 +/- 0.0V to 4.0V. 2. VCOM (CAL) Voltage (Device Address 1001111x) VCOM (CAL) voltage is the function to make minor adjustment of VCOM (HOT) voltage value. VCOM (HOT) can be set by 10mV step from +/- 0.0V to 0.63V. Refer Page 19, “EEPROM I2C Format for DVR (VCOM calibrator)” for VCOM (CAL) voltage setting. 3. VCOM (COLD) Voltage (Register Address 05h [6:0]) To set VCOM (COLD) voltage can have the VCOM voltage relates to NTC Pin voltage, when NTC Function is used. VCOM (COLD) voltage range can be set by 10mV step from VCOM (CAL)–0V to VCOM (CAL)+0.63V. Refer “NTC Block Function” for the detail description of NTC Function. However, VCOM output voltage setting range is AVDD x0.7 to AVDD x0.2 or AVDD/2+4.8V to AVDD/2-4.8V. For Example AVDD = 13.0V 10.5V +0.63V 11.13V VCOM Max Voltage AVDD x 0.7 = 13 x 0.7 = 9.1V AVDD/2 = 6.5V 2.5V . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 -0.63V 55/75 1.87V VCOM Min Voltage AVDD x 0.2 = 13 x 0.2 = 2.6V TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M VDD Block Function VINB REGISTER ERRAMP DAC PWM SWB VDD DRIVER PGNDB VDD LDO DISCHARGE Figure 91. VDD Block Diagram VDD Block (Buck DC/DC) can set below functions by EEPROM. 1. VDD Voltage (Register Address 06h [5:0]) VDD voltage can be set by 0.05V step from 0.9V to 3.4V. 2. SWB Switching Frequency (Register Address 0Ch [3:2]) Switching frequency can be set at 525KHz, 1.05MHz, or 2.1MHz. 3. VDD Phase Adjust (Register Address 06h [7]) Phase Margin can be adjusted. 0’b : VD_Phase_Set1 1’b : VD_Phase_Set2 VIN[V] 5 3.3 VDD[V] 0.9 to 1.25 1.3 to 0.9 to VDD Phase Adjust 1'b 0'b 0'b Set VDD Phase Adjust 1’b when On-duty < 25%. 4. VDD Mode Select (Register Address 06h [6]) VDD Block can be switched to DC/DC or LDO Mode. Since this function switch needs to change the application construction, input writing signal by I2C cannot perform Register writing. To write this Register setting, start-up bit(REG0Ch[7]) should be ”0”. . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 56/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M VDD Block Function – continued Application Example for VDD (Buck DC/DC) VDD application can select Buck DC/DC or LDO by “VDD Mode Select” of EEPROM setting. When VDD Mode is selected at ”0”, Buck DC/DC operates. Below figure shows example of Buck DC/DC application circuit. VINB REGISTER DAC C_VINB ERRAMP PWM SWB L_SWB VDD DRIVER C_VDD PGNDB VDD LDO DISCHARGE Figure 92. VDD Block Diagram(Buck DC/DC) Application Example for VDD (LDO) When VDD Mode is selected at ”1”, LDO operates. Below figure shows example of LDO application circuit. VINB REGISTER DAC C_VINB ERRAMP PWM SWB DRIVER PGNDB VDD C_VDD VDD LDO DISCHARGE Figure 93. VDD Block Diagram(LDO) C_VDD in LDO mode, please use 1.0μF to 10μF. In addition, when VDD function is not used, please set in VDD LDO mode, and, please connect capacitor more than 1.0μF. . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 57/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M GPM Block Function VGH level shift GSOUT GSIN control level shift RE Figure 94. GPM Block Diagram GPM Block (Gate Pulse Modulation) can set below functions by EEPROM. 1. Input Delay Time (Register Address 07h [7:6]) Falling timing of input signal can be set at 0.1μsec, 0.5μsec, 1.0μsec, or 1.5μsec. GSIN Input Delay Time GSOUT Figure 95. GPM Input Delay Time Pin connection when GPM is not used When GPM function is not used, connect GSIN pin to VIN. Connect RE pin to resistance (2.0kohm). GSOUT pin should be OPEN. . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 58/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M RESET Block Function VIN VDD RST REGISTER RESET DAC DELAY Figure 96. RESET Block Diagram RESET Block can set below functions by EEPROM. 1. RESET Detect Voltage (Register Address 07h [4:0]) RESET detection voltage can be set by 0.1V step from 0.6V to 3.3V. 2. RESET Monitor Select (Register Address 07h [5]) RESET detection pin can select from VDD and VIN. 3. Delay2 Time (Register Address 09h [2:0]) RESET detection time can be set from 0msec to 40msec. RESET Monitor pin (VIN or VDD) Detect Voltage Detect Voltage -0.1V Delay2 Time RST Figure 97. RESET Function . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 59/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M PG/LDSW Block Function PG/LDSW Block can switch PG (Power Good) and LDSW (Load Switch) function by EEPROM. Case of PG Function, When GPM Block becomes workable, PG pin will change from High to Low to recognize as all boost sequence is completed. PG/LDSW SEQUENCE LOGIC VGL Figure 98. PG/LDSW Block Diagram PG/LDSW Case of LDSW Function, This function is used when VGL voltage output is prior to AVDD voltage output. With below application construction, ”Timing Chart 3” sequence can be realized. PAVDD M_LDSW Gate Voltage AVDD LSW ON Delay PAVDD C_LDSW M_LDSW C_GD AVDD EN PG/LDSW R_LDSW R_LSGATE PG/LDSW M_LDSW Gate Voltage SEQUENCE LOGIC AVDD LDSW OFF Delay Figure 99. LDSW Function Figure 100. LDSW Delay Time LDSW on delay can be set by the formula below. 𝑅𝐿𝑆𝐺𝐴𝑇𝐸 × 𝑅𝐿𝐷𝑆𝑊 𝑅𝐿𝑆𝐺𝐴𝑇𝐸 + 𝑅𝐿𝐷𝑆𝑊 𝑉𝑡ℎ 𝐿𝐷𝑆𝑊 𝑂𝑁 𝐷𝑒𝑙𝑎𝑦 = −𝐶𝐿𝐷𝑆𝑊 × ( ) ln (1 − × ) [𝑠𝑒𝑐] 𝑅𝐿𝑆𝐺𝐴𝑇𝐸 + 𝑅𝐿𝐷𝑆𝑊 𝑅𝐿𝐷𝑆𝑊 𝐴𝑉𝐷𝐷 LDSW off delay can be set by the formula below. 𝐿𝐷𝑆𝑊 𝑂𝐹𝐹 𝐷𝑒𝑙𝑎𝑦 = −𝐶_𝐿𝐷𝑆𝑊 × 𝑅_𝐿𝐷𝑆𝑊 × ln ( 𝑅𝐿𝑆𝐺𝐴𝑇𝐸 + 𝑅𝐿𝐷𝑆𝑊 𝑉𝑡ℎ × ) [𝑠𝑒𝑐] 𝑅𝐿𝐷𝑆𝑊 𝐴𝑉𝐷𝐷 where: AVDD is AVDD setting voltage. Vth is M_LDSW gate threshold voltage When using the LDSW function, set the delay3 time to be longer than or equal to the sum of the maximum value including the variation of the load switch ON delay time and VGL soft start time. If the delay3 time setting is short, UVP is applied at startup. . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 60/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M NTC Block Function VGH REGISTER ADC 4bit NTC DAC LOGIC VCOM REGISTER Θ DAC Figure 101. NTC Block Diagram NTC Block is the function to adjust VGH, VCOM voltage depending on NTC pin voltage. NTC pin will output 40μA (Typ) current. Connecting thermistor element can perform temperature adjustment function. Below functions can be set by EEPROM. 1. VGH NTC Enable (Register Address 02h [7]) VGH Block NTC Function can be changed to Enable or Disable. 2. VCOM NTC Enable (Register Address 05h [7]) VCOM Block NTC Function can be changed to Enable or Disable. Pin connection when NTC is not used. When NTC function is not used, connect NTC pin to OPEN. EN Block Function VEN Rup EN 100KΩ 300KΩ + VREF (0.9V) 200KΩ Figure 102. EN Block Diagram When inserting resistor to EN terminal, EN threshold voltage is decided by resistance division with internal resistor. Threshold Voltage calculation; EN threshold voltage high typical ( VENH ) = 0.9/300x (400+Rup) [V] EN threshold voltage low typical ( VENL ) = 0.9/500x (600+Rup) [V] The EN threshold voltage including unevenness is as follows; . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 61/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M VGH and VCOM temperature compensation NTC[V] 1.25V 0.5V Ta[℃] VGH[V] VGH + VGH (HOT) (COLD) Fh Eh Dh Ch Bh Ah 9h 8h 7h 6h 5h 4h 3h 2h 1h 0h VGH (HOT) Ta[℃] VCOM[V] VCOM (CAL) Fh Eh Dh Ch Bh Ah 9h 8h 7h 6h 5h 4h 3h 2h 1h 0h VCOM + VCOM (CAL) (COLD) Ta[℃] Figure 103. NTC Function NTC Function can adjust VGH, VCOM voltage depending on NTC voltage (VNTC). 4 bit ADC is used to detect NTC voltage. When NTC pin voltage VNTC ≤ 0.5V, NTC function will judge as HOT setting. In this case, VGH and VCOM output voltage can be calculated by below formula. VGH = VGH (HOT) VCOM = VCOM (CAL) When NTC pin voltage VNTC ≥ 1.25V, NTC function will judge as COLD setting. VGH = VGH (HOT) + ΔVGH (COLD) VCOM = VCOM (CAL) – ΔVCOM (COLD) When NTC pin voltage is 0.5V < VNTC < 1.25V, VGH and VCOM can be estimated by below formula. 𝑉𝐺𝐻 = Δ𝑉𝐺𝐻(𝐶𝑂𝐿𝐷) 𝑉𝑁𝑇𝐶 − 0.5𝑉 ∗ (𝑅𝑂𝑈𝑁𝐷𝑈𝑃 ( ) − 𝟏) + 𝑉𝐺𝐻(𝐻𝑂𝑇) [V] 𝟏𝟓 0.047𝑉 𝑉𝐶𝑂𝑀 = 𝑉𝐶𝑂𝑀(𝐶𝐴𝐿) − . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 ΔVCOM(C𝑂𝐿𝐷) 𝑉𝑁𝑇𝐶 − 0.5𝑉 ∗ (𝑅𝑂𝑈𝑁𝐷𝑈𝑃 ( ) − 𝟏) [𝑉] 𝟏𝟓 0.047𝑉 62/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M FAULT Block Function FAULT UVLO TSD Shut Down by UVP and OCP LOGIC Check Sum Fail Register I2C Figure 104. FAULT Block Diagram FAULT Function is to inform IC situation to outside. When the operation is normal, FAULT pin will be High. When the operation is abnormal, FAULT pin will be Low. Below are the conditions to have FAULT pin to Low. I. Detect UVLO II. Start TSD III. Shutdown by UVP or OCP IV. Check Sum NG Fail Register Function When FAULT PIN is Low, it is possible to confirm which protection circuit is activating by reading Data from Fail Register. Fail Register will reflect the protection detected circuit at the moment of FAULT=Low Register Address of Fail Register is 10h. Register Address D7 D6 D5 D4 D3 D2 D1 D0 10h AVDD UVP VDD UVP VGH UVP VGL UVP Double Register Error AVDD OCP TSD Check sum Error Fail Register does not have EEPROM writing function. When VIN UVLO is detected, the data will be deleted. . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 63/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M Protection function explanation of POWER MANAGEMENT block I. UNDER VOLTAGE LOCK OUT (UVLO) The BM81810MUV-M has UVLO function for VIN and a circuit miss-operation during in under UVLO voltage operation is prevented. If VIN below UVLO voltage, it shuts down VDD, AVDD, VGH, VGL, GPM, VCOM and RESET. II. THERMAL SHUTDOWN (TSD) The BM81810MUV-M incorporates a Thermal Shut Down (TSD) function. If IC temperature exceeds 175°C (TYP), it shuts down VDD, AVDD, VGH, VGL, GPM, VCOM and RESET. III. UNDER VOLTAGE PROTECTION (UVP) This block has Under Voltage Protection (UVP) function for VDD, AVDD, VGH and VGL output. When detecting UVP, inner Counter will be activated, and after 5ms passed, it shuts down VDD, AVDD, VGH, VGL, GPM, and VCOM. (It also shuts down RESET when RESET monitors VDD voltage.) IV. OVER VOLTAGE PROTECTION (OVP) This block has Over Voltage Protection (OVP) function for AVDD output. When detecting OVP, output voltage rising is limited by forcing Switching turn off. If output voltage falls, Switching is restarted. V. OVER CURRENT PROTECTION (OCP) This block has Over Current Protection (OCP) function for VDD and AVDD. When detecting OCP, it controls Switching and limits generating over current in FET. BLOCK VDD Working Condition Action Protective removal Over current Protection ( Buck DCDC mode ) Protective Function ISWB > 1.0 A (Min) Control switching pulse duty to not over current limit ISWB < 1.0 A (Min) Over current Protection ( LDO mode ) ISWB > 0.3 A (Min) Control LDO to not over current limit. ISWB < 0.3 A (Min) IC shutdown if UVP status maintains during 5msec IC restart AVDD < ( Target Value x 1.05 ) Under Voltage Protection AVDD Detect : VDDTarget value x 0.9 Over Voltage Protection AVDD > (Target value x 1.1) Switching STOP Over current Protection ISW > 1.0 A (Min) or 2.0 A (Min) Control switching pulse duty to not over current limit IC shutdown if OCP status maintains during 5msec ISW < 1.0 A (Min) or 2.0 A (Min) IC restart Under Voltage Protection Detect : AVDDTarget value x 0.9 IC shutdown if UVP status maintains during 5msec VGH Under Voltage Protection Detect : VGHTarget value x 0.9 IC shutdown if UVP status maintains during 5msec IC restart VGL Under Voltage Protection Detect : VGL>Target value x 0.8 Release : VGL 2.55V (Typ) Thermal shutdown Tj > 175°C (Typ) IC shutdown Tj < 150°C (Typ) IC restart General . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 64/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M Double Register BM81810MUV-M can perform various setting by Register. If these settings are changed without intension, to avoid application abnormal operation, certain specific Register has error detection function. Below shows the Register with anomaly detection function. Register Address D7 D6 D5 D4 00h 07h 08h D0 ⊿VGH COLD Voltage VGL Output Voltage 04h 06h D1 VGH HOT Output Voltage VGH NTC Enable 03h 05h D2 AVDD Output Voltage 01h 02h D3 VCOM HOT Output Voltage VCOM NTC Enable VDD Phase VCOM COLD Votlage VDD MODE GPM Input Delay Function Select VDD Output Voltage Reset Monitor Select Reset Voltage Delay1 time Discharge time 09h Data Refresh Delay3 time DoubleReg Delay2 time 0Ah VGH Discharge Enable Delayt5 time AR_Time Delay4 time 0Bh AVDD COMP Start-up Bit 0Ch AVDD OCP Select VGH mode select AVDD SS Time VGH/VGL Frequency 0Dh 10h AVDD SW Slew Rate VDD Frequency AVDD COIL AVDD Frequency Check Sum AVDD UVP VDD UVP VGH UVP VGL UVP Double Register Error AVDD OCP TSD Check sum Error Double Register correspond BIT Data Refresh Data Refresh is the Function to read Data from EEPROM periodically. If Register setting is suddenly changed without intension, Data Refresh function can read Data from EEPROM to recover to the normal Data. Data Refresh performs at certain cycle period. The time of period can be set by Register at 0.5sec or 1.0sec. In the case of WPN=Low, Double Register Function and Data Refresh Function can be set by Register as Enable or Disable. Below table shows the function by each combination. In the case of WPN=High, Double Register Function and Data Refresh Function are Disable. WPN Data Refresh Double Register Data Refresh Operation Double Register Check Low 0 : Disable 0 : Disable Disable Disable （Keep working even logic abnormality happens） Low 0 : Disable 1 : Enable Disable Enable （First shutdown once logic abnormality detects. After Fault to be low for 1msec, then re-start） Low 1 : Enable 0 : Disable Enable （Data Refresh at set period） Disable （Keep working even logic abnormality happens） Low 1 : Enable 1 : Enable Enable （Data Refresh at set period） Enable (Perform Data Refresh once logic abnormality detects) High - - Disable Disable （Keep working even logic abnormality happens） . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 65/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M PCB Layout Guide GND Wiring Pattern The high current GND (PGND) should be wired thick. To reduce line impedance, the GND lines must be as short and thick as possible and uses few via. Therefore design at PCB board four layers or above is recommended. (Please use the middle layer as GND shielding and directly connect each GND.) In the case of two layers or less at PCB board designs, please enough confirm with the actual model about the heat and the noise with care to a GND wiring. Switching-Line Wiring Pattern The wiring from switching line (SW pin) of DC/DC converter to inductor and diode must be as short and thick as possible. If a wiring is long, ringing by switching increases, and the voltage over the resistance of this IC might be generated. Please note that switching line does not vary PCB layer. Switching line and wiring easily affected by noise such as feedback line must be placed separately. Switching noise spread may cause the lack of operation stability. In case the multi-layer PCB board, please note that a switching line and a line easily affected by noise or the external components are not adjacent between layers. Drawing GND shield line between switching line and these lines easily affected by noise is recommended if these lines are placed close. Power Supply Voltage Line Wiring Pattern For power supply voltage (VIN, VINB, VLSO, PAVDD, AVDD, VGH), place smooth capacitor nearby IC pin. Please note that smooth capacitor does not vary PCB layer. The figure 105 shows an application circuit on the basis of the basic PCB layout pattern guideline mentioned above. ◆ Bold line: High current line ◆ Blue line(two dots and dashed line): Wiring easily affected by noise ◆ Red line (dashed line): Noise source line such as switching line. ◆ Place smooth capacitor nearby IC pin ◆ D_SW locates it near SW terminal / PAVDD terminal of BM81810MUV-M, and a current loop of SW terminal ••• SBD ••• PAVDD, please become as short as possible. R_NTC2 R_NTC3 WPN R_NTC1 R_FLT VIN R_RE GSOUT VIN Θ R_PG VGH FAULT RE EN 10 11 12 13 14 15 16 L_SWB C_VDD VCP CPP1 C_DRP1 D_VGL DRP DRN C_DRN VGL VCOM 9 SWB 2 3 VREG 1 4 5 6 7 C_VCOM 8 C_VGL AVDD SW SCL RST VLSO SDA R_RST 25 26 27 28 29 30 31 32 GSIN C_VGH C_VCP 17 18 19 20 21 22 23 24 VIN VDD C_DRP2 CPP2 NTC PG / LDSW AVDD C_VINB C_REG (D_SW) L_SW VIN C_VIN C_AVD C_LSO Figure 105. PCB Layout Indications . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 66/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M EMC Layout Guide Introduce the plan that can design on the PCB as EMC measures. Measures by the board pattern •Wire AVDD line briefly thickly. (1) •Wire the current loop of Boost DC/DC briefly thickly. (2) Measures by the external component •Insert a common mode filter or a beads coil in the AVDD line and form the EMC filter. (3) •Place output capacitor and small capacitor (10pF - 1,000pF) in parallel. (4) •Insert the snubber circuit in SW pin. (Assumed the efficiency becomes worse) (5) Figure 106. EMI Circuit 1 (2) Figure 107. EMI Circuit 2 . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 67/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M I/O Equivalence Circuit 1. VINB 2. VREG 3. VIN VIN VINB VIN VREG 4. VLSO 6. SW 7. PAVDD VIN PAVDD PAVDD VLSO SW 8. AVDD 9. NEG 10. VCOM AVDD AVDD AVDD VCOM NEG 12. VGL AVDD 13. DRN 14. DRP PAVDD PAVDD AVDD AVDD Internal reg. DRP DRN VGL . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 68/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M I/O Equivalence Circuit - continued 15. CPP1 16. VCP 17. CPP2 VGH VGH VGH CPP2 CPP2 CPP2 VCP VCP VCP CPP1 CPP1 CPP1 AVDD AVDD 18. VGH 19. GSOUT AVDD 20. RE VGH VGH VGH 21. WPN GSOUT GSOUT RE RE 22. NTC 23. FAULT VREG VREG FAULT WPN NTC 24. PG/LDSW 25. GSIN 26. SDA VREG VREG PG/LDSW SDA GSIN . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 69/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M I/O Equivalence Circuit - continued 27. SCL 28. RST 29. VDD VREG VDD RST SCL 30. SWB 32. EN VREG VINB SWB . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 EN 70/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M Operation Notes 1. Reverse Connection of Power Supply Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when connecting the power supply, such as mounting an external diode between the power supply and the IC’s power supply terminals. 2. Power Supply Lines Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and aging on the capacitance value when using electrolytic capacitors. 3. Ground Voltage Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition. 4. Ground Wiring Pattern When using both small-signal and large-current ground traces, the two ground traces should be routed separately but connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal ground caused by large currents. Also ensure that the ground traces of external components do not cause variations on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance. 5. Thermal Consideration Should by any chance the power dissipation rating be exceeded the rise in temperature of the chip may result in deterioration of the properties of the chip. In case of exceeding this absolute maximum rating, increase the board size and copper area to prevent exceeding the Pd rating. 6. Recommended Operating Conditions These conditions represent a range within which the expected characteristics of the IC can be approximately obtained. The electrical characteristics are guaranteed under the conditions of each parameter. 7. Inrush Current When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and routing of connections. 8. Operation Under Strong Electromagnetic Field Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction. 9. Testing on Application Boards When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply should always be turned off completely before connecting or removing it from the test setup during the inspection process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during transport and storage. 10. Inter-pin Short and Mounting Errors Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin. Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and unintentional solder bridge deposited in between pins during assembly to name a few. 11. Unused Input Pins Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the power supply or ground line. . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 71/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M Operational Notes – continued 12. Regarding the Input Pin of the IC This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a parasitic diode or transistor. For example (refer to figure below): When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode. When GND > Pin B, the P-N junction operates as a parasitic transistor. Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be avoided. Resistor Transistor (NPN) Pin A Pin B C E Pin A N P+ P N N P+ N Pin B B Parasitic Elements N P+ N P N P+ B N C E Parasitic Elements P Substrate P Substrate GND GND Parasitic Elements Parasitic Elements GND GND N Region close-by Example of monolithic IC structure 13. Ceramic Capacitor When using a ceramic capacitor, determine the dielectric constant considering the change of capacitance with temperature and the decrease in nominal capacitance due to DC bias and others. 14. Area of Safe Operation (ASO) Operate the IC such that the output voltage, output current, and power dissipation are all within the Area of Safe Operation (ASO). 15. Thermal Shutdown Circuit(TSD) This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always be within the IC’s power dissipation rating. If however the rating is exceeded for a continued period, the junction temperature (Tj) will rise which will activate the TSD circuit that will turn OFF all output pins. When the Tj falls below the TSD threshold, the circuits are automatically restored to normal operation. Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from heat damage. 16. Over Current Protection Circuit (OCP) This IC incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. This protection circuit is effective in preventing damage due to sudden and unexpected incidents. However, the IC should not be used in applications characterized by continuous operation or transitioning of the protection circuit. . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 72/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M Ordering Information B M 8 1 8 1 0 Part Number M U V Package MUV: VQFN32SV5050 - ME2 Product Rank M: for Automotive Packaging specification E2: Embossed tape and reel Marking Diagram VQFN32SV5050(TOP VIEW) B M 8 1 8 1 0 Part Number Marking LOT Number Pin 1 Mark . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 73/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M Physical Dimension, Tape and Reel Information Package Name . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 VQFN32SV5050 74/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M Revision History Date Revision 25.July.2016 001 10.Jan.2019 002 9.Dec.2020 003 Changes New Release AVDD Current Limit (1A setting) Limit Maximum 3.0A -> 2.5A (P.6) Remove WPN pin from input tolerant. (P.1) Describe the package name in detail. (P.1) Change absolute maximum ratings value of WPN pin. (P.4) Add C_GD to application circuit when using LDSW mode.(P.31, P32) Correct some minor typographical errors. Updated packages and part numbers. P.75-2, P.75-3 . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 75/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M Ordering Information B M 8 1 8 1 0 Part Number M U V Package MUV: VQFN32SV050A - MZE2 Product Rank M: for Automotive Production site Z: Added Packaging specification E2: Embossed tape and reel Marking Diagram VQFN32SV050A(TOP VIEW) B M 8 1 8 1 0 Part Number Marking LOT Number Pin 1 Mark . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 75-2/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 BM81810MUV-M Physical Dimension, Tape and Reel Information Package Name . www.rohm.com © 2016 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 VQFN32SV050A 75-3/75 TSZ02201-0313AAF00730-1-2 9.Dec.2020 Rev.003 Notice Precaution on using ROHM Products 1. If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment (Note 1), aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific Applications. (Note1) Medical Equipment Classification of the Specific Applications JAPAN USA EU CHINA CLASSⅢ CLASSⅡb CLASSⅢ CLASSⅢ CLASSⅣ CLASSⅢ 2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which a failure or malfunction of our Products may cause. The following are examples of safety measures: [a] Installation of protection circuits or other protective devices to improve system safety [b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure 3. Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our Products under any special or extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of product performance, reliability, etc, prior to use, must be necessary: [a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents [b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust [c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2 [d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves [e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items [f] Sealing or coating our Products with resin or other coating materials [g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used. However, recommend sufficiently about the residue.); or Washing our Products by using water or water-soluble cleaning agents for cleaning residue after soldering [h] Use of the Products in places subject to dew condensation 4. The Products are not subject to radiation-proof design. 5. Please verify and confirm characteristics of the final or mounted products in using the Products. 6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied, confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect product performance and reliability. 7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in the range that does not exceed the maximum junction temperature. 8. Confirm that operation temperature is within the specified range described in the product specification. 9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in this document. Precaution for Mounting / Circuit board design 1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product performance and reliability. 2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products, please consult with the ROHM representative in advance. For details, please refer to ROHM Mounting specification Notice-PAA-E © 2015 ROHM Co., Ltd. All rights reserved. Rev.004 Precautions Regarding Application Examples and External Circuits 1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the characteristics of the Products and external components, including transient characteristics, as well as static characteristics. 2. You agree that application notes, reference designs, and associated data and information contained in this document are presented only as guidance for Products use. Therefore, in case you use such information, you are solely responsible for it and you must exercise your own independent verification and judgment in the use of such information contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of such information. Precaution for Electrostatic This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron, isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control). Precaution for Storage / Transportation 1. Product performance and soldered connections may deteriorate if the Products are stored in the places where: [a] the Products are exposed to sea winds or corrosive gases, including Cl 2, H2S, NH3, SO2, and NO2 [b] the temperature or humidity exceeds those recommended by ROHM [c] the Products are exposed to direct sunshine or condensation [d] the Products are exposed to high Electrostatic 2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is exceeding the recommended storage time period. 3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads may occur due to excessive stress applied when dropping of a carton. 4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of which storage time is exceeding the recommended storage time period. Precaution for Product Label A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only. Precaution for Disposition When disposing Products please dispose them properly using an authorized industry waste company. Precaution for Foreign Exchange and Foreign Trade act Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign trade act, please consult with ROHM in case of export. Precaution Regarding Intellectual Property Rights 1. All information and data including but not limited to application example contained in this document is for reference only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any other rights of any third party regarding such information or data. 2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the Products with other articles such as components, circuits, systems or external equipment (including software). 3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to manufacture or sell products containing the Products, subject to the terms and conditions herein. Other Precaution 1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM. 2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written consent of ROHM. 3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the Products or this document for any military purposes, including but not limited to, the development of mass-destruction weapons. 4. The proper names of companies or products described in this document are trademarks or registered trademarks of ROHM, its affiliated companies or third parties. Notice-PAA-E © 2015 ROHM Co., Ltd. All rights reserved. Rev.004 Datasheet General Precaution 1. Before you use our Products, you are requested to carefully read this document and fully understand its contents. ROHM shall not be in any way responsible or liable for failure, malfunction or accident arising from the use of any ROHM’s Products against warning, caution or note contained in this document. 2. All information contained in this document is current as of the issuing date and subject to change without any prior notice. Before purchasing or using ROHM’s Products, please confirm the latest information with a ROHM sales representative. 3. The information contained in this document is provided on an “as is” basis and ROHM does not warrant that all information contained in this document is accurate and/or error-free. ROHM shall not be in any way responsible or liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccuracy or errors of or concerning such information. Notice – WE © 2015 ROHM Co., Ltd. All rights reserved. Rev.001