BR24C01AFV-W

BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W / Memory ICs BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W I2C BUS compatible serial EEPROM BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W / BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W The BR24C01A-W, BR24C02-W, and BR24C04-W series are 2-wire (I2C BUS type) serial EEPROMs which are electrically programmable. ∗ I2C BUS is a registered trademark of Philips. !Applications VCRs, TVs, printers, car stereos, cordless telephones, short wave radios, programmable DIP switches !Features 1) 128×8bits (1k) serial EEPROM. (BR24C01A-W / AF-W / AFJ-W / AFV-W) 256×8bits (2k) serial EEPROM. (BR24C02-W / F-W / FJ-W / FV-W) 512×8bits (4k) serial EEPROM. (BR24C04-W / F-W / FJ-W / FV-W) 2) Two wire serial interface. 3) Operating voltage range : 2.7V∼5.5V 4) Low current consumption Active (at 5V) : 1.5mA (Typ.) Standby (at 5V) : 0.1µA (Typ.) 5) Auto erase and auto complete functions can be used during write operations. 6) Page write function. BR24C01A-W / AF-W / AFJ-W / AFV-W : 8 bytes BR24C02-W / F-W / FJ-W / FV-W : 8 bytes BR24C04-W / F-W / FJ-W / FV-W : 16 bytes 7) DATA security Write protect feature Inhibit to WRITE at low VCC 8) Noise filters at SCL and SDA pins. 9) Address can be incremented automatically during read operations. 10) Compact packages. 11) Rewriting possible up to 100,000 times 12) Data can be stored for ten years without corruption. !Absolute maximum ratings (Ta = 25°C) Parameter Applied voltage Symbol VCC Limits −0.3~+6.5 300(SSOP−B8) Power dissipation Pd 450(SOP8, SOP−J8) 800(DIP8) Storage temperature Operating temperature Input voltage Tstg Topr − −65~+125 −40~+85 −0.3~VCC+0.3 ∗1 ∗2 ∗3 Unit V mW °C °C V ∗1 Reduced by 3.0mW for each increase in Ta of 1°C over 25°C. ∗2 Reduced by 4.5mW for each increase in Ta of 1°C over 25°C. ∗3 Reduced by 8.0mW for each increase in Ta of 1°C over 25°C. BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W / Memory ICs BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W !Recommended operating conditions (Ta = 25°C) Parameter Power supply voltage Input voltage Symbol VCC VIN Limits 2.7~5.5 (WRITE) 2.7~5.5 (READ) 0~VCC Unit V V V !Block diagram BR24C01A-W / AF-W / AFJ-W / AFV-W !Pin descriptions Pin name A0, A1, A2 SCL SDA WP VCC GND Function Slave address setting pin Serial data clock Serial data input / output Write protect pin Power supply Ground A0 1 7bits 1kbits EEPROM ARRAY 8bits 8 VCC ∗ A1 2 ADDRESS DECODER 7bits SLAVE · WORD ADDRESS REGISTER DATA REGISTER 7 WP START STOP ∗ An open drain output requires a pull-up resistor. A2 3 CONTROL LOGIC ACK 6 SCL GND 4 HIGH VOLTAGE GEN. VCC LEVEL DETECT 5 SDA BR24C02-W / F-W / FJ-W / FV-W Pin name A0, A1, A2 SCL SDA WP VCC GND Function Slave address setting pin Serial data clock Serial data input / output Write protect pin Power supply Ground A0 1 8bits 2kbits EEPROM ARRAY 8bits 8 VCC ∗ A1 2 ADDRESS DECODER 8bits SLAVE · WORD ADDRESS REGISTER DATA REGISTER 7 WP START STOP ∗ An open drain output requires a pull-up resistor. A2 3 CONTROL LOGIC ACK 6 SCL GND 4 HIGH VOLTAGE GEN. VCC LEVEL DETECT 5 SDA BR24C04-W / F-W / FJ-W / FV-W Pin name A0 A1, A2 SCL SDA WP VCC GND Function N.C. Slave address setting pin Serial data clock Serial data input / output Write protect pin Power supply Ground A0 1 9bits 4kbits EEPROM ARRAY 8bits 8 VCC ∗ A1 2 ADDRESS DECODER 9bits SLAVE · WORD ADDRESS REGISTER DATA REGISTER 7 WP START STOP ∗ An open drain output requires a pull-up resistor. A2 3 CONTROL LOGIC ACK 6 SCL GND 4 HIGH VOLTAGE GEN. VCC LEVEL DETECT 5 SDA BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W / Memory ICs BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W !Electrical characteristics DC characteristics (unless otherwise noted, Ta = −40 to + 85 °C, VCC = 2.7 to 5.5V) Parameter Input high level voltage Input low level voltage Output low level coltage Input leakage current Output leakage current operatingcurrent dissipation Standby current Not designed for radiation resistance. Symbol VIH VIL VOL ILI ILO ICC ISB Min. 0.7VCC − − −1 −1 − − Typ. − − − − − − − Max. − 0.3VCC 0.4 1 1 2.0 2.0 Unit V V V µA µA mA µA Conditions − − IOL=3.0mA(SDA) VIN=0V~VCC VOUT=0V~VCC VCC=5.5V, fSCL=400kHz VCC=5.5V, SDA·SCL=VCC A0, A1, A2=GND, WP=GND Operating timing characteristics (unless otherwise noted, Ta = −40 to + 85 °C, VCC = 2.7 to 5.5V) Parameter SCL frequency Data clock HIGH time Data clock LOW time SDA / SCL rise time SDA / SCL fall time Start condition hold time Start condition setup time Input data hold time Input data setup time Output data delay time Output data hold time Stop condition setup time Bus open time before start of transfer Internal write cycle time Noise erase valid time (SCL / SDA pins) Symbol fSCL tHIGH tLOW tR tF tHD : STA tSU : STA tHD : DAT tSU : DAT tPD tDH tSU : STO tBUF tWR tI Vcc=5V±10% Min. − 0.6 1.2 − − 0.6 0.6 0 100 0.1 0.1 0.6 1.2 − − Typ. − − − − − − − − − − − − − − − Max. 400 − − 0.3 0.3 − − − − 0.9 − − − 10 0.05 − 4.0 4.7 − − 4.0 4.7 0 250 0.2 0.2 4.7 4.7 − − Vcc=3V±10% Min. Typ. − − − − − − − − − − − − − − − Max. 100 − − 1.0 0.3 − − − − 3.5 − − − 10 0.1 Unit kHz µs µs µs µs µs µs ns ns µs µs µs µs ms µs BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W / Memory ICs !Timing charts BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W tR SCL tHD : STA SDA (input) tBUF SDA (output) tSU : DAT tF tHIGH tLOW tHD : DAT tPD tDH SCL tSU : STA SDA tHD : STA tSU : STO START BIT STOP BIT · Data is read on the rising edge of SCL. · Data is output in synchronization with the falling edge of SCL. Fig.1 Synchronized data input / output timing SCL SDA D0 Write data (n address) ACK tWR Stop condition Start condition Fig.2 Write cycle timing !Circuit operation (1) Start condition (recognition of start bit) Before executing any command, when SCL is HIGH, a start condition (start bit) is required to cause SDA to fall from HIGH to LOW. This IC is designed to constantly detect whether there is a start condition (start bit) for the SDA and SCL line, and no commands will be executed unless this condition is satisfied. (See Fig.1 for the synchronized data input / output timing.) (2) Stop condition (recognition of stop bit) To stop any command, a stop condition (stop bit) is required. A stop condition is achieved when SDA goes from LOW to HIGH while SCL is HIGH. This enables commands to be completed. (See Fig.1 for the synchronized data input / output timing.) (3) Precautions concerning write commands In the WRITE mode, the transferred data is not written to the memory unless the stop bit is executed. BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W / Memory ICs BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W (4) Device addressing – BR24C01A-W / AF-W / AFJ-W / AFV-W, BR24C02-W / F-W / FJ-W / FV-W 1) Make sure the slave address is output from the master immediately after the start condition. 2) The upper four bits of the slave address are used to determine the device type. The device code for this IC is fixed at “1010”. 3) The next three bits of the slave address (A2, A1, A0 … device address) are used to select the device. This IC can address up to eight devices on the same bus. 4) The lowermost bit of the slave address (R / W … READ / WRITE) is used to set the write or read mode as follows. R / W set to 0 … Write (Random read word address setting is also 0) R / W set to 1 … Read 1010 A2 A1 A0 R/W – BR24C04-W / F-W / FJ-W / FV-W 1) Make sure the slave address is output from the master in continuation with the start condition. 2) The upper four bits of the slave address are used to determine the device type. The device code for this IC is fixed at “1010”. 3) The next two bits of the slave address (A2, A1, … device address) are used to select the device. This IC can address up to four devices on the same bus. 4) The next bit of the slave address (PS … Page Select) is used to select the page. As shown below, it can write to or read from any of the 256 words in the two pages in memory. PS set to 0 … Page 1 (000 to 0FF) PS set to 1 … Page 2 (100 to 1FF) 5) The lowermost bit of the slave address (R / W … READ / WRITE) is used to set the write or read mode as follows. R / W set to 0 … Write (Random read word address setting is also 0) R / W set to 1 … Read 1010 A2 A1 PS R/W (5) Write protect (WP) When WP pin set to VCC (High level), write protect is set by all address. When WP pin set to GND (Low level), enable to write to all address. Either control this pin or connect to GND (or VCC). It is inhibited from being left unconnected. (6) ACK signal The acknowledge signal (ACK signal) is determined by software and is used to indicate whether or not a data transfer is proceeding normally. The transmitting device, whether the master or slave, opens the bus after an 8-bit data output (µ-COM when a write or read command of the slave address input ; this IC when reading data). For the receiving device during the ninth clock cycle, SDA is set to LOW and an acknowledge signal (ACK signal) is sent to indicate that it received the 8-bit data (this IC when a write command or a read command of the slave address input, µ-COM when a read command data output). The ICs output a LOW acknowledge signal (ACK signal) after recognizing the start condition and slave address (8 bits). When data is being write to the ICs, a LOW acknowledge signal (ACK signal) is output after the receipt of each eight bits of data (word address and write data). BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W / Memory ICs BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W When data is being read from the IC, eight bits of data (read data) are output and the IC waits for a returned LOW acknowledge signal (ACK signal). When an acknowledge signal (ACK signal) is detected and a stop condition is not sent from the master (µ-COM) side, the IC continues to output data. If an acknowledge signal (ACK signal) is not detected, the IC interrupts the data transfer and ceases reading operations after recognizing the stop condition (stop bit). The IC then enters the waiting or standby state. (See Fig.3 for acknowledge signal (ACK signal) response.) Start condition (start bit) SCL (from µ-COM) SDA (µ-COM output data) SDA (IC output data) 1 8 9 Acknowledge signal (ACK signal) Fig.3 Acknowledge (ACK signal) response (during write and read slave address input) (7) Byte write cycle BR24C01A-W / AF-W / AFJ-W / AFV-W S T A R T SDA LINE W R I T E S T O P SLAVE ADDRESS WORD ADDRESS DATA 1 0 1 0 A2 A1 A0 ∗ RA /C WK WA 6 WA 0 D7 D0 A C K A C K WP Fig.4 BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W / Memory ICs BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W BR24C02-W / F-W / FJ-W / FV-W S T A R T SDA LINE W R I T E S T O P SLAVE ADDRESS WORD ADDRESS DATA 1 0 1 0 A2 A1 A0 WA 7 WA 0 D7 D0 RA /C WK WP A C K A C K Fig.5 BR24C04-W / F-W / FJ-W / FV-W S T A R T SDA LINE W R I T E S T O P SLAVE ADDRESS WORD ADDRESS DATA 1 0 1 0 A2 A1 PS WA 7 WA 0 D7 D0 RA /C WK WP A C K A C K Fig.6 • Data is written to the address designated by the word address (n address). • After eight bits of data are input, the data is written to the memory cell by issuing the stop bit. (8) Page write cycle BR24C01A-W / AF-W / AFJ-W / AFV-W S T A R T SDA LINE W R I T E ∗ RA /C WK S T O P SLAVE ADDRESS WORD ADDRESS(n) WA 6 WA 0 DATA(n) DATA(n+7) 1 0 1 0 A2 A1 A0 D7 D0 D0 A C K A C K A C K WP Fig.7 BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W / Memory ICs BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W • A 8-byte write is possible using this command. • Th page write command arbitrarily sets the upper four bits (WA6 to WA3) of the word address. The lower three bits (WA2 and WA0) can write up to eight bytes of data with the address being incremented internally. BR24C02-W / F-W / FJ-W / FV-W S T A R T SDA LINE W R I T E WA 7 SLAVE ADDRESS WORD ADDRESS(n) WA 0 DATA(n) DATA(n+7) S T O P 1 0 1 0 A2 A1 A0 D7 D0 D0 RA /C WK A C K A C K A C K WP Fig.8 • A 8-byte write is possible using this command. • Th page write command arbitrarily sets the upper five bits (WA7 to WA3) of the word address. The lower three bits (WA2 and WA0) can write up to eight bytes of data with the address being incremented internally. BR24C04-W / F-W / FJ-W / FV-W S T A R T SDA LINE W R I T E WA 7 SLAVE ADDRESS WORD ADDRESS(n) WA 0 DATA(n) DATA(n+15) S T O P 1 0 1 0 A2 A1PS D7 D0 D0 RA /C WK A C K A C K A C K WP Fig.9 • A 16-byte write is possible using this command. • Th page write command arbitrarily sets the upper four bits (WA7 to WA4) of the word address. The lower four bits (WA3 and WA0) can write up to sixteen bytes of data with the address being incremented internally. BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W / Memory ICs BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W (9) Current read cycle BR24C01A-W / AF-W / AFJ-W / AFV-W S T A R T SDA LINE SLAVE ADDRESS R E A D DATA S T O P 1 0 1 0 A2 A1 A0 D7 D0 RA /C WK Fig.10 A C K BR24C02-W / F-W / FJ-W / FV-W S T A R T SDA LINE SLAVE ADDRESS R E A D DATA S T O P 1 0 1 0 A2 A1 A0 D7 D0 RA /C WK Fig.11 A C K BR24C04-W / F-W / FJ-W / FV-W S T A R T SDA LINE SLAVE ADDRESS R E A D DATA S T O P 1 0 1 0 A2 A1 PS D7 D0 RA /C WK Fig.12 A C K • In case the previous operation is random or current read (which includes sequential read respectively), the internal address counter is increased by one from the last accessed address (n). Thus current read outputs the data of the next word address (n+1). If the last command is byte or page write, the internal address counter stays at the last address (n). Thus current read outputs the data of the word address (n). If the master does not transfer the acknowledge but does generate a stop condition, the current address read operation only provides s single byte of data. At this point, this IC discontinues transmission. • When an ACK signal LOW is detected after D0 and a stop condition is not sent from the master (µ-COM), the next word address data can be read. [All words all read enabled] (See Fig.16 to 18 for the sequential read cycles.) • This command is ended by inputting HIGH to the ACK signal after D0 and raising the SDA signal (stop condition) by setting SCL to HIGH. BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W / Memory ICs BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W (10) Random read cycle BR24C01A-W / AF-W / AFJ-W / AFV-W S T A R T SDA LINE W R I T E ∗ RA /C WK S T A R T WA 0 SLAVE ADDRESS WORD ADDRESS(n) WA 6 SLAVE ADDRESS R E A D DATA(n) S T O P 1 0 1 0 A2 A1 A0 1 0 1 0 A2 A1A0 D7 D0 A C K Fig.13 RA /C WK A C K BR24C02-W / F-W / FJ-W / FV-W S T A R T SDA LINE W R I T E WA 7 SLAVE ADDRESS WORD ADDRESS(n) WA 0 S T A R T SLAVE ADDRESS R E A D D7 DATA(n) S T O P 1 0 1 0 A2 A1A0 1 0 1 0 A2 A1 A0 D0 RA /C WK A C K Fig.14 RA /C WK A C K BR24C04-W / F-W / FJ-W / FV-W S T A R T SDA LINE W R I T E WA 7 SLAVE ADDRESS WORD ADDRESS(n) WA 0 S T A R T SLAVE ADDRESS R E A D D7 DATA(n) S T O P 1 0 1 0 A2 A1PS 1 0 1 0 A2 A1PS D0 RA /C WK A C K Fig.15 RA /C WK A C K • This command can read the designated word address data. • When an ACK signal LOW is detected after D0 and a stop condition is not sent from the master (µ-COM), the next word address data can be read. [All words all read enabled] (See Fig.16 to 18 for the sequential read cycles.) • This command is ended by inputting a HIGH signal to the ACK signal after D0 and raising the SDA signal (stop condition) by raising SCL to HIGH. BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W / Memory ICs BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W (11) Sequential read cycle (For a current read) BR24C01A-W / AF-W / AFJ-W / AFV-W S T A R T SDA LINE SLAVE ADDRESS R E A D DATA(n) DATA(n+x) S T O P 1 0 1 0 A2 A1 A0 D7 D0 D7 D0 RA /C WK A C K Fig.16 A C K A C K BR24C02-W / F-W / FJ-W / FV-W S T A R T SDA LINE SLAVE ADDRESS R E A D DATA(n) DATA(n+x) S T O P 1 0 1 0 A2 A1 A0 D7 D0 D7 D0 RA /C WK A C K Fig.17 A C K A C K BR24C04-W / F-W / FJ-W / FV-W S T A R T SDA LINE SLAVE ADDRESS R E A D DATA(n) DATA(n+x) S T O P 1 0 1 0 A2 A1PS D7 D0 D7 D0 RA /C WK A C K Fig.18 A C K A C K • When an ACK signal LOW is detected after D0 and a stop condition is not sent from the master (µ-COM), the next word address data can be read. [All words can be read] • This command is ended by inputting a HIGH signal to the ACK signal after D0 and raising the SDA signal (stop condition) using the SCL signal HIGH. • Sequential reading can also be done with a random read. BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W / Memory ICs BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W !Operation notes (1) During power rise During power rise, the VCC may rise passing though the low voltage domain in which the IC internal circuit does not work. For this reason, there is a risk of misoperation when the power rises without full IC internal reset. To prevent this, pay attention to the following points during a power rise. 1) Set SCL = SDA = “HIGH” 2) Raise the power so as to active the Power On Reset (P. O. R) circuit. Follow the steps below as to operate the P. O. R. circuit properly. 1) Set the power rise time (tR) to within 10ms. 2) Set the OFF domain for once power has been cut to 100mS minimum. VCC tR tOFF (2) SDA terminal pull-up resistance The SDA terminal is an open drain output. Consequently, it requires an external pull-up resistance. The appropriate pull-up resistance value is selected from the IC VOL-IOL features., which have been appended as measuring data, as well as VIL and ILI and other personal icons that control the IC in question. Recommended values 2.0k to 10kW 0.45 OUTPUT VOLTAGE : VOL (V) 0.4 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 0 1 2 3 4 5 OUTPUT CURRENT : IOL (mA) VCC=3.0V VCC=5.0V Ta=85°C VCC=3.0V VCC=5.0V Ta=25°C VCC=3.0V VCC=5.0V Ta=−40°C Fig.19 VOL−IOL features (Note : Typ.) Note : All memory array data are set to “FF” status at time of shipping. BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W / Memory ICs BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W !External dimensions (Units : mm) BR24C01A-W BR24C02-W BR24C04-W BR24C01AF-W BR24C02F-W BR24C04F-W 9.3 ± 0.3 8 5 6.5 ± 0.3 5.0 ± 0.2 8 5 6.2 ± 0.3 0.51Min. 7.62 1.5 ± 0.1 0.11 1 4 3.2 ± 0.2 3.4 ± 0.3 1.27 0.4 ± 0.1 0.3Min. 0.15 0.3 ± 0.1 2.54 0.5 ± 0.1 0 ~ 15 DIP8 BR24C01AFJ-W BR24C02FJ-W BR24C04FJ-W BR24C01AFV-W BR24C02FV-W BR24C04FV-W SOP8 4.9 ± 0.2 8765 3.0 ± 0.2 8 5 6.0 ± 0.3 3.9 ± 0.2 6.4 ± 0.3 4.4 ± 0.2 0.2 ± 0.1 1.375 ± 0.1 1234 0.22 ± 0.1 (0.52) 0.65 0.1 1.15 ± 0.1 1 4 0.175 0.45Min. 1.27 0.42 ± 0.1 0.1 0.3Min. 0.1 SOP-J8 SSOP-B8 0.15 ± 0.1 0.15 ± 0.1 1 4 4.4 ± 0.2