Datasheet
Serial EEPROM series Standard EEPROM
I2C BUS EEPROM (2-Wire)
BR24Sxxx-W
(8K 16K 32K 64K 128K 256K)
●General Description
2
BR24Sxxx-W is a serial EEPROM of I C BUS interface method
●Packages W(Typ.) x D(Typ.) x H(Max.)
●Features
2
Completely conforming to the world standard I C
BUS.
All controls available by 2 ports of serial clock
(SCL) and serial data (SDA)
Other devices than EEPROM can be connected to
the same port, saving microcontroller port
1.7V to 5.5V single power source action most suitable
for battery use
FAST MODE 400kHz at 1.7V to 5.5V
Page write mode useful for initial value write at
factory shipment
Highly reliable connection by Au pad and Au wire
Auto erase and auto end function at data rewrite
Low current consumption
¾
At write operation (5V)
: 0.5mA (Typ.)
¾
At read operation (5V)
: 0.2mA (Typ.)
¾
At standby operation (5V) : 0.1μA (Typ.)
Write mistake prevention function
¾ Write (write protect) function added
¾ Write mistake prevention function at low voltage
Data rewrite up to 1,000,000 times
Data kept for 40 years
Noise filter built in SCL / SDA terminal
Shipment data all address FFh
SOP8
TSSOP-B8
5.00mm x 6.20mm x 1.71mm
3.00mm x 6.40mm x 1.20mm
SOP- J8
TSSOP-B8J
4.90mm x 6.00mm x 1.65mm
3.00mm x 4.90mm x 1.10mm
SSOP-B8
MSOP8
3.00mm x 6.40mm x 1.35mm
2.90mm x 4.00mm x 0.90mm
VSON008X2030
2.00mm x 3.00mm x 0.60mm
●Page write
Number of pages
Product number
16Byte
32Byte
64Byte
BR24S08-W
BR24S16-W
BR24S32-W
BR24S64-W
BR24S128-W
BR24S256-W
●BR24Sxxx-W
Capacity
Bit
format
Type
Power source
voltage
SOP8
SOP-J8
8Kbit
1K×8
BR24S08-W
1.7V to 5.5V
●
●
●
16Kbit
2K×8
BR24S16-W
1.7V to 5.5V
●
●
32Kbit
4K×8
BR24S32-W
1.7V to 5.5V
●
64Kbit
8K×8
BR24S64-W
1.7V to 5.5V
●
128Kbit
16K×8
BR24S128-W
1.7V to 5.5V
256Kbit
32K×8
BR24S256-W
1.7V to 5.5V
○Product structure：Silicon monolithic integrated circuit
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©2012 ROHM Co., Ltd. All rights reserved.
TSZ22111･14･001
MSOP8
TSSOP-B8J
VSON008
X2030
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
SSOP-B8 TSSOP-B8
○This product is not designed protection against radioactive rays
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TSZ02201-0R2R0G100320-1-2
20.AUG.2012 Rev.001
BR24Sxxx-W
Datasheet
(8K 16K 32K 64K 128K 256K)
●Absolute Maximum Ratings (Ta=25℃)
Parameter
Symbol
Supply Voltage
VCC
Ratings
Unit
-0.3 to +6.5
V
Remarks
450 (SOP8)
When using at Ta=25℃ or higher 4.5mW to be reduced per 1℃.
450 (SOP-J8)
When using at Ta=25℃ or higher 4.5mW to be reduced per 1℃.
300 (SSOP-B8)
Power Dissipation
Pd
When using at Ta=25℃ or higher 3.0mW to be reduced per 1℃.
mW
330 (TSSOP-B8)
310 (TSSOP-B8J)
When using at Ta=25℃ or higher 3.1mW to be reduced per 1℃.
310 (MSOP8)
When using at Ta=25℃ or higher 3.1mW to be reduced per 1℃.
300 (VSON008X2030)
When using at Ta=25℃ or higher 3.0mW to be reduced per 1℃.
Storage Temperature
Tstg
－65 to +125
℃
Operating Temperature
Topr
－40 to +85
℃
‐
-0.3 to Vcc+1.0
V
Terminal Voltage
When using at Ta=25℃ or higher 3.3mW to be reduced per 1℃.
●Memory cell characteristics (Ta=25℃, Vcc=1.7V to 5.5V)
Limits
Parameter
Min.
Typ.
Number of data rewrite times *1
1,000,000
Data hold years *1
40
-
Unit
Max.
-
Times
Years
*1 Not 100% TESTED
●Recommended Operating Ratings
Parameter
Symbol
Power source voltage
Vcc
Input voltage
VIN
Ratings
1.7 to 5.5
0 to Vcc
Unit
V
●Electrical Characteristics
(Unless otherwise specified, Ta=-40℃ to +85℃, VCC=1.7V to 5.5V)
Limits
Parameter
Symbol
Unit
Min
Typ.
Max.
Condition
"H" Input Voltage1
VIH1
0.7Vcc
-
Vcc+1.0
V
"L" Input Voltage1
VIL1
-0.3
-
0.3Vcc
V
"L" Output Voltage1
VOL1
-
-
0.4
V
IOL=3.0mA , 2.5V≦Vcc≦5.5V (SDA)
"L" Output Voltage2
VOL2
-
-
0.2
V
IOL=0.7mA , 1.7V≦Vcc≦2.5V (SDA)
Input Leakage Current
ILI
-1
-
1
μA
VIN=0 to Vcc
Output Leakage Current
ILO
-1
-
1
μA
VOUT=0 to Vcc (SDA)
-
-
2.0
-
-
2.5
ICC2
-
-
0.5
mA
ISB
-
-
2.0
μA
Current consumption
at action
Standby Current
ICC1
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TSZ22111･15･001
mA
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Vcc=5.5V , fSCL =400kHz, tWR=5ms
Byte Write, Page Write BR24S08/16/32/64-W
Vcc=5.5V , fSCL =400kHz, tWR=5ms
Byte Write, Page Write BR24S128/256-W
Vcc=5.5V , fSCL =400kHz
Random read, Current read, Sequential read
Vcc=5.5V , SDA・SCL=Vcc
A0, A1, A2=GND, WP=GND
TSZ02201-0R2R0G100320-1-2
20.AUG.2012 Rev.001
BR24Sxxx-W
Datasheet
(8K 16K 32K 64K 128K 256K)
●Action timing characteristics
(Unless otherwise specified, Ta=-40℃ to +85℃, VCC=1.7V to 5.5V)
Parameter
Limits
Symbol
SCL Frequency
Data clock "High" time
Data clock "Low" time
SDA, SCL rise time *1
SDA, SCL fall time
*1
Start condition hold time
Start condition setup time
Input data hold time
Input data setup time
Output data delay time
Output data hold time
Stop condition data setup time
Bus release time before transfer start
Internal write cycle time
Noise removal valid period (SDA,SCL terminal)
WP hold time
WP setup time
WP valid time
fSCL
tHIGH
tLOW
tR
tF
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
tPD
tDH
tSU:STO
tBUF
tWR
tI
tHD:WP
tSU:WP
tHIGH:WP
Min.
Typ.
0.6
1.2
0.6
0.6
0
100
0.1
0.1
0.6
1.2
0
0.1
1.0
-
Unit
Max.
400
0.3 *2
0.3
0.9
5
0.1
-
kHz
μs
μs
μs
μs
μs
μs
ns
ns
μs
μs
μs
μs
ms
μs
ns
μs
μs
*1 : Not 100% TESTED
*2 : BR24S16/64-W : 1.0μs.
●Sync data input / output timing
tR
tF
tHIGH
SCL
SCL
tSU:DAT
tHD:STA
tLOW
tHD:DAT
tSU:STA
tHD:STA
tSU:STO
SDA
(入力)
(Input)
SDA
tBUF
tPD
tDH
SDA
(出力)
(Output)
START BIT
STOP BIT
○Input read at the rise edge of SCL
○Data output in sync with the fall of SCL
Figure 1-(a) Sync data input / output timing
Figure 1-(b) Start - stop bit timing
SCL
SCL
DATA(1)
SDA
D0
ACK
WRITE DATA(n)
SDA
tWR
STOP
CONDITION
D1
D0
DATA(n)
ACK
ACK
ｔWR
START
CONDITION
ストップコンディション
Stop
condition
WP
tSU：WP
Figure 1-(c) Write cycle timing
ｔHD：WP
Figure 1-(d) WP timing at write execution
SCL
DATA(n)
DATA(1)
SDA
D1
D0
ACK
ACK
tHIGH:WP
tWR
tWR
WP
○At write execution, in the area from the D0 taken clock rise of the first
DATA(1), to tWR, set WP= 'LOW'.
○By setting WP "HIGH" in the area, write can be cancelled.
When it is set WP = 'HIGH' during tWR, write is forcibly ended, and data
of address under access is not guaranteed, therefore write it once again.
Figure 1-(e) WP timing at write cancel
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TSZ02201-0R2R0G100320-1-2
20.AUG.2012 Rev.001
BR24Sxxx-W
Datasheet
(8K 16K 32K 64K 128K 256K)
●Block Diagram
*2
A0
1
8Kbit to 256Kbit EEPROM
array
8
Vcc
7
WP
6
SCL
5
SDA
*1
10bit
11bit
12bit
13bit
14bit
15bit
*2
A1
Adddress
decoder
2
8bit
*1 10bit
START
*2
A2
3
Data
register
Slave - word
address register
11bit
12bit
13bit
14bit
15bit
STOP
Control circuit
ACK
GND
High voltage
generating circuit
4
＊
1
Power source
voltage detection
＊
10bit: BR24S08-W
11bit: BR24S16-W
12bit: BR24S32-W
13bit: BR24S64-W
14bit: BR24S128-W
15bit: BR24S256-W
2
A0, A1=Don't use: BR24S08-W
A0, A1, A2=Don't use: BR24S16-W
●Pin Configuration
(TOP VIEW)
A0
1
A1
2
A2
3
GND
4
BR24S08-W
BR24S16-W
BR24S32-W
BR24S64-W
BR24S128-W
BR24S256-W
8
Vcc
7
WP
6
SCL
5
SDA
●Pin Descriptions
Function
Terminal
name
Input/
Output
BR24S08-W
BR24S16-W
BR24S32/64/128/256-W
A0
Input
Don't use
Don't use
Slave address setting
A1
Input
Don't use
Don't use
Slave address setting
Slave address setting
Don't use
Slave address setting
A2
Input
GND
-
SDA
Input / Output
SCL
Input
Reference voltage of all input / output, 0V.
Slave and word address,
Serial data input serial data output
Serial clock input
WP
Input
Write protect terminal
Vcc
-
Connect the power source.
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TSZ22111･15･001
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TSZ02201-0R2R0G100320-1-2
20.AUG.2012 Rev.001
BR24Sxxx-W
Datasheet
(8K 16K 32K 64K 128K 256K)
●Typical Performance Curves
(The following values are Typ. ones.)
Figure 3. "L" Input Voltage VIL
(A0, A1, A2, SCL, SDA, WP)
Figure 2. "H" Input Voltage VIH
(A0, A1, A2, SCL, SDA, WP)
Figure 4. "L" Output Voltage
VOL-IOL1(Vcc=1.7V)
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TSZ22111･15･001
Figure 5. "L" Output Voltage VOL-IOL
(Vcc=2.5V)
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TSZ02201-0R2R0G100320-1-2
20.AUG.2012 Rev.001
BR24Sxxx-W
Datasheet
(8K 16K 32K 64K 128K 256K)
ILO[uA]
●Typical Performance Curves‐Continued
Figure 7. Output Leak Current ILO (SDA)
Figure 6. Input Leak Current ILI
(A0, A1, A2, SCL, WP)
Figure 9. Current consumption at WRITE operation
ICC1
(fscl=400kHz BR24S128/256-W)
Figure 8. Current consumption at WRITE operation
ICC1
(fscl=400kHz BR24S16/32/64-W)
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TSZ02201-0R2R0G100320-1-2
20.AUG.2012 Rev.001
BR24Sxxx-W
Datasheet
(8K 16K 32K 64K 128K 256K)
●Typical Performance Curves‐Continued
Figure 11. Standby operation ISB
Figure 10. Current consumption at READ operation
ICC2
(fscl=400kHz)
Figure 12. SCL frequency fSCL
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TSZ22111･15･001
Figure 13. Data clock High Period tHIGH
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TSZ02201-0R2R0G100320-1-2
20.AUG.2012 Rev.001
BR24Sxxx-W
Datasheet
(8K 16K 32K 64K 128K 256K)
●Typical Performance Curves‐Continued
Figure 14. Data clock LOW Period tLOW
Figure 15. Start Condition Hold Time tHD:STA
Figure 16. Start Condition Setup Time tSU:STA
Figure 17. Input Data Hold Time tHD:DAT(HIGH)
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TSZ02201-0R2R0G100320-1-2
20.AUG.2012 Rev.001
BR24Sxxx-W
Datasheet
(8K 16K 32K 64K 128K 256K)
●Typical Performance Curves‐Continued
Figure 18. Input Data Hold Time tHD:DAT(LOW)
Figure 19. Input Data Setup Time tSU:DAT(HIGH)
Figure 20. Input Data Setup Time tSU:DAT(LOW)
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TSZ22111･15･001
Figure 21. “L” Data output delay time tPD0
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TSZ02201-0R2R0G100320-1-2
20.AUG.2012 Rev.001
BR24Sxxx-W
(8K 16K 32K 64K 128K 256K)
Datasheet
●Typical Performance Curves‐Continued
Figure 22. “H” Data output delay time tPD1
Figure 23. BUS open time before transmission tBUF
Figure 24. Internal writing cycle time tWR
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TSZ22111･15･001
Figure 25. Noise reduction affection time tl(SCL H)
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TSZ02201-0R2R0G100320-1-2
20.AUG.2012 Rev.001
BR24Sxxx-W
(8K 16K 32K 64K 128K 256K)
Datasheet
●Typical Performance Curves‐Continued
Figure 26. Noise reduction effective time tl(SCL L)
Figure 27. Noise reduction effective time tl(SDA H)
Figure 28. Noise reduction effective time tI (SDA L)
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Figure 29. WP setup time tSU:WP
TSZ02201-0R2R0G100320-1-2
20.AUG.2012 Rev.001
BR24Sxxx-W
(8K 16K 32K 64K 128K 256K)
Datasheet
WP EFECTIVE
●Typical Performance Curves‐Continued
Figure 30. WP effective time tHIGH:WP
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TSZ22111･15･001
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TSZ02201-0R2R0G100320-1-2
20.AUG.2012 Rev.001
BR24Sxxx-W
Datasheet
(8K 16K 32K 64K 128K 256K)
●I2C BUS Communication
2
○I C BUS data communication
2
I C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long,
and acknowledge is always required after each byte.
I2C BUS carries out data transmission with plural devices connected by 2 communication lines of serial data (SDA) and
serial clock (SCL).
Among devices, there are “master” that generates clock and control communication start and end, and “slave” that is
controlled by addresses peculiar to devices.
EEPROM becomes “slave”. And the device that outputs data to bus during data communication is called “transmitter”,
and the device that receives data is called “receiver”.
SDA
1-7
SCL
S
START ADDRESS
condition
8
9
R/W
ACK
1-7
8
DATA
1-7
9
ACK
8
9
DATA
ACK
P
STOP
condition
Figure 31. Data transfer timing
○Start condition (start bit recognition)
・Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL is 'HIGH'
is necessary.
・This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this condition is
satisfied, any command is executed.
○Stop condition (stop bit recognition)
・Each command can be ended by SDA rising from 'LOW' to 'HIGH' when stop condition (stop bit), namely, SCL is 'HIGH'
○Acknowledge (ACK) signal
・This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In master
and slave, the device (μ-COM at slave address input of write command, read command, and this IC at data output of read
command) at the transmitter (sending) side releases the bus after output of 8bit data.
・The device (this IC at slave address input of write command, read command, and μ-COM at data output of read command)
at the receiver (receiving) side sets SDA 'LOW' during 9 clock cycles, and outputs acknowledge signal (ACK signal)
showing that it has received the 8bit data.
・This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) 'LOW'.
・Each write action outputs acknowledge signal) (ACK signal) 'LOW', at receiving 8bit data (word address and write data).
・Each read action outputs 8bit data (read data), and detects acknowledge signal (ACK signal) 'LOW'.
・When acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (μ-COM) side, this IC
continues data output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and recognizes
stop condition (stop bit), and ends read action. And this IC gets in standby status.
○Device addressing
・Output slave address after start condition from master.
・The significant 4 bits of slave address are used for recognizing a device type. The device code of this IC is fixed to '1010'.
・Next slave addresses (A2 A1 A0 --- device address) are for selecting devices, and plural ones can be used on a same bus
according to the number of device addresses.
・The most insignificant bit (R/W --- READ/WRITE) of slave address is used for designating write or read action, and is as
shown below.
Setting R/W to 0 --- write (setting 0 to word address setting of random read)
Setting R/W to 1 --- read
Type
Slave address
―
BR24S08-W
1 0 1
0
A2 P1 P0
R/W
BR24S16-W
1 0 1
0
P2 P1 P0
R/W
BR24S32-W, BR24S64-W
BR24S128-W, BR24S256-W
1 0 1
0
A2
―
―
A1
A0
1
A1
2
1
A2
3
8
GND
4
Maximum number of
connected buses
A0 R/W
2
BR24S08-W
BR24S16-W
BR24S32-W
BR24S64-W
BR24S128-W
BR24S256-W
8
Vcc
7
WP
6
SCL
5
SDA
P0 to P2 are page select bits.
Note) Up to 2 units of BR24S08-W, up to 1 units of BR24S16-W, and up to 8 units of BR24S32/64/128/256-W can be connected.
Device address is set by 'H' and 'L' of each pin of A0, A1, and A2.
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TSZ02201-0R2R0G100320-1-2
20.AUG.2012 Rev.001
BR24Sxxx-W
Datasheet
(8K 16K 32K 64K 128K 256K)
●Write Command
○Write cycle
・Arbitrary data is written to EEPROM. When to write only 1 byte, byte write normally used, and when to write continuous
data of 2 bytes or more, simultaneous write is possible by page write cycle. The maximum number of write bytes is
specified per device of each capacity.
Up to 64 arbitrary bytes can be written. (In the case of BR24S128/256-W)
S
T
A
R
T
SDA
LINE
SLAVE
ADDRESS
W
R
I
T
E
WORD
ADDRESS
WA
7
1 0 1 0 A2 A1 A0
DATA
WA
0
D7
D0
A
C
K
R A
/ C
W K
Note)
S
T
O
P
A
C
K
Figure 32. Byte write cycle (BR24S08/16-W)
S
T
A
R
T
SDA
LINE
W
R
I
T
E
SLAVE
ADDRESS
＊ WA WA WAWA
14 13 12 11
1 0 1 0 A2 A1 A0
R A
/ C
W K
Note)
2nd WORD
ADDRESS
1st WORD
ADDRESS
WA
0
*1
D0
D7
A
C
K
A
C
K
*1
S
T
O
P
DATA
As for WA12, BR24S32-W becomes Don't care.
As for WA13, BR24S32/64-W becomes Don't care.
As for WA14, BR24S32/64/128-W becomes Don't care.
A
C
K
Figure 33. Byte write cycle (BR24S32/64/128/256-W)
S
T
A
R
T
SDA
L IN E
W
R
I
T
E
SLAVE
ADDRESS
W ORD
A D D R E S S (n )
WA
7
1 0 1 0 A 2A 1A 0
SDA
L IN E
SLAVE
ADDRESS
W
R
I
T
E
R A
/ C
W K
D0
D0
A
C
K
A
C
K
(BR24S08/16-W)
1 st W O R D
A D D R E S S (n )
*1
D A T A (n )
WA
0
A
C
K
S
T
O
P
*2
2nd W ORD
A D D R E S S (n )
＊ W A W AW A W A
1 4 13 1 2 11
1 0 1 0 A 2A 1A 0
N o te )
D7
D A TA (n +1 5 )
A
C
K
Figure 34. Page write cycle
S
T
A
R
T
WA
0
R A
/ C *1
W K
注)
Note)
D A TA (n )
S
T
O
P
*2
D7
D A TA (n + 3 1 )
D0
A
C
K
*1
As for WA12, BR24S32-W becomes Don't care.
As for WA13, BR24S32/64-W becomes Don't care.
As for WA14, BR24S32/64/128-W becomes Don't care.
*2
As for BR24S128/256-W becomes (n+63).
D0
A
C
K
A
C
K
Figure 35. Page write cycle (BR24S32/64/128/256-W)
・Data is written to the address designated by word address (n-th address).
・By issuing stop bit after 8bit data input, write to memory cell inside starts.
・When internal write is started, command is not accepted for tWR (5ms at maximum).
・By page write cycle, the following can be written in bulk: Up to 16 bytes (BR24S08-W, BR24S16-W)
: Up to 32 bytes (BR24S32-W, BR24S64-W)
: Up to 64 bytes (BR24S128-W, BR24S256-W)
And when data of the maximum bytes or higher is sent, data from the first byte is overwritten.
(Refer to "Internal address increment in Page 15.)
・As for page write command of BR24S08-W and, BR24S16-W, after page select bit(PS) of slave address is designated
arbitrarily, by continuing data input of 2 bytes or more, the address of insignificant 4 bits is incremented internally, and data
up to 16 bytes can be written.
・As for page write cycle of BR24S32-W and BR24S64-W , after the significant 7 bits (in the case of BR24S32-W) of word
address, or the significant 8 bits (in the case of BR24S64-W) of word address are designated arbitrarily, by continuing data
input of 2 bytes or more, the address of insignificant 5 bits is incremented internally, and data up to 32 bytes can be written.
・As for page write cycle of BR24S128-W and BR24S256-W, after the significant 9 bit (in the case of BR24S128-W) of word
address, or the significant 10bit (in the case of BR24S256-W) of word address are designated arbitrarily, by continuing
data input of 64 bytes or more.
Note)
*1 *2 *3
1 0 1 0 A 2A 1A 0
*1
*2
*3
In BR24S16-W, A2 becomes P2
In BR24S08/16-W, A1 becomes P1
In BR24S08/16-W, A0 becomes P0
Figure 36. Difference of slave address each type
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○Notes on write cycle continuous input
At STOP (stop bit)
write starts.
S
T
A
R
T
SDA
LINE
W
R
I
T
E
SLAVE
ADDRESS
WORD
ADDRESS（ｎ）
WA
0
WA
7
1 0 1 0 P2 P1 P0
DATA(n)
R A
/ C
W K
note)
DATA(n+15)
D7
D0
A
C
K
Figure 37.
S
T
A
R
T
S
T
O
P
D0
A
C
K
1 0 1 0
A
C
K
Next command
tWR(maximum：5ms)
Command is not accepted for this
period.
Page write cycle(BR24S08/16-W)
A t S TO P (stop bit)
w rite starts.
SDA
L IN E
S
T
A
R
T
W
R
I
T
E
SLAVE
ADDRESS
＊
1 0 1 0 A 2A 1A 0
note )
1 st W O R D
A D D R E S S (n )
2nd W ORD
A D D R E S S (n )
W A W AW A W A
D A T A (n )
WA
0
14 13 12 11
R A
/ C
W K
A
C
K
*1
D7
S
T
O
P
*2
D A TA (n+ 31 )
D0
*1
As for WA12, BR24S32-W becomes Don't care.
As for WA13, BR24S32/64-W becomes Don't care.
As for WA14, BR24S32/64/128-W becomes Don't care.
*2
As for BR24S128/256-W becomes (n+63).
1 0 1 0
D0
A
C
K
A
C
K
A
C
K
S
T
A
R
T
N e xt co m m a n d
tW R (ma ximu m : 5 m s)
C o m m an d is n ot a ccep te d for
th is period .
Figure 38.
Page write cycle(BR24S32/64/128/256-W)
○Notes on page write cycle
List of numbers of page write
Number of pages
16Byte
32Byte
Product number
BR24S08-W
BR24S16-W
BR24S32-W
BR24S64-W
64Byte
BR24S128-W
BR24S256-W
The above numbers are maximum bytes for respective types. Any bytes below these can be written.
In the case of BR24S256-W, 1 page = 64bytes, but the page write cycle write time is 5ms at maximum for 64byte bulk write.
It does not stand 5ms at maximum × 64byte = 320ms(Max.).
○Internal address increment
Page write mode (in the case of BR24S16-W)
WA7 ----0
----0
----0
-----
WA4
0
0
0
WA3
0
0
0
WA2
0
0
0
0
0
0
-------------
WA0
0
1
0
Increment
---------
---------
0Eh
WA1
0
0
1
0
0
0
1
1
0
1
1
0
1
1
0
0
1
0
Significant bit is fixed.
No digit up
For example, when it is started from address 0Eh, therefore, increment is made as below,
0Eh→0Fh→00h→01h･･･, which please note.
* 0Eh･･･16 in hexadecimal, therefore, 00001110 becomes a binary number.
○Write protect (WP) terminal
・Write protect (WP) function
When WP terminal is set Vcc (H level), data rewrite of all address is prohibited. When it is set GND (L level), data rewrite of
all address is enabled. Be sure to connect this terminal to Vcc or GND, or control it to H level or L level. Do not use it open.
At extremely low voltage at power ON/OFF, by setting the WP terminal 'H', mistake write can be prevented.
During tWR, set the WP terminal always to 'L'. If it is set 'H', write is forcibly terminated.
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●Read Command
○Read cycle
Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle.
Random read cycle is a command to read data by designating address, and is used generally.
Current read cycle is a command to read data of internal address register without designating address, and is used when
to verify just after write cycle. In both the read cycles, sequential read cycle is available, and the next address data can
be read in succession.
S
T
A
R
T
W
R
I
T
E
SLAVE
ADDRESS
SDA
L IN E
S
T
A
R
T
W ORD
A D D R E S S (n)
WA
7
1 0 1 0 A 2 A 1A 0
WA
0
R A
/ C
W K
N o te)
R
E
A
D
S LA V E
ADDRESS
D A TA (n)
1 0 1 0 A 2 A 1A 0
A
C
K
S
T
O
P
It is necessary to input 'H'
to the last ACK.
D0
D7
A
C
K
R A
/ C
W K
Figure 39. Random read cycle (BR24S08/16-W)
S
T
A
R
T
SLAVE
ADDRESS
SDA
LINE
W
R
I
T
E
1 0 1 0 A2A1A0
Note)
＊
A
C
K
*1
R
E
A
D
SLAVE
ADDRESS
S
T
O
P
DATA(n)
*1
WA
0
WA WA WAWA
14 13 12 11
R A
/ C
W K
S
T
A
R
T
2nd WORD
ADDRESS（ｎ）
1st WORD
ADDRESS（ｎ）
1 0 1 0 A2A1A0
A
C
K
D7
D0
R A
/ C
W K
As for WA12, BR24S32-W become Don't care.
As for WA13, BR24S32/64-W become Don't care.
As for WA14, BR24S32/64/128-W become Don't care.
A
C
K
Figure 40. Random read cycle (BR24S32/64/128/256-W)
S
T
A
R
T
SDA
L IN E
R
E
A
D
S LA V E
ADDRESS
1 0 1 0 A 2 A 1A 0
D A TA (n )
D7
D0
A
C
K
R A
/ C
W K
N ote )
It is necessary to input 'H'
to the last ACK.
S
T
O
P
Figure 41. Current read cycle
S
T
A
R
T
SDA
LINE
SLAVE
ADDRESS
R
E
A
D
1 0 1 0 A2 A1A0
Note）
D7
D0
R A
/ C
W K
S
T
O
P
DATA(n+x)
DATA(n)
D7
A
C
K
D0
A
C
K
A
C
K
Figure 42. Sequential read cycle (in the case of current read cycle)
・In random read cycle, data of designated word address can be read.
・When the command just before current read cycle is random read cycle, current read cycle (each including sequential read
cycle), data of incremented last read address (n)-th address, i.e., data of the (n+1)-th address is output.
・When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (μ-COM) side, the next address
data can be read in succession.
・Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal is started at SCL signal 'H'.
・When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output.
Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to input
'H' to ACK signal after D0, and to start SDA at SCL signal 'H'.
・Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is started at SCL
signal 'H'.
Note)
*1 *2 *3
1 0 1 0 A2 A1A0
*1
*2
*3
BR24S16-W A2 becomes P2.
BR24S08/16-W A1 becomes P1.
BR24S08/16-W A0 becomes P0.
Figure 43. Difference of slave address of each type
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●Software reset
Software reset is executed when to avoid malfunction after power on, and to reset during command input. Software reset
has several kinds, and 3 kids of them are shown in the figure below. (Refer to Figure 44(a), Figure 44 (b), Figure 44 (c).) In
dummy clock input area, release the SDA bus ('H' by pull up). In dummy clock area, ACK output and read data '0' (both 'L'
level) may be output from EEPROM, therefore, if 'H' is input forcibly, output may conflict and over current may flow, leading
to instantaneous power failure of system power source or influence upon devices.
Dummy clock×14
SCL
1
2
13
Start×2
Normal command
14
SDA
Normal command
Figure 44-(a) The case of 14 Dummy clock + START + START+ command input
Start
SCL
Start
Dummy clock×9
1
2
8
Normal command
9
SDA
Normal command
Figure 44-(b) The case of START+9 Dummy clock + START + command
Start×9
SCL
1
2
3
8
7
9
Normal command
SDA
Normal command
* Start command from START input.
Figure 44-(c) START × 9 + command input
●Acknowledge polling
During internal write, all input commands are ignored, therefore ACK is not sent back. During internal automatic write
execution after write cycle input, next command (slave address) is sent, and if the first ACK signal sends back 'L', then it
means end of write action, while if it sends back 'H', it means now in writing. By use of acknowledge polling, next command
can be executed without waiting for tWR = 5ms.
When to write continuously, R/W = 0, when to carry out current read cycle after write, slave address R/W = 1 is sent, and if
ACK signal sends back 'L', then execute word address input and data so forth.
During internal write,
ACK = HIGH is sent back.
First write command
S
T
A
R
T
S
Write command T
O
P
S
T
A
R
T
S
T
A Slave
R dd
T
A
Slave
C
K
A
…
C
K
tWR
Second write command
…
S
T Slave
A
R address
T
A
C
K
H
S
T Slave
A
R address
T
A
C
K
L
Word
address
A
C
K
L
Data
A
C
K
L
S
T
O
P
tWR
After completion of internal
write, ACK=LOW is sent back,
so input next word address and
data in succession.
Figure 45. Case to continuously write by acknowledge polling
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●WP valid timing (write cancel)
WP is usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so forth, pay attention to the following WP
valid timing. During write cycle execution, in cancel valid area, by setting WP='H', write cycle can be cancelled. In both byte
write cycle and page write cycle, the area from the first start condition of command to the rise of clock to taken in D0 of
data(in page write cycle, the first byte data) is cancel invalid area.
WP input in this area becomes Don't care. Set the setup time to rise of D0 taken 100ns or more. The area from the rise of
SCL to take in D0 to the end of internal automatic write (tWR) is cancel valid area. And, when it is set WP='H' during tWR,
write is ended forcibly, data of address under access is not guaranteed, therefore, write it once again.(Refer to Figure 46.)
After execution of forced end by WP standby status gets in, so there is no need to wait for tWR (5ms at maximum).
・Rise of D0 taken clock
SCL
SCL
・Rise of SDA
SDA
D0
D1
SDA
ACK
ACK
D0
Enlarged view
SDA
S
T Slave
A
R address
T
Enlarged view
A
A
C Word C
K address K D7 D6 D5 D4 D3 D2 D1 D0
L
L
WP cancel invalid area
A
C
K
L
Data
A
C
K
L
WP cancel valid area
S
T
O
P
tWR
Write forced end
WP
Data is not written.
Data not guaranteed
Figure 46. WP valid timing
●Command cancel by start condition and stop condition
During command input, by continuously inputting start condition and stop condition, command can be cancelled.
(Refer to Figure 47.)
However, in ACK output area and during data read, SDA bus may output 'L', and in this case, start condition and stop
condition cannot be input, so reset is not available. Therefore, execute software reset. And when command is cancelled by
start, stop condition, during random read cycle, sequential read cycle, or current read cycle, internal setting address is not
determined, therefore, it is not possible to carry out current read cycle in succession. When to carry out read cycle in
succession, carry out random read cycle.
SCL
SDA
1
0
1
0
Start condition
Figure 47. Case of cancel by start, stop condition during slave address input
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●I/O peripheral circuit
○Pull up resistance of SDA terminal
SDA is NMOS open drain, so requires pull up resistance. As for this resistance value (RPU), select an appropriate value to
this resistance value from microcontroller VIL, IL, and VOL-IOL characteristics of this IC. If RPU is large, action frequency is
limited. The smaller the RPU, the larger the consumption current at action.
○Maximum value of RPU
The maximum value of RPU is determined by the following factors.
(1)SDA rise time to be determined by the capacitance (CBUS) of bus line of RPU and SDA should be tR or below.
And AC timing should be satisfied even when SDA rise time is late.
(2)The bus electric potential○
A to be determined by input leak total (IL) of device connected to bus output of 'H' to SDA
bus and RPU should sufficiently secure the input 'H' level (VIH) of microcontroller and EEPROM including recommended
noise margin 0.2Vcc.
Microcontroller
BR24SXX
Vcc - ILRPU - 0.2Vcc ≧ VIH
0.8VCC - VIH
∴
RPU ≦
IL
RPU
Ex.) When Vcc = 3V, IL=10μA, VIH = 0.7Vcc
SDA terminal
A
from(2)
0.8×3 - 0.7×3
RPU ≦
IL
10×10-6
IL
≦ 30 ［kΩ］
○Minimum value of RPU
The minimum value of RPU is determined by the following factors.
(1)When IC outputs LOW, it should be satisfied that VOLMAX=0.4V
and IOLMAX=3mA.
VCC - VOL
≦
IOL
RPU
∴
Figure 48. I/O circuit diagram
VCC - VOL
IOL
≧
RPU
Bus line
capacity
CBUS
(2)VOLMAX =0.4V should secure the input 'L' level (VIL) of microcontroller and EEPROM including recommended noise margin 0.1Vcc.
VOLMAX ≦ VIL-0.1 Vcc
Ex.) When Vcc= 3V, VOL0.4V, IOL=3mA, microcontroller, EEPROM VIL=0.3Vcc
from(1),
3－0.4
RPU ≧
3×10
≧
867
［Ω］
And
VOL=0.4［V］
VIL=0.3×3
=0.9［V］
Therefore, the condition (2) is satisfied.
○Pull up resistance of SCL terminal
When SCL control is made at CMOS output port, there is no need, but in the case there is timing where SCL becomes
'Hi-Z', add a pull up resistance. As for the pull up resistance, one of several kΩ to several ten kΩ is recommended in
consideration of drive performance of output port of microcontroller.
●A0, A1, A2, WP process
○Process of device address terminals (A0,A1,A2)
Check whether the set device address coincides with device address input sent from the master side or not, and select
one among plural devices connected to a same bus. Connect this terminal to pull up or pull down, or Vcc or GND. And,
pins (Don't use PIN) not used as device address may be set to any of ‘H’, 'L', and 'Hi-Z'.
Types with Don't use PIN
BR24S08F/FJ/FV/FVT/FVM/FVJ/NUX-W
A0, A1
BR24S16F/FJ/FV/FVT/FVM/FVJ/NUX-W
A0, A1, A2
○Process of WP terminal
WP terminal is the terminal that prohibits and permits write in hardware manner. In 'H' status, only READ is available and
WRITE of all address is prohibited. In the case of 'L', both are available. In the case of use it as an ROM, it is
recommended to connect it to pull up or Vcc. In the case to use both READ and WRITE, control WP terminal or connect
it to pull down or GND.
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●Cautions on microcontroller connection
○Rs
2
In I C BUS, it is recommended that SDA port is of open drain input/output. However, when to use CMOS input / output of
tri state to SDA port, insert a series resistance Rs between the pull up resistance Rpu and the SDA terminal of EEPROM.
This is controls over current that occurs when PMOS of the microcontroller and NMOS of EEPROM are turned ON
simultaneously. Rs also plays the role of protection of SDA terminal against surge. Therefore, even when SDA port is
open drain input/output, Rs can be used.
ACK
SCL
RPU
RS
SDA
'H' output of microcontroller
'L' output of EEPROM
Microcontre
Over current flows to SDA line by 'H' output
of microcontroller and 'L' output of
EEPROM.
EEPROM
Figure 49. I/O circuit
Figure 50. Input/output collision timing
○Maximum value of Rs
The maximum value of Rs is determined by following relations.
(1)SDA rise time to be determined by the capacity (CBUS) of bus line of Rpu and SDA shoulder be tR or below.
And AC timing should be satisfied even when SDA rise time is late.
A to be determined by Rpu and Rs the moment when EEPROM outputs 'L' to SDA bus should
(2)The bus electric potential○
sufficiently secure the input 'L' level (VIL) of microcontroller including recommended noise margin 0.1Vcc.
VCC
RPU
RS
(VCC－VOL)×RS
RPU+RS
A
VOL
∴
RS
≦
VIL－VOL－0.1VCC
1.1VCC－VIL
IOL
from(2),
RS
EEPROM
Microcontroller
×
Example）When VCC=3V, VIL=0.3VCC, VOL=0.4V,
Bus line
capacity CBUS
VIL
VOL+0.1VCC≦VIL
+
≦
0.3×3－0.4－0.1×3
1.1×3－0.3×3
≦
1.67［kΩ］
RPU
RPU=20kΩ
×
20×103
Figure 51. I/O circuit
○Maximum value of Rs
The minimum value of Rs is determined by over current at bus collision. When over current flows, noises in power source
line, and instantaneous power failure of power source may occur. When allowable over current is defined as I, the
following relation must be satisfied. Determine the allowable current in consideration of impedance of power source line
in set and so forth. Set the over current to EEPROM 10mA or below.
RPU
VCC
RS
≦
I
RS
≧
VCC
I
'L' output
RS
∴
Over currentⅠ
Example）When VCC=3V, I=10mA
'H' output
RS
Microcontroller
EEPROM
3
10×10-3
≧300[Ω]
Figure 52. I/O circuit diagram
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●I2C BUS input / output circuit
○Input (A0, A1, A2, SCL, WP)
Figure 53. Input pin circuit diagram
○Input/Output (SDA)
Figure 54. Input /output pin circuit diagram
●Notes on power ON
At power on, in IC internal circuit and set, Vcc rises through unstable low voltage area, and IC inside is not completely reset,
and malfunction may occur. To prevent this, functions of POR circuit and LVCC circuit are equipped. To assure the action,
observe the following condition at power on.
1. Set SDA = 'H' and SCL ='L' or 'H'
2. Start power source so as to satisfy the recommended conditions of tR, tOFF, and Vbot for operating POR circuit.
Recommended conditions of tR,tOFF,Vbot
tR
VCC
tOFF
tR
tOFF
Vbot
10ms or below
10ms or longer
0.3V or below
100ms or below
10ms or longer
0.2V or below
Vbot
0
Figure 55. Rise waveform diagram
3. Set SDA and SCL so as not to become 'Hi-Z'.
When the above conditions 1 and 2 cannot be observed, take the following countermeasures.
a) In the case when the above conditions 1 cannot be observed. When SDA becomes 'L' at power on.
→Control SCL and SDA as shown below, to make SCL and SDA, 'H' and 'H'.
VCC
tLOW
SCL
SDA
After Vcc becomes stable
After Vcc becomes stable
tDH
tSU:DAT
tSU:DAT
Figure 56. When SCL='H' and SDA='L'
Figure 57. When SCL='H' and SDA='L'
b) In the case when the above condition 2 cannot be observed.
→After power source becomes stable, execute software reset(Page 17).
c) In the case when the above conditions 1 and 2 cannot be observed.
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●Low voltage malfunction prevention function
LVCC circuit prevents data rewrite action at low power, and prevents wrong write.
At LVCC voltage (Typ. =1.2V) or below, it prevent data rewrite.
●Vcc noise countermeasures
○Bypass capacitor
When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is
recommended to attach a by pass capacitor (0.1μF) between IC Vcc and GND. At that moment, attach it as close to IC
as possible.
And, it is also recommended to attach a bypass capacitor between board Vcc and GND.
●Notes for Use
(1) Described numeric values and data are design representative values, and the values are not guaranteed.
(2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further
sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin
in consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI.
(3) Absolute maximum ratings
If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded,
LSI may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of
fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that
conditions exceeding the absolute maximum ratings should not be impressed to LSI.
(4) GND electric potential
Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that of
GND terminal.
(5) Terminal design
In consideration of permissible loss in actual use condition, carry out heat design with sufficient margin.
(6) Terminal to terminal shortcircuit and wrong packaging
When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may
destruct LSI. And in the case of shortcircuit between LSI terminals and terminals and power source, terminal and GND
owing to foreign matter, LSI may be destructed.
(7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently.
Status of this document
The Japanese version of this document is formal specification. A customer may use this translation version only for a reference
to help reading the formal version.
If there are any differences in translation version of this document formal version takes priority.
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Datasheet
(8K 16K 32K 64K 128K 256K)
●Ordering Information
Product Code Description
B
R
2 4
S
x x x
x
x
x
-
W
xx
BUS type
2
24：I C
Operating temperature/
Power source Voltage
-40℃ to+85℃/
1.7V to 5.5V
Capacity
08=8K
64=64K
16=16K
128=128K
32=32K
256=256K
Package
F
:SOP8
FJ
:SOP-J8
FV
: SSOP-B8
FVT
: TSSOP-B8
FVJ
: TSSOP-B8J
FVM
: MSOP8
NUX
: VSON008X2030
Double Cell
Packaging and forming specification
E2
: Embossed tape and reel
(SOP8,SOP-J8, SSOP-B8,TSSOP-B8, TSSOP-B8J)
TR
: Embossed tape and reel
www.rohm.com
©2012 ROHM Co., Ltd. All rights reserved.
TSZ22111･15･001
(MSOP8, VSON008X2030)
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BR24Sxxx-W
Datasheet
(8K 16K 32K 64K 128K 256K)
●Physical Dimension Tape and Reel Information
SOP8
6
5
1 2
3
4
0.3MIN
7
4.4±0.2
6.2±0.3
8
+6°
4° −4°
0.9±0.15
5.0±0.2
(MAX 5.35 include BURR)
0.595
1.5±0.1
+0.1
0.17 -0.05
S
S
0.11
0.1
1.27
0.42±0.1
(Unit : mm)
Tape
Embossed carrier tape
Quantity
2500pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
Direction of feed
1pin
Reel
www.rohm.com
©2012 ROHM Co., Ltd. All rights reserved.
TSZ22111･15･001
)
∗ Order quantity needs to be multiple of the minimum quantity.
24/33
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20.AUG.2012 Rev.001
BR24Sxxx-W
Datasheet
(8K 16K 32K 64K 128K 256K)
●Physical Dimension Tape and Reel Information - continued
SOP-J8
4.9±0.2
(MAX 5.25 include BURR)
7
6
5
1
2
3
4
0.45MIN
8
3.9±0.2
6.0±0.3
+6°
4° −4°
0.545
0.2±0.1
1.375±0.1
S
0.175
1.27
0.42±0.1
0.1 S
(Unit : mm)
Tape
Embossed carrier tape
Quantity
2500pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
Direction of feed
1pin
Reel
www.rohm.com
©2012 ROHM Co., Ltd. All rights reserved.
TSZ22111･15･001
)
∗ Order quantity needs to be multiple of the minimum quantity.
25/33
TSZ02201-0R2R0G100320-1-2
20.AUG.2012 Rev.001
BR24Sxxx-W
Datasheet
(8K 16K 32K 64K 128K 256K)
●Physical Dimension Tape and Reel Information - continued
SSOP-B8
3.0±0.2
(MAX 3.35 include BURR)
7
6
5
1
2
3
4
0.1
1.15±0.1
0.3MIN
6.4 ± 0.3
4.4 ± 0.2
8
0.15±0.1
S
(0.52)
0.65
0.1 S
+0.06
0.22 −0.04
0.08
M
(Unit : mm)
Tape
Embossed carrier tape
Quantity
2500pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
Direction of feed
1pin
Reel
www.rohm.com
©2012 ROHM Co., Ltd. All rights reserved.
TSZ22111･15･001
)
∗ Order quantity needs to be multiple of the minimum quantity.
26/33
TSZ02201-0R2R0G100320-1-2
20.AUG.2012 Rev.001
BR24Sxxx-W
Datasheet
(8K 16K 32K 64K 128K 256K)
●Physical Dimension Tape and Reel Information - continued
TSSOP-B8
3.0 ± 0.1
(MAX 3.35 include BURR)
7
6
5
1
2
3
4
4±4
1.0±0.2
0.5±0.15
1PIN MARK
0.525
+0.05
0.145 −0.03
S
0.1±0.05
1.2MAX
1.0±0.05
6.4±0.2
4.4±0.1
8
0.08 S
+0.05
0.245 −0.04
0.08
M
0.65
(Unit : mm)
Tape
Embossed carrier tape
Quantity
3000pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
Direction of feed
1pin
Reel
www.rohm.com
©2012 ROHM Co., Ltd. All rights reserved.
TSZ22111･15･001
)
∗ Order quantity needs to be multiple of the minimum quantity.
27/33
TSZ02201-0R2R0G100320-1-2
20.AUG.2012 Rev.001
BR24Sxxx-W
Datasheet
(8K 16K 32K 64K 128K 256K)
●Physical Dimension Tape and Reel Information - continued
TSSOP-B8J
3.0 ± 0.1
(MAX 3.35 include BURR)
5
1
2
3
4
4±4
0.45±0.15
1PIN MARK
0.95±0.2
6
3.0±0.1
7
+0.05
0.145 −0.03
0.525
S
0.1±0.05
0.85±0.05
4.9±0.2
1.1MAX
8
0.08 S
+0.05
0.32 −0.04
0.08
M
0.65
(Unit : mm)
Tape
Embossed carrier tape
Quantity
2500pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
Direction of feed
1pin
Reel
www.rohm.com
©2012 ROHM Co., Ltd. All rights reserved.
TSZ22111･15･001
)
∗ Order quantity needs to be multiple of the minimum quantity.
28/33
TSZ02201-0R2R0G100320-1-2
20.AUG.2012 Rev.001
BR24Sxxx-W
Datasheet
(8K 16K 32K 64K 128K 256K)
●Physical Dimension Tape and Reel Information - continued
MSOP8
4.0±0.2
2.8±0.1
8 7 6 5
0.6±0.2
+6°
4° −4°
0.29±0.15
2.9±0.1
(MAX 3.25 include BURR)
1 2 3 4
1PIN MARK
+0.05
0.145 −0.03
0.475
0.08±0.05
0.75±0.05
0.9MAX
S
+0.05
0.22 −0.04
0.08 S
0.65
(Unit : mm)
Tape
Embossed carrier tape
Quantity
3000pcs
Direction
of feed
TR
The direction is the 1pin of product is at the upper right when you hold
( reel on the left hand and you pull out the tape on the right hand
)
1pin
Direction of feed
Reel
www.rohm.com
©2012 ROHM Co., Ltd. All rights reserved.
TSZ22111･15･001
∗ Order quantity needs to be multiple of the minimum quantity.
29/33
TSZ02201-0R2R0G100320-1-2
20.AUG.2012 Rev.001
BR24Sxxx-W
Datasheet
(8K 16K 32K 64K 128K 256K)
●Physical Dimension Tape and Reel Information - continued
VSON008X2030
3.0±0.1
2.0±0.1
0.6MAX
1PIN MARK
1.5±0.1
0.5
1
4
8
5
0.25
1.4±0.1
0.3±0.1
C0.25
(0.12)
0.08 S
+0.03
0.02 −0.02
S
+0.05
0.25 −0.04
(Unit : mm)
Tape
Embossed carrier tape
Quantity
4000pcs
Direction
of feed
TR
The direction is the 1pin of product is at the upper right when you hold
( reel on the left hand and you pull out the tape on the right hand
Direction of feed
1pin
Reel
www.rohm.com
©2012 ROHM Co., Ltd. All rights reserved.
TSZ22111･15･001
)
∗ Order quantity needs to be multiple of the minimum quantity.
30/33
TSZ02201-0R2R0G100320-1-2
20.AUG.2012 Rev.001
BR24Sxxx-W
Datasheet
(8K 16K 32K 64K 128K 256K)
●Marking Diagrams
SOP8(TOP VIEW)
SOP-J8(TOP VIEW)
Part Number Marking
Part Number Marking
LOT Number
LOT Number
1PIN MARK
1PIN MARK
SSOP-B8(TOP VIEW)
TSSOP-B8(TOP VIEW)
Part Number Marking
Part Number Marking
LOT Number
LOT Number
1PIN MARK
1PIN MARK
TSSOP-B8J(TOP VIEW)
MSOP8(TOP VIEW)
Part Number Marking
Part Number Marking
LOT Number
LOT Number
1PIN MARK
1PIN MARK
VSON008X2030 (TOP VIEW)
Part Number Marking
LOT Number
1PIN MARK
www.rohm.com
©2012 ROHM Co., Ltd. All rights reserved.
TSZ22111･15･001
31/33
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20.AUG.2012 Rev.001
BR24Sxxx-W
(8K 16K 32K 64K 128K 256K)
Datasheet
●Marking Information
Capacity
8K
16K
32K
64K
128K
256K
Product Name
Marking
Package Type
S08
SOP8
S08
SOP-J8
S08
SSOP-B8
S08
TSSOP-B8
S08
TSSOP-B8J
S08
MSOP8
S08
VSON008X2030
S16
SOP8
S16
SOP-J8
S16
SSOP-B8
S16
TSSOP-B8
S16
TSSOP-B8J
S16
MSOP8
S16
VSON008X2030
S32
SOP8
S32
SOP-J8
S32
SSOP-B8
S32
TSSOP-B8
S32
TSSOP-B8J
S32
MSOP8
S32
VSON008X2030
S64
SOP8
S64
SOP-J8
S64
SSOP-B8
S64
TSSOP-B8
S64
TSSOP-B8J
S64
MSOP8
4S128
SOP8
4S128
SOP-J8
S128
SSOP-B8
4S128
TSSOP-B8
4S256
SOP8
4S256
SOP-J8
www.rohm.com
©2012 ROHM Co., Ltd. All rights reserved.
TSZ22111･15･001
32/33
TSZ02201-0R2R0G100320-1-2
20.AUG.2012 Rev.001
BR24Sxxx-W
Datasheet
(8K 16K 32K 64K 128K 256K)
●Revision History
Date
Revision
20.Aug.2012
001
Changes
New Release
www.rohm.com
©2012 ROHM Co., Ltd. All rights reserved.
TSZ22111･15･001
33/33
TSZ02201-0R2R0G100320-1-2
20.AUG.2012 Rev.001
Datasheet
Notice
Precaution on using ROHM Products
1.
Our Products are designed and manufactured for application in ordinary electronic equipments (such as AV equipment,
OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you
(Note 1)
, transport
intend to use our Products in devices requiring extremely high reliability (such as medical equipment
equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car
accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or
serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.
Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any
damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific
Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅣ
CLASSⅢ
2.
ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3.
Our Products are designed and manufactured for use under standard conditions and not under any special or
extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any
special or extraordinary environments or conditions. If you intend to use our Products under any special or
extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of
product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of
flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning
residue after soldering
[h] Use of the Products in places subject to dew condensation
4.
The Products are not subject to radiation-proof design.
5.
Please verify and confirm characteristics of the final or mounted products in using the Products.
6.
In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7.
De-rate Power Dissipation (Pd) depending on Ambient temperature (Ta). When used in sealed area, confirm the actual
ambient temperature.
8.
Confirm that operation temperature is within the specified range described in the product specification.
9.
ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1.
When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2.
In principle, the reflow soldering method must be used; if flow soldering method is preferred, please consult with the
ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice - GE
© 2014 ROHM Co., Ltd. All rights reserved.
Rev.002
Datasheet
Precautions Regarding Application Examples and External Circuits
1.
If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2.
You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1.
Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2.
Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3.
Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4.
Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
QR code printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since our Products might fall under controlled goods prescribed by the applicable foreign exchange and foreign trade act,
please consult with ROHM representative in case of export.
Precaution Regarding Intellectual Property Rights
1.
All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data. ROHM shall not be in any way responsible or liable
for infringement of any intellectual property rights or other damages arising from use of such information or data.:
2.
No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the information contained in this document.
Other Precaution
1.
This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2.
The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3.
In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4.
The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice - GE
© 2014 ROHM Co., Ltd. All rights reserved.
Rev.002
Datasheet
General Precaution
1. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents.
ROHM shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this docume nt is current as of the issuing date and subj ect to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the la test information with a ROHM sale s
representative.
3.
The information contained in this doc ument is provi ded on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate an d/or error-free. ROHM shall not be in an y way responsible or
liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccur acy or errors of or
concerning such information.
Notice – WE
© 2014 ROHM Co., Ltd. All rights reserved.
Rev.001
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