BR24T08FVM-WGTR

Serial EEPROM Series Standard EEPROM I2C BUS EEPROM (2-Wire) BR24T08-W General Description BR24T08 W is a serial EEPROM of I2C BUS Interface Method Features Packages W(Typ) x D(Typ) x H(Max) Completely conforming to the world standard I2C BUS. All controls available by 2 ports of serial clock (SCL) and serial data (SDA) Other devices than EEPROM can be connected to the same port, saving microcontroller port 1.6V to 5.5v Single Power Source Operation most suitable for battery use 1.6V to 5.5V wide limit of operating voltage, possible FAST MODE 400kHz operation Page Write Mode useful for initial value write at factory shipment Self-timed Programming Cycle Low current Consumption Prevention of Write Mistake Write (Write Protect) Function added Prevention of Write Mistake at Low Voltage More than 1 million write cycles More than 40 years data retention Noise filter built in SCL / SDA terminal Initial delivery state FFh TSSOP-B8 DIP-T8 9.30mm x 6.50mm x 7.10mm 3.00mm x 6.40mm x 1.20mm SOP8 5.00mm x 6.20mm x 1.71mm TSSOP-B8J 3.00mm x 4.90mm x 1.10mm SOP-J8 MSOP8 4.90mm x 6.00mm x 1.65mm 2.90mm x 4.00mm x 0.90mm SOP-J8A 4.90mm x 6.00mm x 1.75mm VSON008X2030 2.00mm x 3.00mm x 0.60mm SSOP-B8 3.00mm x 6.40mm x 1.35mm Figure 1. BR24T08-W Capacity Bit Format Type Power Source Voltage BR24T08-W DIP-T8 BR24T08F-W SOP8 BR24T08FJ-W SOP-J8 BR24T08FJ-WSGN 8Kbit Product structure 1K×8 Package BR24T08FV-W SOP-J8A 1.6V to 5.5V SSOP-B8 BR24T08FVT-W TSSOP-B8 BR24T08FVJ-W TSSOP-B8J BR24T08FVM-W MSOP8 BR24T08NUX-W VSON008X2030 Silicon monolithic integrated circuit www.rohm.com ©2013 ROHM Co., Ltd. All rights reserved. TSZ22111 14 001 This product has no designed protection against radioactive rays 1/35 TSZ02201-0R2R0G100100-1-2 31.Aug.2017 Rev.006 Datasheet BR24T08-W Absolute Maximum Ratings (Ta=25°C) Parameter Symbol Supply Voltage VCC Power Dissipation Rating Unit -0.3 to +6.5 V 450 (SOP8) Derate by 4.5mW/°C when operating above Ta=25°C 450 (SOP-J8) Derate by 4.5mW/°C when operating above Ta=25°C 300 (SSOP-B8) Derate by 3.0mW/°C when operating above Ta=25°C 330 (TSSOP-B8) Pd Remark mW 310 (TSSOP-B8J) Derate by 3.3mW/°C when operating above Ta=25°C Derate by 3.1mW/°C when operating above Ta=25°C 310 (MSOP8) Derate by 3.1mW/°C when operating above Ta=25°C 300 (VSON008X2030) Derate by 3.0mW/°C when operating above Ta=25°C 800 (DIP-T8) Derate by 8.0mW/°C when operating above Ta=25°C Storage Temperature Tstg -65 to +150 °C Operating Temperature Topr -40 to +85 °C -0.3 to Vcc+1.0 V The Max value of input voltage / output voltage is not over 6.5V. When the pulse width is 50ns or less the Min value of input voltage / output voltage is not lower than -0.8V. Tjmax 150 °C Junction temperature at the storage condition VESD -4000 to +4000 V Input Voltage/ Output Voltage Junction Temperature Electrostatic discharge voltage (human body model) Memory Cell Characteristics (Ta=25°C, Vcc=1.6V to 5.5V) Parameter Min 1,000,000 40 (1) Write Cycles Data Retention (1) Limit Typ - Max - Unit Times Years (1) Not 100% TESTED Recommended Operating Ratings Parameter Power Source Voltage Input Voltage Symbol VCC VIN Rating 1.6 to 5.5 0 to Vcc Unit V DC Characteristics Unless otherwise specified, Ta= -40°C to +85°C Vcc=1.6V to 5.5V Parameter Symbol Limit Unit Conditions Min Typ Max VIH1 0.7Vcc - Vcc+1.0 V Input Low Voltage1 VIL1 -0.3 (2) - +0.3Vcc V 1.7V Vcc 5.5V Input High Voltage2 VIH2 0.8Vcc - Vcc+1.0 V 1.6V Input Low Voltage2 VIL2 -0.3 (2) - +0.2Vcc V 1.6V Vcc 1.7V Output Low Voltage1 VOL1 - - 0.4 V IOL=3.0mA, 2.5V Vcc 5.5V (SDA) Output Low Voltage2 VOL2 - - 0.2 V IOL=0.7mA, 1.6V Vcc 2.5V (SDA) Input Leakage Current ILI -1 - +1 µA VIN=0 to Vcc Output Leakage Current ILO -1 - +1 µA Supply Current (Write) ICC1 - - 2.0 mA Supply Current (Read) ICC2 - - 0.5 mA Standby Current ISB - - 2.0 µA VOUT=0 to Vcc (SDA) Vcc=5.5V, fSCL=400kHz, tWR=5ms, Byte write, Page write Vcc=5.5V, fSCL=400kHz Random read, current read, sequential read Vcc=5.5V, SDA SCL=Vcc A0,A1,A2=GND,WP=GND Input High Voltage1 1.7V Vcc 5.5V Vcc 1.7V (2) When the pulse width is 50ns or less, it is -0.8V. www.rohm.com ©2013 ROHM Co., Ltd. All rights reserved. TSZ22111 15 001 2/35 TSZ02201-0R2R0G100100-1-2 31.Aug.2017 Rev.006 Datasheet BR24T08-W AC Characteristics (Unless otherwise specified, Ta= -40°C to +85°C, Vcc=1.6V to 5.5V) Parameter Limit Symbol Min Typ Max Unit Clock Frequency fSCL - - 400 kHz Data Clock High Period tHIGH 0.6 - - µs Data Clock Low Period tLOW 1.2 - - µs SDA,SCL(INPUT) Rise Time (1) tR - - 1.0 µs SDA,SCL (INPUT)Fall Time (1) tF1 - - 1.0 µs µs SDA(OUTPUT)Fall Time (1) tF2 - - 0.3 Start Condition Hold Time tHD:STA 0.6 - - µs Start Condition Setup Time tSU:STA 0.6 - - µs Input Data Hold Time tHD:DAT 0 - - ns Input Data Setup Time tSU:DAT 100 - - ns Output Data Delay Time tPD 0.1 - 0.9 µs Output Data Hold Time tDH 0.1 - - µs tSU:STO 0.6 - - µs Bus Free Time tBUF 1.2 - - µs Write Cycle Time tWR - - 5 ms Stop Condition Setup Time Noise Spike Width (SDA and SCL) tI - - 0.1 µs WP Hold Time tHD:WP 1.0 - - µs WP Setup Time tSU:WP 0.1 - - µs WP High Period tHIGH:WP 1.0 - - µs (1) Not 100% TESTED. Condition Input Data Level: VIL=0.2×Vcc VIH=0.8×Vcc Input Data Timing Reference Level: 0.3×Vcc/0.7×Vcc Output Data Timing Reference Level: 0.3×Vcc/0.7×Vcc Rise/Fall Time: 20ns Serial Input / Output Timing 70% DATA(n) DATA(1) D0 D1 ACK ACK 70% tWR (INPUT) 30% (OUTPUT ) tSU:WP Input read at the rise edge of SCL Data output in sync with the fall of SCL D1 tSU:STA tHD:STA DATA(n) DATA(1) 70% 70% tHD:WP Figure 2-(d). WP Timing at Write Execution Figure 2-(a). Serial Input / Output Timing 70% 30% tSU:STO D0 ACK ACK 70% tWR tHIGH:WP 70% 30% 70% 30% Figure 2-(b). Start-stop Bit Timing D0 ACK 70% Figure 2-(e). WP Timing at Write Cancel 70% 70% tWR (n-th address) Figure 2-(c). Write Cycle Timing www.rohm.com ©2013 ROHM Co., Ltd. All rights reserved. TSZ22111 15 001 3/35 TSZ02201-0R2R0G100100-1-2 31.Aug.2017 Rev.006 Datasheet BR24T08-W Block Diagram A0 1 8Kbit EEPROM Array 8 VCC 7 WP 6 SCL 5 SDA 8bit A1 2 Address Decoder 10bit Word Address Register START A2 3 Data Register STOP Control Circuit ACK GND 4 High Voltage Generating Circuit Power Source Voltage Detection Figure 3. Block Diagram Pin Configuration (TOP VIEW) A0 1 A1 2 8 Vcc 7 WP BR24T08-W A2 3 6 SCL GND 4 5 SDA Pin Descriptions Terminal Name Input/ Output A0 - Don’t use (1) A1 - Don’t use (1) A2 Input GND SCL Input/ Output Input WP Input VCC - SDA Descriptions Slave address setting (2) Reference voltage of all input / output, 0V Serial data input serial data output Serial clock input Write protect terminal Connect the power source (1) Pins not used as device address may be set to any of ‘H’, 'L', and 'Hi-Z' (2) A2 is not allowed to use as open.. www.rohm.com ©2013 ROHM Co., Ltd. All rights reserved. TSZ22111 15 001 4/35 TSZ02201-0R2R0G100100-1-2 31.Aug.2017 Rev.006 Datasheet BR24T08-W Typical Performance Curves 6 6 Ta=-40 Ta= 25 Ta= 85 5 Ta=-40 Ta= 25 Ta= 85 5 4 4 3 3 1PIN MARK SPEC 2 2 1 1 SPEC 0 0 0 1 2 3 4 5 0 6 1 2 3 4 5 6 Supply Voltage: Vcc(V) Supply Voltage: Vcc(V) Figure 4. Input High Voltage1,2 vs Supply Voltage (A2, SCL, SDA, WP) Figure 5. Input Low Voltage1,2 vs Supply Voltage (A2, SCL, SDA, WP) 1 1 Ta=-40 Ta= 25 Ta= 85 0.8 Ta=-40 Ta= 25 Ta= 85 0.8 0.6 0.6 SPEC 0.4 0.4 SPEC 0.2 0.2 0 0 0 1 2 3 4 5 0 6 1 2 3 4 5 6 Output Low Current: IOL(mA) Output Low Current: IOL(mA) Figure 6. Output Low Voltage1 vs Output Low Current (Vcc=2.5V) Figure 7. Output Low Voltage2 vs Output Low Current (Vcc=1.6V) www.rohm.com ©2013 ROHM Co., Ltd. All rights reserved. TSZ22111 15 001 5/35 TSZ02201-0R2R0G100100-1-2 31.Aug.2017 Rev.006 Datasheet BR24T08-W Typical Performance Curves continued 1.2 1.2 SPEC 1 Ta=-40 Ta= 25 Ta= 85 0.8 0.6 0.4 0.4 0.2 0.2 0 0 1 Ta=-40 Ta= 25 Ta= 85 0.8 0.6 0 SPEC 1 2 3 4 5 0 6 1 2 3 4 5 6 Supply Voltage: Vcc(V) Supply Voltage: Vcc(V) Figure 9. Output Leakage Current vs Supply Voltage (SDA) Figure 8. Input Leakage Current vs Supply Voltage (A2, SCL, WP) 3 0.6 2.5 0.5 SPEC 0.4 2 0.3 1.5 Ta=-40 Ta= 25 1 0.2 Ta= 85 0.5 0.1 0 0 0 1 2 3 4 5 0 6 2 3 4 5 6 Supply Voltage: Vcc(V) Supply Voltage: Vcc(V) Figure 11. Supply Current (Read) vs Supply Voltage (fSCL=400kHz) Figure 10. Supply Current (Write) vs Supply Voltage (fSCL=400kHz) www.rohm.com ©2013 ROHM Co., Ltd. All rights reserved. TSZ22111 15 001 1 6/35 TSZ02201-0R2R0G100100-1-2 31.Aug.2017 Rev.006 Datasheet BR24T08-W Typical Performance Curves continued 2.5 10000 2 1000 1.5 100 1 10 0.5 1 0 0.1 0 1 2 3 4 5 6 0 Supply Voltage: Vcc(V) 1 2 3 4 5 6 Supply Voltage: Vcc(V) Figure 12. Standby Current vs Supply Voltage Figure 13. Clock Frequency vs Supply Voltage 1 1.5 0.8 1.2 0.6 0.9 0.4 0.6 0.2 0.3 0 0 0 1 2 3 4 5 6 Supply Voltage: Vcc(V) Supply Voltage: Vcc(V) Figure 14. Data Clock High Period vs Supply Voltage www.rohm.com ©2013 ROHM Co., Ltd. All rights reserved. TSZ22111 15 001 Figure 15. Data Clock Low Period vs Supply Voltage 7/35 TSZ02201-0R2R0G100100-1-2 31.Aug.2017 Rev.006 Datasheet BR24T08-W Typical Performance Curves continued 1 1 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0 0 -0.2 -0.2 0 1 2 3 4 5 6 0 1 Supply Voltage: Vcc(V) 50 0 0 -50 -50 -100 -100 -150 -150 -200 -200 2 3 4 5 0 6 5 6 1 2 3 4 5 6 Supply Voltage: Vcc(V) Supply Voltage: Vcc(V) Figure 18. Input Data Hold Time vs Supply Voltage (HIGH) www.rohm.com ©2013 ROHM Co., Ltd. All rights reserved. TSZ22111 15 001 4 Figure 17. Start Condition Setup Time vs Supply Voltage 50 1 3 Supply Voltage: Vcc(V) Figure 16. Start Condition Hold Time vs Supply Voltage 0 2 Figure 19. Input Data Hold Time vs Supply Voltage (LOW) 8/35 TSZ02201-0R2R0G100100-1-2 31.Aug.2017 Rev.006 Datasheet BR24T08-W Typical Performance Curves continued 300 300 200 200 100 100 0 0 -100 -100 -200 -200 0 1 2 3 4 5 6 0 1 Supply Voltage: Vcc(V) 2 3 4 5 6 Supply Voltage: Vcc(V) Figure 21. Input Data Setup Time vs Supply Voltage (LOW) Figure 20. Input Data Setup Time vs Supply Voltage (HIGH) 2 2 1.5 1.5 1 1 0.5 0.5 0 0 0 1 2 3 4 5 6 0 Supply Voltage: Vcc(V) 2 3 4 5 6 Supply Voltage: Vcc(V) Figure 22. ‘L’ Output Data Delay Time vs Supply Voltage www.rohm.com ©2013 ROHM Co., Ltd. All rights reserved. TSZ22111 15 001 1 Figure 23. ‘H’ Output Data Delay Time vs Supply Voltage 9/35 TSZ02201-0R2R0G100100-1-2 31.Aug.2017 Rev.006 Datasheet BR24T08-W Typical Performance Curves continued 2 2 1.5 1.5 1 1 0.5 0.5 0 0 -0.5 0 1 2 3 4 5 6 Supply Voltage: Vcc(V) Supply Voltage: Vcc(V) Figure 25. Bus Free Time vs Supply Voltage Figure 24. Stop Condition Setup Time vs Supply Voltage 0.6 6 SPEC 5 0.5 4 0.4 3 0.3 2 0.2 Ta=-40 Ta= 25 Ta= 85 1 0.1 0 0 0 1 2 3 4 5 0 6 2 3 4 5 6 Supply Voltage: Vcc(V) Supply Voltage: Vcc(V) Figure 26. Write Cycle Time vs Supply Voltage www.rohm.com ©2013 ROHM Co., Ltd. All rights reserved. TSZ22111 15 001 1 Figure 27. Noise Spike Width vs Supply Voltage (SCL H) 10/35 TSZ02201-0R2R0G100100-1-2 31.Aug.2017 Rev.006 Datasheet BR24T08-W Typical Performance Curves continued 0.6 0.6 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.2 0.1 0.1 0 0 0 1 2 3 4 5 0 6 1 2 3 4 5 6 Supply Voltage: Vcc(V) Supply Voltage: Vcc(V) Figure 28. Noise Spike Width vs Supply Voltage (SCL L) Figure 29. Noise Spike Width vs Supply Voltage (SDA H) 0.6 1.2 0.5 1 0.4 0.8 0.3 0.6 0.2 0.4 0.1 0.2 0 0 0 1 2 3 4 5 6 0 Supply Voltage: Vcc(V) 2 3 4 5 6 Supply Voltage: Vcc(V) Figure 30. Noise Spike Width vs Supply Voltage (SDA L) www.rohm.com ©2013 ROHM Co., Ltd. All rights reserved. TSZ22111 15 001 1 Figure 31. WP Hold Time vs Supply Voltage 11/35 TSZ02201-0R2R0G100100-1-2 31.Aug.2017 Rev.006 Datasheet BR24T08-W Typical Performance Curves continued 0.2 1.2 0.1 1 0 0.8 -0.1 -0.2 0.6 -0.3 0.4 -0.4 0.2 -0.5 0 -0.6 0 1 2 3 4 5 6 Supply Voltage: Vcc(V) Supply Voltage: Vcc(V) Figure 33. WP High Period vs Supply Voltage Figure 32. WP Setup Time vs Supply Voltage www.rohm.com ©2013 ROHM Co., Ltd. All rights reserved. TSZ22111 15 001 12/35 TSZ02201-0R2R0G100100-1-2 31.Aug.2017 Rev.006 Datasheet BR24T08-W Timing Chart 1. I2C BUS Data Communication I2C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long, and acknowledge is always required after each byte. I2C BUS data communication with several devices is possible by connecting with 2 communication lines: serial data (SDA) and serial clock (SCL). Among the devices, there should be a “master” that generates clock and control communication start and end. The rest become “slave” which are controlled by an address peculiar to each device, like this EEPROM. The device that outputs data to the bus during data communication is called “transmitter”, and the device that receives data is called “receiver”.. Figure 34. Data Transfer Timing 2. Start Condition (Start Bit Recognition) (1) Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL is 'HIGH' is necessary. (2) This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this condition is satisfied, any command cannot be executed. 3. Stop Condition (Stop Bit Recognition) (1) Each command can be ended by a stop condition (stop bit) where SDA goes from 'LOW' to 'HIGH' while SCL is 'HIGH'. 4. Acknowledge (ACK) Signal (1) The acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In a master-slave communication, the device (Ex. µ-COM sends slave address input for write or read command, to this IC ) at the transmitter (sending) side releases the bus after output of 8bit data. (2) The device (Ex. This IC receives the slave address input for write or read command from the µ-COM) at the receiver (receiving) side sets SDA 'LOW' during the 9th clock cycle, and outputs acknowledge signal (ACK signal) showing that it has received the 8bit data. (3) This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) 'LOW'. (4) After receiving 8bit data (word address and write data) during each write operation, this IC outputs acknowledge signal (ACK signal) 'LOW'. (5) During read operation, this IC outputs 8bit data (read data) and detects acknowledge signal (ACK signal) 'LOW'. When acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (µ-COM) side, this IC continues to output data. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, recognizes stop condition (stop bit), and ends read operation. Then this IC becomes ready for another transmission. 5. Device Addressing (1) Slave address comes after start condition from master. (2) The significant 4 bits of slave address are used for recognizing a device type. The device code of this IC is fixed to '1010'. (3) Next slave addresses (A2 --- device address) are for selecting devices, and plural ones can be used on a same bus according to the number of device addresses. (4) The most insignificant bit ( R / W --- READ / WRITE ) of slave address is used for designating write or read operation, and is as shown below. Setting R / W to 0 ------- write (setting 0 to word address setting of random read) Setting R / W to 1 ------- read Slave Address 1 0 1 0 A2 P1 P0 R/W P0 and P1 are page select bits. www.rohm.com ©2013 ROHM Co., Ltd. All rights reserved. TSZ22111 15 001 Maximum Number of Connected Buses 2 13/35 TSZ02201-0R2R0G100100-1-2 31.Aug.2017 Rev.006 Datasheet BR24T08-W Write Command 1. Write Cycle (1) Arbitrary data can be written to this EEPROM. When writing only 1 byte, Byte Write is normally used, and when writing continuous data of 2 bytes or more, simultaneous write is possible by Page Write cycle. The maximum number of bytes is specified per device of each capacity. Up to 8 arbitrary bytes can be written. S T A R T SDA LINE SLAVE ADDRESS W R I T E WORD ADDRESS WA 7 1 0 1 0 A2 P1 P0 S T O P DATA WA 0 D0 D7 A C K R A / C W K A C K Figure 35. Byte Write Cycle S T A R T SDA LINE SLAVE ADDRESS 1 0 1 W R I T E WORD ADDRESS(n) WA 7 0 A2 P1P0 R A / C W K WA 0 D7 A C K S T O P DATA(n+15) DATA(n) D0 D0 A C K A C K Figure 36. Page Write Cycle (2) (3) (4) (5) (6) During internal write execution, all input commands are ignored, therefore ACK is not returned. Data is written to the address designated by word address (n-th address) By issuing stop bit after 8bit data input, internal write to memory cell starts. When internal write is started, command is not accepted for tWR (5ms at maximum). Using page write cycle, writing in bulk is done as follows: When data of more than 16 bytes is sent, the bytes in excess overwrite the data already sent first. (Refer to "Internal address increment") (7) As for page write command BR24T08-W, where 2 or more bytes of data is intended to be written, after the page select bits ‘P0’, and ‘P1’ of slave address are designated arbitrarily, only the value of 4 least significant bits in the address is incremented internally, so that data up to 16 bytes of memory only can be written. In the case BR24T08-W, 1 page=16bytes, but the page write cycle time is 5ms at maximum for 16byte bulk write. It does not stand 5ms at maximum 16byte=80ms (Max) . 2. Internal Address Increment Page write mode (in the case of BR24T08-W) For example, when it is started from address 0Eh, then, increment is made as below, please take note. 0Eh 0Fh 00h 01h 0Eh 0E in hexadecimal, therefore, 00001110 becomes a binary number. 3. Write Protect (WP) Terminal Write Protect (WP) Function When WP terminal is set at Vcc (H level), data rewrite of all addresses is prohibited. When it is set at GND (L level), data rewrite of all address is enabled. Be sure to connect this terminal to Vcc or GND, or control it to H level or L level. Do not use it open. In case of using it as ROM, it is recommended to connect it to pull up or Vcc. At extremely low voltage at power ON / OFF, by setting the WP terminal 'H', write error can be prevented. www.rohm.com ©2013 ROHM Co., Ltd. All rights reserved. TSZ22111 15 001 14/35 TSZ02201-0R2R0G100100-1-2 31.Aug.2017 Rev.006 Datasheet BR24T08-W Read Command 1. Read Cycle Read cycle is when data of EEPROM is read. Read cycle could be random read cycle or current read cycle. Random read cycle is a command to read data by designating a specific address, and is used generally. Current read cycle is a command to read data of internal address register without designating an address, and is used when to verify just after write cycle. In both the read cycles, sequential read cycle is available where the next address data can be read in succession. S T A R T SDA LINE SLAVE ADDRESS W R I T E S T A R T WORD ADDRESS(n) WA 7 1 0 1 0 A2P1P0 WA 0 RA / C WK R E A D SLAVE ADDRESS 1 0 1 0 A2A1A0 A C K S T O P DATA(n) D0 D7 A C K R A / C WK Figure 37. Random Read Cycle S T A R T SDA LINE R E A D SLAVE ADDRESS 1 0 1 0 A2P1P0 S T O P DATA(n) D7 D0 A C K R A / C WK Figure 38. Current Read Cycle S T A R T SDA LINE SLAVE ADDRESS R E A D 1 0 1 0 A2 P1P0 DATA(n) D7 R A / C WK S T O P DATA(n+x) D7 D0 A C K A C K D0 A C K Figure 39. Sequential Read Cycle (in the case of current read cycle) (1) In random read cycle, data of designated word address can be read. (2) When the command just before current read cycle is random read cycle, current read cycle (each including sequential read cycle), data of incremented last read address (n)-th, i.e., data of the (n+1)-th address is output. (3) When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (µ-COM) side, the next address data can be read in succession. (4) Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal goes from ‘L’ to ‘H’ while SCL signal is 'H'. (5) When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output. Therefore, read command cycle cannot be ended. To end read command cycle, be sure to input 'H' to ACK signal after D0, and the stop condition where SDA goes from ‘L’ to ‘H’ while SCL signal is 'H'. (6) Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is asserted from ‘L’ to ‘H’ while SCL signal is 'H'. www.rohm.com ©2013 ROHM Co., Ltd. All rights reserved. TSZ22111 15 001 15/35 TSZ02201-0R2R0G100100-1-2 31.Aug.2017 Rev.006 Datasheet BR24T08-W Software Reset Software reset is executed to avoid malfunction after power on and during command input. Software reset has several kinds and 3 kinds of them are shown in the figure below. (Refer to Figure 40-(a), Figure 40-(b), and Figure 40-(c).) Within the dummy clock input area, the SDA bus is released ('H' by pull up) and ACK output and read data '0' (both 'L' level) may be output from EEPROM. Therefore, if 'H' is input forcibly, output may conflict and over current may flow, leading to instantaneous power failure of system power source or influence upon devices. Dummy clock×14 SCL 1 2 Start×2 13 Normal command 14 SDA Normal command Figure 40-(a). The Case of Dummy Clock×14 + START+START+ Command Input Dummy clock Start SCL 1 Start 9 2 8 Normal command 9 SDA Normal command Figure 40-(b). The Case of START + Dummy Clock×9 + START + Command Input Start SCL 1 2 9 3 7 8 Normal command 9 SDA Normal command SD Figure 40-(c). START×9 + Command Input Start command from START input. Acknowledge Polling During internal write execution, all input commands are ignored, therefore ACK is not returned. During internal automatic write execution after write cycle input, next command (slave address) is sent. If the first ACK signal sends back 'L', then it means end of write operation, else 'H' is returned, which means writing is still in progress. By the use of acknowledge polling, next command can be executed without waiting for tWR = 5ms. To write continuously, R / W = 0, then to carry out current read cycle after write, slave address with R / W = 1 is sent. If ACK signal sends back 'L', and then execute word address input and data output and so forth.. During internal write, ACK = HIGH is returned. First write command S T A R T Write Command S T O P S T Slave A R Address T S T Slave A R Address T A C K H A C K H tWR Second Write Command S T Slave A R Address T A C K H S T Slave A R Address T A C K L Word Address A C K L Data A C K L S T O P tWR After completion of internal write, ACK=LOW is returned, so input next word address and data in succession. Figure 41. Case of Continuous Write by Acknowledge Polling www.rohm.com ©2013 ROHM Co., Ltd. All rights reserved. TSZ22111 15 001 16/35 TSZ02201-0R2R0G100100-1-2 31.Aug.2017 Rev.006 Datasheet BR24T08-W WP Valid Timing (Write Cancel) WP is usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so on, pay attention to the following WP valid timing. During write cycle execution, inside cancel valid area, by setting WP='H', write cycle can be cancelled. In both byte write cycle and page write cycle, the area from the first start condition of command to the rise of clock to take in D0 of data(in page write cycle, the first byte data) is the cancel invalid area. WP input in this area becomes ‘Don't care’. The area from the rise of SCL to take in D0 to the stop condition input is the cancel valid area. Furthermore, after the execution of forced end by WP, the IC enters standby status. Rise of SDA Rise of D0 taken clock SCL SDA SCL D1 D0 ACK SDA SDA S T Slave A R Address T A C Word K Address L D0 ACK Enlarged view Enlarged view A C D7 D6 D5 D4 D3 D2 D1 D0 K L WP cancel invalid area A C K L Data A C K L S T O P WP cancel valid area tWR WP cancel invalid area WP Data is not written. Figure 42. WP Valid Timing Command Cancel by Start Condition and Stop Condition During command input, by continuously inputting start condition and stop condition, command can be cancelled. (Figure 43.) However, within ACK output area and during data read, SDA bus may output 'L'. In this case, start condition and stop condition cannot be input, so reset is not available. Therefore, execute software reset. When command is cancelled by start-stop condition during random read cycle, sequential read cycle, or current read cycle, internal setting address is not determined. Therefore, it is not possible to carry out current read cycle in succession. To carry out read cycle in succession, carry out random read cycle. SCL SDA 1 0 1 0 Start condition Stop condition Figure 43. Case of Cancel by Start, Stop Condition during Slave Address Input www.rohm.com ©2013 ROHM Co., Ltd. All rights reserved. TSZ22111 15 001 17/35 TSZ02201-0R2R0G100100-1-2 31.Aug.2017 Rev.006 Datasheet BR24T08-W I/O Peripheral Circuit 1. Pull-up Resistance of SDA Terminal SDA is NMOS open drain, so it requires a pull up resistor. As for this resistance value (R PU), select an appropriate value from microcontroller VIL, IL, and VOL-IOL characteristics of this IC. If RPU is large, operating frequency is limited. The smaller the RPU, the larger is the supply current (Read). 2. Maximum Value of RPU The maximum value of RPU is determined by the following factors. (1) SDA rise time to be determined by the capacitance (CBUS) of bus line and RPU of SDA should be tR or lower. Furthermore, AC timing should be satisfied even when SDA rise time is slow. (2) The bus. electric potential A to be determined by the input current leak total (IL) of device connected to bus at output of 'H' to the SDA line and RPU should sufficiently secure the input 'H' level (VIH) of microcontroller and EEPROM including recommended noise margin of 0.2Vcc. VCC ILRPU 0.2 Vcc 0.8Vcc IL RPU VIH VIH Microcontroller BR24TXX RPU Ex.) Vcc =3V IL=10µA VIH=0.7 Vcc From (2) 0.8 3 0.7 3 RPU 10 10-6 SDA terminal A IL IL 30 [k ] Bus Line Capacity CBUS Figure 44. I/O Circuit Diagram 3. Minimum Value of RPU The minimum value of RPU is determined by the following factors. (1) When IC outputs LOW, it should be satisfied that VOLMAX=0.4V and IOLMAX=3mA. Vcc VOL IOL RPU Vcc VOL RPU IOL (2) VOLMAX=0.4V should secure the input 'L' level (VIL) of microcontroller and EEPROM including recommended noise margin 0.1Vcc. VOLMAX VIL-0.1 Vcc Ex.) Vcc =3V, VOL=0.4V, IOL=3mA, microcontroller, EEPROM VIL=0.3Vcc from (1) 3 0.4 RPU 3 10 3 867[ ] And VOL=0.4 [V] VIL=0.3×3 =0.9 [V] Therefore, the condition (2) is satisfied. 4. Pull-up Resistance of SCL Terminal When SCL control is made at the CMOS output port, there is no need for a pull up resistor. But when there is a time where SCL becomes 'Hi-Z', add a pull up resistor. As for the pull up resistor value, one of several k to several ten k is recommended in consideration of drive performance of output port of microcontroller. www.rohm.com ©2013 ROHM Co., Ltd. All rights reserved. TSZ22111 15 001 18/35 TSZ02201-0R2R0G100100-1-2 31.Aug.2017 Rev.006 Datasheet BR24T08-W Cautions on Microcontroller Connection 1. RS In I2C BUS, it is recommended that SDA port is of open drain input/output. However, when using CMOS input / output of tri state to SDA port, insert a series resistance RS between the pull up resistor RPU and the SDA terminal of EEPROM. This is to control over current that may occur when PMOS of the microcontroller and NMOS of EEPROM are turned ON simultaneously. RS also plays the role of protecting the SDA terminal against surge. Therefore, even when SDA port is open drain input/output, RS can be used. ACK SCL RPU RS SDA 'H' output of microcontroller Microcontroller EEPROM 'L' output of EEPROM Over current flows to SDA line by 'H' output of microcontroller and 'L' output of EEPROM. Figure 45. I/O Circuit Diagram Figure 46. Input / Output Collision Timing 2. Maximum Value of RS The maximum value of RS is determined by the following relations. (1) SDA rise time to be determined by the capacitance (CBUS) of bus line and RPU of SDA should be tR or lower. Furthermore, AC timing should be satisfied even when SDA rise time is slow. (2) The bus’ electric potential A to be determined by RPU and RS the moment when EEPROM outputs 'L' to SDA bus should sufficiently secure the input 'L' level (VIL) of microcontroller including recommended noise margin of 0.1Vcc. (Vcc VOL) RS +VOL+0.1Vcc VIL RPU+RS VCC RPU A RS VOL IOL 0.3 3 0.4 0.1 3 1.1 3 0.3 3 RS EEPROM Micro controller RPU Ex.) VCC=3V VIL=0.3Vcc VOL=0.4V Bus line capacity CBUS VIL VIL VOL 0.1Vcc 1.1Vcc VIL RS 20 RPU=20k 103 1.67 [k ] Figure 47. I/O Circuit Diagram 3. Minimum Value of RS The minimum value of RS is determined by over current at bus collision. When over current flows, noises in power source line and instantaneous power failure of power source may occur. When allowable over current is defined as I, the following relation must be satisfied. Determine the allowable current in consideration of the impedance of power source line in set and so forth. Set the over current to EEPROM at 10mA or lower. Vcc RS RPU RS I RS 'L'output Vcc I Ex.) VCC=3V I=10mA Over current I RS 'H' output 3 10 10 3 300 [ ] Microcontroller EEPROM Figure 48. I/O Circuit Diagram www.rohm.com ©2013 ROHM Co., Ltd. All rights reserved. TSZ22111 15 001 19/35 TSZ02201-0R2R0G100100-1-2 31.Aug.2017 Rev.006 Datasheet BR24T08-W I/O Equivalence Circuit 1. Input (A2, SCL, WP) Figure 49. Input Pin Circuit Diagram 2. Input / Output (SDA) Figure 50. Input / Output Pin Circuit Diagram www.rohm.com ©2013 ROHM Co., Ltd. All rights reserved. TSZ22111 15 001 20/35 TSZ02201-0R2R0G100100-1-2 31.Aug.2017 Rev.006 Datasheet BR24T08-W Power-Up / Down Conditions At power ON, the IC’s internal circuits may go through unstable low voltage area as the Vcc rises, making the IC’s internal logic circuit not completely reset, hence, malfunction may occur. To prevent this, the IC is equipped with POR circuit and LVCC circuit. To assure the operation, observe the following conditions at power ON. 1. Set SDA = 'H' and SCL ='L' or 'H’ 2. Start power source so as to satisfy the recommended conditions of t R, tOFF, and Vbot for operating POR circuit. tR VCC Recommended conditions of tR, tOFF,Vbot tR tOFF Vbot 0 tOFF Vbot 10ms or below 10ms or larger 0.3V or below 100ms or below 10ms or larger 0.2V or below Figure 51. Rise Waveform Diagram 3. Set SDA and SCL so as not to become 'Hi-Z'. When the above conditions 1 and 2 cannot be observed, take the following countermeasures. (1) In the case when the above condition 1 cannot be observed such that SDA becomes 'L' at power ON. Control SCL and SDA as shown below, to make SCL and SDA, 'H' and 'H'. VCC tLOW SCL SDA After Vcc becomes stable After Vcc becomes stable tDH tSU:DAT tSU:DAT Figure 52. When SCL= 'H' and SDA= 'L' Figure 53. When SCL='L' and SDA='L' (2) In the case when the above condition 2 cannot be observed. After power source becomes stable, execute software reset (PAGE 16). (3) In the case when the above conditions 1 and 2 cannot be observed. Carry out (1), and then carry out (2). Low Voltage Malfunction Prevention Function LVCC circuit prevents data rewrite operation at low power, and prevents write error. At LVCC voltage (Typ =1.2V) or below, data rewrite is prevented. Noise Countermeasures 1. Bypass Capacitor When noise or surge gets in the power source line, malfunction may occur, therefore, it is recommended to connect a bypass capacitor (0.1µF) between IC Vcc and GND pins. Connect the capacitor as close to IC as possible. In addition, it is also recommended to connect a bypass capacitor between board’s Vcc and GND. www.rohm.com ©2013 ROHM Co., Ltd. All rights reserved. TSZ22111 15 001 21/35 TSZ02201-0R2R0G100100-1-2 31.Aug.2017 Rev.006 Datasheet BR24T08-W Operational Notes 1. Described numeric values and data are design representative values only, and the values are not guaranteed. 2. We believe that the application circuit examples in this document are recommendable. However, in actual use, confirm characteristics further sufficiently. If changing the fixed number of external parts is desired, make your decision with sufficient margin in consideration of static characteristics, transient characteristics, and fluctuations of external parts and our LSI. 3. Absolute maximum ratings If the absolute maximum ratings such as supply voltage, operating temperature range, and so on are exceeded, LSI may be destroyed. Do not supply voltage or subject the IC to temperatures exceeding the absolute maximum ratings. In the case of fear of exceeding the absolute maximum ratings, take physical safety countermeasures such as adding fuses, and see to it that conditions exceeding the absolute maximum ratings should not be supplied to the LSI. 4. GND electric potential Set the voltage of GND terminal lowest at any operating condition. Make sure that each terminal voltage is not lower than that of GND terminal. 5. Thermal design Use a thermal design that allows for a sufficient margin by taking into account the permissible power dissipation (Pd) in actual operating conditions. 6. Short between pins and mounting errors Be careful when mounting the IC on printed circuit boards. The IC may be damaged if it is mounted in a wrong orientation or if pins are shorted together. Short circuit may be caused by conductive particles caught between the pins. 7. Operating the IC in the presence of strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently. www.rohm.com ©2013 ROHM Co., Ltd. All rights reserved. TSZ22111 15 001 22/35 TSZ02201-0R2R0G100100-1-2 31.Aug.2017 Rev.006 Datasheet BR24T08-W Part Numbering B R 2 4 T 0 8 x x x - W xxx xx BUS Type 24 I2C Operating Temperature/ Power Source Voltage -40 to+85 / 1.6V to 5.5V Capacity 08=8K Package Blank :DIP-T8 F :SOP8 FJ :SOP-J8 (-WE2) / SOP-J8A ( -WSGNE2 ) FV : SSOP-B8 FVT : TSSOP-B8 FVJ : TSSOP-B8J FVM : MSOP8 NUX : VSON008X2030 Double Cell SGN : SOP-J8A Packaging and Forming Specification E2 : Embossed tape and reel (SOP8,SOP-J8,SOP-J8A,SSOP-B8,TSSOP-B8,TSSOP-B8J) TR : Embossed tape and reel (MSOP8, VSON008X2030) None : Tube (DIP-T8) www.rohm.com ©2013 ROHM Co., Ltd. All rights reserved. TSZ22111 15 001 23/35 TSZ02201-0R2R0G100100-1-2 31.Aug.2017 Rev.006 Datasheet BR24T08-W Physical Dimensions Tape and Reel Information DIP-T8 •      •  • ”n” 9RMXQQ 8ETIERH6IIPMRJSVQEXMSR" 'SRXEMRIV 8YFI 5YERXMX] TGW (MVIGXMSRSJJIIH (MVIGXMSRSJTVSHYGXWMWJM\IHMREGSRXEMRIVXYFI 3VHIVUYERXMX]RIIHWXSFIQYPXMTPISJXLIQMRMQYQUYERXMX] www.rohm.com ©2013 ROHM Co., Ltd. All rights reserved. TSZ22111 15 001 24/35 TSZ02201-0R2R0G100100-1-2 31.Aug.2017 Rev.006 Datasheet BR24T08-W SOP8 • 1%