BR25H320F-W

TECHNICAL NOTE HIGH GRADE Specification HIGH RELIABILITY series SPI BUS Serial EEPROMs ☆ Supply voltage 2.5V~5.5V Operating temperature -40°C ~ +125°C type ☆ : Under development ●Description BR25H□□□-W series is a serial EEPROM of SPI BUS interface method. BR25H010-W, BR25H020-W, BR25H040-W, BR25H080-W, BR25H160-W, BR25H320-W ☆ ●Features ● High speed clock action up to 5MHz (Max.) ● Wait function by HOLDB terminal. ● Part or whole of memory arrays settable as read only memory area by program. ● 2.5～5.5V single power source action most suitable for battery use. ● Page write mode useful for initial value write at factory shipment. ● Highly reliable connection by Au pad and Au wire. ● For SPI bus interface (CPOL, CPHA)=(0, 0), (1, 1) ● Auto erase and auto end function at data rewrite. ●Page write ● Low current consumption Number of pages At write action (5V) : 1.5mA (Typ.) At read action (5V) : 1.0mA (Typ.) Product At standby action (5V) : 0.1μA (Typ.) number ● Address auto increment function at read action ● Write mistake prevention function Write prohibition at power on. Write prohibition by command code (WRDI). Write prohibition by WPB pin. Write prohibition block setting by status registers (BP1, BP0) Write mistake prevention function at low voltage. ● SOP8, SOP-J8 Package ● Data at shipment Memory array: FFh, status register WPEN, BP1, BP0 : 0 ● Data kept for 40 years. ● Data rewrite up to 1,000,000times. 16 Byte BR25H010-W BR25H020-W BR25H040-W 32 Byte BR25H080-W BR25H160-W BR25H320-W ●BR25H series Capacity 1Kbit 2Kbit 4Kbit 8Kbit 16Kbit 32Kbit Bit format 128×8 256×8 512×8 1K×8 2K×8 4Kx8 Type BR25H010-W BR25H020-W BR25H040-W BR25H080-W BR25H160-W BR25H320-W Power source voltage 2.5~5.5V 2.5~5.5V 2.5~5.5V 2.5~5.5V 2.5~5.5V 2.5~5.5V SOP8 ● ● ● ● ● ● SOP-J8 ● ● ● ● ● ● Ver A. Aug. 2007 ●Absolute maximum ratings (Ta=25°C) Parameter Impressed voltage Permissible dissipation Storage temperature range Operating temperature range Terminal voltage ●Recommended action conditions Unit Parameter Symbol Limits Unit Symbol Limits Vcc Pd Tstg Topr – -0.3~+6.5 450(SOP8) 450(SOP-J8) -65~150 -40~125 -0.3~Vcc+0.3 V *1 *2 mW °C °C V Power source voltage Input voltage Vcc Vin 2.5~5.5 0~Vcc V ●Input / output capacity (Ta=25°C, frequency=5MHz) Parameter Input capacity Output capacity ж1 ж1 Symbol Conditions VIN=GND VOUT=GND Min. Max. Unit ・When using at Ta=25℃ or higher, 3.6mW (*1,*2) to be reduced per 1℃ CIN COUT – – 8 8 pF ●Memory cell characteristics (Vcc=2.5V～5.5V) Parameter Number of data rewrite times ж1 Data hold years ж1 *1: Not 100% TESTED Limits Min Typ. 1,000,000 500,000 300,000 40 20 - Max - Unit Times Times Times Years Years ж Condition Ta≤85℃ Ta≤105℃ Ta≤125℃ Ta≤25°C Ta≤85°C 1:Not 100% TESTED ●Electrical characteristics (Unless otherwise specified, Ta=-40~+125°C, Vcc=2.5~5.5V) Parameter “H” input voltage “L” output voltage “L” output voltage “H” output voltage Input leak current Output lead current Symbol VIH VIL VOL VOH ILI ILO ICC1 Current consumption at write action ICC2 – – 3.0 mA Min. 0.7x Vcc -0.3 0 Vcc -0.5 -10 -10 – Limits Typ. Max. Vcc – +0.3 0.3x – Vcc – 0.4 – – – – Vcc 10 10 2.0 Unit V V V V μA μA mA 2.5≤Vcc≤5.5V 2.5≤Vcc≤5.5V IOL=2.1mA IOH=-0.4mA VIN=0~Vcc VOUT=0~Vcc, CSB=Vcc Vcc=2.5V,fSCK=5MHz, tE/W=5ms VIH/VIL=0.9Vcc/0.1Vcc, Byte write, Page write Write status regisuter Vcc=5.5V,fSCK=5MHz, tE/W=5ms VIH/VIL=0.9Vcc/0.1Vcc Byte write, Page write Write status register Vcc=2.5V,fSCK=5MHz VIH/VIL=0.9Vcc/0.1Vcc, Read, Read status register Vcc=5.5V,fSCK=5MHz VIH/VIL=0.9Vcc/0.1Vcc Read, Read status register Vcc=5.5V CSB=HOLDB=WPB=Vcc, SCK=SI=Vcc or =GND, SO=OPEN ・Radiation resistance design is not made Conditions ICC3 Current consumption at read action ICC4 Standby current ISB – – 1.5 mA – – – – 2.0 10 mA μA ●Block diagram CSB SCK VOLTAGE INSTRUCTION DECODE CONTROL CLOCK GENERATION W RITE INHIBITION HIGH VOLTAGE GENERATOR DETECTION *1 SI HOLDB INSTRUCTION REGISTER ADDRESS REGISTER 7～12bit *1 STATUS REGISTER ADDRESS DECODER READ/WRITE AMP 7～12bit *1 1～32K EEPROM 7bit: BR25H010-W 8bit: BR25H020-W 9bit: BR25H040-W 10bit: BR25H080-W 11bit: BR25H160-W 12bit: BR25H320-W WPB SO DATA REGISTER 8bit 8bit Fig.1 Block diagram 2/16 ●Pin assignment and description Vcc HOLDB SCK SI BR25H010-W BR25H020-W BR25H040-W BR25H080-W BR25H160-W BR25H320-W Terminal name Vcc GND CSB SCK SI SO HOLDB Input/Output – – Input Input Input Output Input Function Power source to be connected All input / output reference voltage, 0V Chip select input Serial clock input Start bit, ope code, address, and serial data input Serial data output Hold input Command communications may be suspended temporarily (HOLD status) CSB SO WPB GND WPB Input Fig.2 Pin assignment diagram Write protect input Write command is prohibited *1 Write status register command is prohibited. *1:BR25H010/020/040-W ●Operating timing characteristics (Ta=-40~+125°C, unless otherwise specified, load capacity CL1=100pF) 2.5≤Vcc≤5.5V Parameter Symbol Unit Min. Typ. Max SCK frequency fSCK – – 5 MHz SCK high time 85 – – ns tSCKWH SCK low time 85 – – ns tSCKWL CSB high time tCS 85 – – ns CSB setup time tCSS 90 – – ns CSB hold time tCSH 85 – – ns SCK setup time 90 – – ns tSCKS SCK hold time 90 – – ns tSCKH SI setup time tDIS 20 – – ns SI hold time tDIH 30 – – ns tPD1 – – 70 ns Data output delay time1 Data output delay time1 ● Sync data input / output timing tCS tCSS CSB tSCKS tSCKWL tSCKWH tRC tFC SCK tDIS tDIH SI SO High-Z Fig.3 Input timing SI is taken into IC inside in sync with data rise edge of SCK. Input address and data from the most significant bit MSB. tCS CSB SCK SI tPD tCSH tSCKH (CL2=30pF) Output hold time Output disable time HOLDB setting setup time HOLDB setting hold time HOLDB release setup time HOLDB release hold time Time from HOLDB to output High-Z Time from HOLDB To output change SCK rise time SCK fall time OUTPUT rise time OUTPUT fall time Write time tPD2 tOH tOZ tHFS tHFH tHRS tHRH tHOZ tHPD – 0 – 0 40 0 70 – – – – – – – Ж – – – – – – – – – – – – – – 55 – 100 – – – – 100 70 1 1 50 50 5 ns ns ns ns ns ns ns ns ns μs μs ns ns ms tOH tRO,tFO tOZ SO High-Z Fig.4 Input / Output timing SO is output in sync with data fall edge of SCK. Data is output from the most significant bit MSB. CSB "H" "L" tHFS tHFH tHRS tHRH SCK tDIS SI n+1 tHOZ High-Z tHPD n n-1 SO Dn+1 Dn Dn Dn-1 HOLDB Ж Ж Ж 1 1 1 tRC tFC tRO tFO tE/W Fig.5 HOLD timing Ж 1 1 NOT 100% TESTED ●AC measurement conditions Parameter Load capacity 1 Load capacity 2 Input rise time Input fall time Input voltage Input / Output judgment voltage Symbol CL1 CL2 – – – – Limits Min. Typ. Max – – 100 – – 30 – – 50 – – 50 0.2Vcc/0.8Vcc 0.3Vcc/0.7Vcc 3/16 Unit pF pF ns ns V V ●Characteristic data (The following characteristic data are Typ. Values.) 6 5 4 VIH[V] 3 2 1 0 0 1 2 3 Vcc[V] 4 5 6 6 1 Ta=-40℃ Ta=25℃ Ta=125℃ VIL[V] 5 4 Ta=-40℃ Ta=25℃ Ta=125℃ VOL[V] 0.8 0.6 Ta=-40℃ Ta=25℃ Ta=125℃ SPEC 3 2 1 0 0 1 2 3 Vcc[V] 4 5 6 SPEC 0.4 0.2 SPEC 0 0 1 2 3 IOL[mA] 4 5 6 Fig.6 　"H" input voltage　VIH(CSB,SCK,SI,HOLDB,WPB) 2.6 2.5 2.4 2.3 VOH[V] 2.2 2.1 2 1.9 1.8 0 0.4 IOH[mA] 0.8 1.2 ILI[μA] 8 6 4 2 0 12 Fig.7 　"L" input voltage　VIL(CSB,SCK,SI,HOLDB,WPB) 12 Fig.8　"L" output voltage　VOL-IOL(Vcc=2.5V) SPEC 10 10 SPEC Ta=-40℃ Ta=25℃ Ta=125℃ ILO[μA] 2 3 Vcc[V] 4 5 6 Ta=-40℃ Ta=25℃ Ta=125℃ 8 6 4 2 0 SPEC Ta=-40℃ Ta=25℃ Ta=125℃ 0 1 0 1 2 3 VOUT[V] 4 5 6 Fig.9　"H" output voltage VOH-IOH(Vcc=2.5V) 4 Fig.10　Input leak current ILI(CSB,SCK,SI,HOLDB,WPB) 2.5 12 Fig.11　Output leak current ILO(SO)(Vcc=5.5V) ICC3,4(READ)[mA] 3 ICC1,2[mA]] fSCK=5MHz DATA=00h SPEC SPEC 2 1.5 1 0.5 fSCK=5MHz DATA=AAh SPEC SPEC 10 8 ISB[μA] 6 4 2 0 SPEC Ta=-40℃ Ta=25℃ Ta=125℃ 2 1 Ta=-40℃ Ta=25℃ Ta=125℃ Ta=-40℃ Ta=25℃ Ta=125℃ 0 0 1 2 3 Vcc[V] 4 5 6 0 0 1 2 3 Vcc[V] 4 5 6 0 1 2 3 Vcc[V] 4 5 6 Fig.12　Current consumption at WRITE operation ICC1,2 100 Fig.13　Consumption Current at READ operation ICC3,4 100 80 tSCKWH [ns] 100 Fig.14　Consumption current at standby operation ISB SPEC tSCKWL [ns] 80 SPEC Ta=-40℃ Ta=25℃ Ta=125℃ 10 fSCK[MHz] 60 40 20 0 SPEC 1 Ta=-40℃ Ta=25℃ Ta=125℃ 60 Ta=-40℃ Ta=25℃ Ta=125℃ 40 20 0.1 0 1 2 3 Vcc[V] 4 5 6 0 0 1 2 3 Vcc[V] 4 5 6 0 1 2 3 Vcc[V] 4 5 6 Fig.15　SCK frequency fSCK 100 100 Fig.16 SCK high time　tSCKWH 100 Fig.17 SCK low time　tSCKWL 80 SPEC tCSS[ns] 80 SPEC tCSH[ns] 80 tCS[ns] 60 Ta=-40℃ Ta=25℃ Ta=125℃ 60 Ta=-40℃ Ta=25℃ Ta=125℃ SPEC Ta=-40℃ Ta=25℃ Ta=125℃ 60 40 40 40 20 20 20 0 0 1 2 3 Vcc[V] 4 5 6 0 0 1 2 3 Vcc[V] 4 5 6 0 0 1 2 3 Vcc[V] 4 5 6 Fig.18 CSB high time　tCS Fig.19　CSB setup time　tCSS Fig.20　CSB hold time　tCSH 4/16 30 50 100 20 Ta=-40℃ Ta=25℃ Ta=125℃ 40 Ta=-40℃ Ta=25℃ Ta=125℃ tPD1 [ns] 80 SPEC SPEC tDIH[ns] 30 tDIS[ns] 10 SPEC 60 0 20 40 -10 10 20 Ta=-40℃ Ta=25℃ Ta=125℃ -20 0 1 2 3 Vcc[V] 4 5 6 0 0 1 2 3 Vcc[V] 4 5 6 0 0 1 2 Fig.21　SI setup time　tDIS 100 120 Fig.22　SI hold time　tDIH 3 Vcc[V] 4 5 6 Fig.23　Data output delay time　tPD1(CL=100pF) 80 80 Ta=-40℃ Ta=25℃ Ta=125℃ 100 SPEC 60 SPEC tOZ [ns] 80 60 40 Ta=-40℃ Ta=25℃ Ta=125℃ tHFH [ns] tPD2 [ns] 60 Ta=-40℃ Ta=25℃ Ta=125℃ 40 SPEC 20 40 20 20 0 0 1 2 3 Vcc[V] 4 5 6 0 1 2 3 Vcc[V] 4 5 6 0 0 -20 0 1 2 3 Vcc[V] 4 5 6 Fig.24　Data output delay time tPD2(CL-30pF) 80 120 100 Fig.25　Output disable time tOZ 80 Fig.26　HOLDB setting hold time tHFH 60 tHOZ [ns] 60 40 tHPD [ns] tHRH [ns] 40 Ta=-40℃ Ta=25℃ Ta=125℃ 60 SPEC 80 SPEC 40 SPEC 20 20 0 20 0 0 1 2 3 Vcc[V] 4 5 6 0 Ta=-40℃ Ta=25℃ Ta=125℃ 0 Ta=-40℃ Ta=25℃ Ta=125℃ -20 -20 1 2 3 Vcc[V] 4 5 6 0 1 2 3 Vcc[V] 4 5 6 Fig.27　HOLDB release hold time tHRH 100 Fig.28　Time from HOLDB to output High-Z tHOZ 100 Fig.29　Time from HOLDB to output change tHPD 8 80 Ta=-40℃ Ta=25℃ Ta=125℃ tFO [ns] 80 Ta=-40℃ Ta=25℃ Ta=125℃ tE/W[ms] 6 Ta=-40℃ Ta=25℃ Ta=125℃ SPEC tRO [ns] 60 60 4 40 SPEC 40 SPEC 20 20 2 Ta=125℃ Ta=-40℃ Ta=25℃ 0 0 1 2 3 Vcc[V] 4 5 6 0 0 1 2 3 Vcc[V] 4 5 6 0 0 1 2 3 Vcc[V] 4 5 6 Fig.30 Output rise time tRO Fig.31 Output fall time tFO Fig.32 Write cycle time tE/W 5/16 ●Features ○Status registers This IC has status registers. The status registers are of 8 bits and express the following parameters. BP0 and BP1 can be set by write status register command. These 2 bits are memorized into the EEPROM, therefore are valid even when power source is turned off. Rewrite characteristics and data hold time are same as characteristics of the EEPROM. WEN can be set by write enable command and write disable command. WEN becomes write disable status when power source is turned off. R/B is for write confirmation, therefore cannot be set externally. The value of status register can be read by read status command. ●Status registers Product number BR25H010-W BR25H020-W BR25H040-W BR25H080-W BR25H160-W BR25H320-W bit 7 1 bit 6 1 bit 5 1 bit 4 1 bit 3 BP1 bit 2 BP0 bit 1 WEN bit 0 R/B WPEN 0 0 0 BP1 BP0 WEN R/B bit Memory location Function WPB pin enable / disable designation bit WPEN=0=invalid WPEN=1=valid Contents This enables / disables the functions of WPB pin. This designates the write disable area of EEPROM. Write designation areas of product numbers are shown below. WPEN EEPROM BP1 BP0 WEN R/B EEPROM EEPROM write disable block designation bit Write and write status register write enable / disable status confirmation bit WEN=0=prohibited WEN=1=permitted Register Register Write cycle status (READY / BUSY) status confirmation bit R/B=0=READY R/B=1=BUSY ●Write disable block setting BP1 0 0 1 1 ○ BP0 0 1 0 1 BR25H010-W None 60h-7Fh 40h-7Fh 00h-7Fh BR25H020-W None C0h-FFh 80h-FFh 00h-FFh Write disable block BR25H040-W BR25H080-W None None 180h-1FFh 300h-3FFh 100h-1FFh 200h-3FFh 000h-1FFh 000h-3FFh BR25H160-W None 600h-7FFh 400h-7FFh 000h-7FFh BR25H320-W None C00h-FFFh 800h-FFFh 000h-FFFh WPB pin By setting WPB=LOW, write command is prohibited. As for BR25H080, 160, 320-W, only when WPEN bit is set “1”, the WPB pin functions become valid. And the write command to be disabled at this moment is WRSR. As for BR25H010, 020,040-W, both WRITE and WRSR commands are prohibited. However, when write cycle is in execution, no interruption can be made. WRSR Prohibition possible Prohibition possible but WPEN bit “1” WRITE Prohibition possible Prohibition impossible Product number BR25H010-W BR25H020-W BR25H040-W BR25H080-W BR25H160-W BR25H320-W ○HOLDB pin By HOLDB pin, data transfer can be interrupted. When SCK=”1”, by making HOLDB from “1” into”0”, data transfer to EEPROM is interrupted. When SCK = “0”, by making HOLDB from “0” into “1”, data transfer is restarted. 6/16 ●Command mode Ope code Command WREN WRDI READ WRITE RDSR WRSR Write enable Write disable Read Write Read status register Write status register Contents Write enable command Write disable command Read command Write command Status register read command Status register write command BR25H010-W BR25H020-W 0000 0000 0000 0000 0000 0000 110 100 ж 011 ж 010 ж ж ж BR25H040-W 0000 0000 0000 0000 0000 0000 110 100 A8011 A8010 ж ж ж BR25H080-W BR25H160-W BR25H320-W 0000 0110 0000 0100 0000 0011 0000 0010 0000 0000 0101 0001 101 001 101 001 ж ж ●Timing chart 1. Write enable (WREN) / disable (WRDI) cycle 1. WREN (WRITE ENABLE): Write enable CSB SCK 0 1 2 3 4 5 6 7 SI 0 0 0 0 *1 1 1 0 SO High-Z ж Fig.33 Write enable command 1. WRDI (WRITE DISABLE): Write disable CSB 1 BR25H010/020/040-W= Don’t care BR25H080/160/320-W= “0” input SCK 0 1 2 3 4 5 6 7 SI 0 0 0 0 *1 1 0 0 SO High-Z Fig.34 Write disable ж 1 BR25H010/020/040-W= Don’t care BR25H080/160/320-W= “0” input ○This IC has write enable status and write disable status. It is set to write enable status by write enable command, and it is set to write disable status by write disable command. As for these commands, set CSB LOW, and then input the respective ope codes. The respective commands accept command at the 7-th clock rise. Even with input over 7 clocks, command becomes valid. When to carry out write and write status register command, it is necessary to set write enable status by the write enable command. If write or write status register command is input in the write disable status, commands are cancelled. And even in the write enable status, once write and write status register command is executed, it gets in the write disable status. After power on, this IC is in write disable status. 7/16 2. Read command (READ) CSB ～～ ～～ ～～ SCK 0 1 2 3 4 5 6 7 8 9 10 11 15 16 ～～ 22 ～～ SI 0 0 0 0 *1 0 1 1 A7 A6 A5 A4 ～～ ～～ A1 A0 ～～ ～～ SO High-Z D7 D6 ж D2 D1 D0 Product number BR25H010-W BR25H020-W BR25H040-W Address length A6-A0 A7-A0 A8-A0 Fig.35 Read command (BR25H010/020/040-W) 1 BR25H010/020-W=Don’t care BR25H040-W=A8 CSB ～～ ～～ ～～ ～～ 12 23 24 ～～ SCK 0 1 2 3 4 5 6 7 8 ～～ 30 ～～ ～～ ж SI 0 0 0 0 0 0 1 1 ж ж ～～ ～～ A11 ～～ ～～ A1 A0 ～～ ～～ Product number BR25H080-W BR25H160-W BR25H320-W D0 Address length A9-A0 A10-A0 A11-A0 SO High-Z D7 D6 D2 ж D1 Fig.36 Read command (BR25H080/160/320-W) =Don’t Care By read command, data of EEPROM can be read. As for this command, set CSB LOW, then input address after read ope code. ж1 EEPROM starts data output of the designated address. Data output is started from SCK fall of 15/23 clock, and from D7 to D0 sequentially. This IC has increment read function. After output of data for 1 byte (8bits), by continuing input of SCK, data of the next address can be read. Increment read can read all the addresses of EEPROM. After reading data of the most significant address, by continuing increment read, data of the most insignificant address is read. ж 1 BR25H010/020/040-W=15 clocks BR25H080/160/320-W=23 clocks 3. Write command (WRITE) CSB SCK SI SO 0 1 2 3 4 5 6 7 8 ～～ ～～ ～～ ～～ ～～ 15 16 22 23 ～～ A1 A0 D7 D6 0 0 0 0 ж 1 0 1 0 A7 A6 A5 A4 ～～ ～～ ～～ ～～ D2 D1 D0 High-Z Product number BR25H010-W BR25H020-W BR25H040-W Address length A6-A0 A7-A0 A8-A0 Fig.37 Write command (BR25H010/020/040-W) CSB SCK SI SO 0 1 2 3 4 5 6 7 8 ж 1 BR25H010/020-W=Don’t care BR25H040-W=A8 ～～ ～～ ～～ ～～ ～～ 23 24 30 31 ～～ ж 0 0 0 0 0 0 1 0 ж ж ～～ ～～ A11 A1 A0 D7 D6 ～～ ～～ D2 D1 D0 High-Z Product number BR25H080-W BR25H160-W BR25H320-W ж Address length A9-A0 A10-A0 A11-A0 Fig.38 Write command (BR25H080/160/320-W) =Don't care By write command, data of EEPROM can be written. As for this command, set CSB LOW, then input address and data after write ope code. Then, by making CSB HIGH, the EEPROM starts writing. The write time of EEPROM requires time of tE/W (Max 5ms). During tE/W, other than status read command is not accepted. Start CSB after taking the last data (D0), and before the next SCK clock starts. At other timing, write command is not executed, and this write command is cancelled. This IC has page write function, and after input of data for 1 byte (8 bits), by continuing data input without starting CSB, data up to *1 ж2 16/32 bytes can be written for one tE/W. In page write, the insignificant 4/5 bit of the designated address is incremented internally at every time when data of 1 byte is input and data is written to respective addresses. When data of the maximum bytes or higher is input, address rolls over, and previously input data is overwritten. ж 1 BR25H010/020/040-W=16 bytes at maximum BR25H080/160/320-W=32 bytes at maximum ж 2 BR25H010/020/040-W=Insignificant 4 bits BR25H080/160/320-W=Insignificant 5 bits 8/16 4. Status register write / read command CSB SCK SI SO 0 1 2 3 4 5 6 7 bit7 8 9 bit6 ж 10 bit5 ж 11 bit4 ж 12 bit3 13 bit2 14 bit1 ж 15 bit0 ж 0 0 0 0 ж 0 0 1 ж BP1 BP0 High-Z ж Fig.39 Status register write command (BR25H010/020/040-W) CSB SCK SI SO 0 1 2 3 4 5 6 7 bit7 =Don't care 8 9 bit6 10 bit5 11 bit4 12 bit3 13 bit2 14 bit1 15 bit0 0 0 0 0 0 0 0 1 WPEN * * * BP1 BP0 * * High-Z ж =Don't care Fig.40 Status register write command (BR25H080/160/320-W) Write status register command can write status register data. The data can be written by this command are 2 bits , that is, BP1 (bit3) and BP0 (bit2) among 8 bits of status register. By BP1 and BP0, write disable block of EEPROM can be set. As for this command, set CSB LOW, and input ope code of write status register, and input data. Then, by making CSB HIGH, EEPROM starts writing. Write time requires time of tE/W as same as write. As for CSB rise, start CSB after taking the last data bit (bit0), and before the next SCK clock starts. At other timing, command is cancelled. Write disable block is determined by BP1 and BP0, and the block can be selected from 1/4 of memory array, 1/2, and entire memory array. (Refer to the write disable block setting table.) To the write disabled block, write cannot be made, and only read can be made. *1 3bits including BR25H080/160/320-W WPEN (bit7) ж1 CSB SCK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SI 0 0 0 0 ж 1 0 1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SO High-Z 1 1 1 1 BP1 BP0 WEN R/B ж =Don’t care Fig.41 Status register read command (BR25H010/020/040-W) CSB SCK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SI 0 0 0 0 0 1 0 1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SO High-Z WPEN 0 0 0 BP1 BP0 WEN R/B Fig.42 Status register read command (BR25H080/160/320-W) 9/16 ●At standby ○Current at standby Set CSB “H”, and be sure to set SCK, SI, WPB, HOLDB input “L” or “H”. Do not input intermediate electric potantial. ○Timing As shown in Fig.43, at standby, when SCK is “H”, even if CSB is fallen, SI status is not read at fall edge. SI status is read at SCK rise edge after fall of CSB. At standby and at power ON/OFF, set CSB “H” status. Even if CSB is fallen at SCK=SI=”H”, SI status is not read at that edge. CSB Command start here. SI is read. SCK 0 1 2 SI Fig.43 Operating timing ●WPB cancel valid area WPB is normally fixed to “H” or “L” for use, but when WPB is controlled so as to cancel write status register command and write command, pay attention to the following WPB valid timing. While write or write status register command is executed, by setting WPB = “L” in cancel valid area, command can be cancelled. The area from command ope code before CSB rise at internal automatic write start becomes the cancel valid area. However, once write is started, any input cannot be cancelled. WPB input becomes Don’t Care, and cancellation becomes invalid. SCK 15 16 CSB Ope code W PB cancel invalid area Data WPB cancel invalid area tE/W data write time WPB cancel invalid area invalid Fig.44 WPB valid timing (WRSR) tE/W data write time W PB cancel invalid area Ope code WPB cancel invalid area Address Data W PB cancel invalid area invalid valid Fig.45 WPB valid timing (WRITE) ●HOLDB pin By HOLDB pin, command communication can be stopped temporarily. (HOLD status) The HOLDB pin carries out command communications normally when it is HIGH. To get in HOLD status, at command communication, when SCK=LOW, set the HOLDB pin LOW. At HOLD status, SCK and SI become Don’t Care, and SO becomes high impedance (High-Z). To release the HOLD status, set the HOLDB pin HIGH when SCK=LOW. After that, communication can be restarted from the point before the HOLD status. For example, when HOLD status is made after A5 address input at read, after release of HOLD status, by starting A4 address input, read can be restarted. When in HOLD status, leave CSB LOW. When it is set CSB=HIGH in HOLD status, the IC is reset, therefore communication after that cannot be restarted. 10/16 ●Method to cancel each command ○READ ・Method to cancel : cancel by CSB = “H” Ope code 8 bit Address 8 bit/16bit Data 8 bit Cancel available in all areas of read mode Fig.46 READ cancel valid timing ○RDSR ・Method to cancel : cancel by CSB = “H” Ope code 8 bit Data 8 bit Cancel available in all areas of read mode Fig.47 RDSR cancel valid timing ○WRITE、PAGE WRITE a：Ope code, address input area. Cancellation is available by CSB=”H” b：Data input area (D7~D1 input area) Cancellation is available by CSB=”H” c：Data input area (D0 area) When CSB is started, write starts. After CSB rise, cancellation cannot be made by any means. d：tE/W area. Cancellation is available by CSB = “H”. However, when write starts (CSB is started) in the area c, cancellation cannot be made by any means. And by inputting on SCK clock, cancellation cannot be made. In page write mode, there is write enable area at every 8 clocks. Ope code 8bit a Address Data tE/W 8bit/16bit 8bit b c d Fig.48 WRITE cancel valid timing SCK D7 D6 D5 D4 b D3 D2 D1 D0 c SI Note 1) If Vcc is made OFF during write execution, designated address data is not guaranteed, therefore write it once again. Note 2) If CSB is started at the same timing as that of the SCK rise, write execution / cancel becomes unstable, therefore, it is recommended to fall in SCK = “L” area. As for SCK rise, assure timing of tCSS / tCSH or higher. ○WRSR a：From ope code to 15 rise. Cancel by CSB =”H”. b：From 15 clock rise to 16 clock rise (write enable area). When CSB is started, write starts. After CSB rise, cancellation cannot be made by any means. c：After 16 clock rise. Cancel by CSB=”H”. However, when write starts (CSB is started) in the area b, cancellation cannot be made by any means. And, by inputting on SCK clock, cancellation cannot be made. 14 15 16 17 D1 a Ope code 8 bit a Data 8 bit D0 b c tE/W c b Fig.49 WRSR cancel valid timing Note 1) If Vcc is made OFF during write execution, designated address data is not guaranteed, therefore write it once again Note 2) If CSB is started at the same timing as that of the SCK rise, write execution / cancel becomes unstable, therefore, it is recommended to fall in SCK = “L” area. As for SCK rise, assure timing of tCSS / tCSH or higher. SCK 7 a Ope code 8 bit a b 8 b 9 ○WREN/WRDI a：From ope code to 7-th clock rise, cancel by CSB = “H”. b：Cancellation is not available when CSB is started after 7-th clock. Fig.50 WREN/WRDI cancel valid timing 11/16 ●High speed operation In order to realize stable high speed operations, pay attention to the following input / output pin conditions. ○Input pin pull up, pull down resistance When to attach pull up, pull down resistance to EEPROM input pin, select an appropriate value for the microcontroller VOL, IOL from VIL characteristics of this IC. ○Pull up resistance RPU≥ Microcontroller VOLM “L” output IOLM EEPROM VILE “L” input VCC-VOLM IOLM VILE ･･･① ･･･② VOLM≤ Example) When Vcc=5V, VILE=1.5V, VOLM=0.4V, IOLM=2mA, from the equation ①, RPU≥ ∴RPU≥ 5-0.4 2×10 -3 Fig.51 Pull up resistance 2.3[kΩ] With the value of Rpu to satisfy the above equation, VOLM becomes 0.4V or higher, and with VILE (=1.5V), the equation ② is also satisfied. ・VILE :EEPROM VIL specifications ・VOLM :Microcontroller VOL specifications ・IOLM :Microcontroller IOL specifications And, in order to prevent malfunction, mistake write at power ON/OFF, be sure to make CSB pull up. ○Pull down resistance VOHM Microcontroller VOHM “H” output EEPROM VIHE RPD≥ VOHM≥ IOHM VIHE ･･･③ ･･･④ IOHM “H” input Fig.52 Pull down resistance Example) When VCC=5V, VOHM=VCC-0.5V, IOHM＝0.4mA, VIHE=VCC×0.7V, from the equation③, 5-0.5 0.4×10-3 11.3[kΩ] RPD≥ ∴RPU≥ Further, by amplitude VIHE, VILE of signal input to EEPROM, operation speed changes. By inputting signal of amplitude of VCC / GND level to input, more stable high speed operations can be realized. On the contrary, when amplitude of 0.8VCC / 0.2Vcc is input, operation speed becomes slow. 12/16 In order to realize more stable high speed operation, it is recommended to make the values of RPU, RPD as large as possible, and make the amplitude of signal input to EEPROM close to the amplitude of VCC / GND level. ж ( 1 At this moment, operating timing guaranteed value is guaranteed.) tPD-VIL characteristics 80 70 60 tPD[ns] 50 40 30 20 10 0 0 0.2 0.4 VIL[V] 0.6 0.8 1 Vcc=2.5V Ta=25℃ VIH=Vcc CL=100pF Fig.53 VIL dependency of data output delay time ○SO load capacity condition Load capacity of SO output pin affects upon delay characteristic of SO output. (Data output delay time, time from HOLDB to High-Z) In order to make output delay characteristic into higher speed, make SO load capacity small. In concrete, “Do not connect many devices to SO bus”, “Make the wire between the controller and EEPROM short”, and so forth. tPD-CL characteristics 80 Vcc=2.5V 　 Ta=25℃ 70 60 tPD[ns] 50 VIH/VIL=0.8Vcc/0.2Vcc EEPROM SO CL 40 30 20 0 20 40 60 CL[V] 80 100 120 Fig.54 SO load dependency of data output delay time ○Other cautions Make the wire length from the microcontroller to EEPROM input signal same length, in order to prevent setup / hold violation to EEPROM, owing to difference of wire length of each input. 13/16 ●Equivalent circuit ○Output circuit SO OEint. Fig.55 SO output equivalent circuit ○Input circuit RESETint. CSB Fig.56 CSB input equivalent circuit SCK SI Fig.57 SCK input equivalent circuit Fig.58 SI input equivalent circuit HOLDB WPB Fig.59 HOLDB input equivalent circuit Fig.60 WPB input equivalent circuit 14/16 ●Notes on power ON/OFF ○At power ON/OFF, set CSB “H” (=Vcc). When CSB is “L”, this IC gets in input accept status (active). If power is turned on in this status, noises and the likes may cause malfunction, mistake write or so. To prevent these, at power ON, set CSB “H”. (When CSB is in “H” status, all inputs are canceled.) Vcc Vcc GND Vcc CSB GND Good Example Bad example Fig.61 CSB timing at power ON/OFF (Good example) (Bad example) CSB terminal is pulled up to Vcc. At power OFF, take 10ms or higher before supply. If power is turned on without observing this condition, the IC internal circuit may not be reset, which please note. CSB terminal is “L” at power ON/OFF. In this case, CSB always becomes “L” (active status), and EEPROM may have malfunction, mistake write owing to noises and the likes. Even when CSB input is High-Z, the status becomes like this case, which please note. ○LVCC circuit LVCC (Vcc-Lockout) circuit prevents data rewrite action at low power, and prevents wrong write. At LVCC voltage (Typ. =1.9V) or below, it prevent data rewrite. ○P.O.R. circuit This IC has a POR (Power On Reset) circuit as mistake write countermeasure. After POR action, it gets in write disable status. The POR circuit is valid only when power is ON, and does not work when power is OFF. When power is ON, if the recommended conditions of the following tR, tOFF, and Vbot are not satisfied, it may become write enable status owing to noises and the likes. Vcc tR Recommended conditions of tR, tOFF, Vbot tR 10ms or below tOFF Vbot tOFF 10ms or higher 10ms or higher Vbot 0.3V or below 0.2V or below 100ms or below 0 Fig.62 Rise waveform ●Noise countermeasures ○Vcc noise (bypass capacitor) When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is recommended to attach a bypass capacitor (0.1μF) between IC Vcc and GND. At that moment, attach it as close to IC as possible. And, it is also recommended to attach a bypass capacitor between board Vcc and GND. ○SCK noise When the rise time (tR) of SCK is long, and a certain degree or more of noise exists, malfunction may occur owing to clock bit displacement. To avoid this, a Schmitt trigger circuit is built in SCK input. The hysterisis width of this circuit is set about 0.2V, if noises exist at SCK input, set the noise amplitude 0.2Vp-p or below. And it is recommended to set the rise time (tR) of SCK 100ns or below. In the case when the rise time is 100ns or higher, take sufficient noise countermeasures. Make the clock rise, fall time as small as possible. ○WPB noise During execution of write status register command, if there exist noises on WPB pin, mistake in recognition may occur and forcible cancellation may result, which please note. To avoid this, a Schmitt trigger circuit is built in WPB input. In the same manner, a Schmitt trigger circuit is built in SI input and HOLDB input too. ●Cautions on use (1)Described numeric values and data are design representative values, and the values are not guaranteed. (2)We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin in consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI. (3)Absolute maximum ratings If the absolute maximum ratings such as impressed voltage and operating temperature range and so forth are exceeded, LSI may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum ratings should not be impressed to LSI. (4)GND electric potential Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that of GND terminal. (5)Heat design In consideration of permissible dissipation in actual use condition, carry out heat design with sufficient margin. (6)Terminal to terminal short circuit and wrong packaging When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may destruct LSI. And in the case of short circuit between LSI terminals and terminals and power source, terminal and GND owing to foreign matter, LSI may be destructed. (7)Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently. 15/16 ●Selection of order type B R 2 BUS type 25: SPI 5 H 0 1 0 F Package type F: SOP8 FJ: SOP-J8 W Double cell E 2 Rohm type name Operating temperature H :-40℃～+125℃ Capacity 010= 1K 020= 2K 040= 4K 080= 8K 160=16K 320=32K Package specifications E2：reel shape emboss taping ●Package specifications SOP8/SOP-J8 SOP8/SOP-J8 ・SOP8 5.0±0.2 8 5 ・SOP-J8 4.9±0.2 Package type Package quantity Emboss taping 2500pcs 6.2±0.3 4.4±0.2 0.3Min. 6.0±0.3 3.9±0.2 1234 1 4 1.5±0.1 0.11 0.15±0.1 0.1 1.375±0.1 0.175 0.2±0.1 1234 1234 1234 1234 1234 1234 1234 1234 1.27 0.4±0.1 1.27 0.42±0.1 0.1 0.45Min. 8765 Package direction E2 (When the reel gripped by the left hand, and the tape is pulled out by the right hand, No.1 pin of product is at the left top.) Reel Pin No.1 Pulling side (Unit:mm) *For ordering, specify a number of multiples of the package quantity. 16/16 Appendix Notes No technical content pages of this document may be reproduced in any form or transmitted by any means without prior permission of ROHM CO.,LTD. The contents described herein are subject to change without notice. The specifications for the product described in this document are for reference only. Upon actual use, therefore, please request that specifications to be separately delivered. Application circuit diagrams and circuit constants contained herein are shown as examples of standard use and operation. Please pay careful attention to the peripheral conditions when designing circuits and deciding upon circuit constants in the set. Any data, including, but not limited to application circuit diagrams information, described herein are intended only as illustrations of such devices and not as the specifications for such devices. ROHM CO.,LTD. disclaims any warranty that any use of such devices shall be free from infringement of any third party's intellectual property rights or other proprietary rights, and further, assumes no liability of whatsoever nature in the event of any such infringement, or arising from or connected with or related to the use of such devices. Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or otherwise dispose of the same, no express or implied right or license to practice or commercially exploit any intellectual property rights or other proprietary rights owned or controlled by ROHM CO., LTD. is granted to any such buyer. Products listed in this document are no antiradiation design. The products listed in this document are designed to be used with ordinary electronic equipment or devices (such as audio visual equipment, office-automation equipment, communications devices, electrical appliances and electronic toys). Should you intend to use these products with equipment or devices which require an extremely high level of reliability and the malfunction of which would directly endanger human life (such as medical instruments, transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers and other safety devices), please be sure to consult with our sales representative in advance. It is our top priority to supply products with the utmost quality and reliability. However, there is always a chance of failure due to unexpected factors. Therefore, please take into account the derating characteristics and allow for sufficient safety features, such as extra margin, anti-flammability, and fail-safe measures when designing in order to prevent possible accidents that may result in bodily harm or fire caused by component failure. ROHM cannot be held responsible for any damages arising from the use of the products under conditions out of the range of the specifications or due to non-compliance with the NOTES specified in this catalog. Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact your nearest sales office. ROHM Customer Support System www.rohm.com Copyright © 2007 ROHM CO.,LTD. THE AMERICAS / EUPOPE / ASIA / JAPAN Contact us : webmaster@ rohm.co. jp 21, Saiin Mizosaki-cho, Ukyo-ku, Kyoto 615-8585, Japan TEL : +81-75-311-2121 FAX : +81-75-315-0172 Appendix1-Rev2.0