BR9040

Memory ICs 1, 2, and 4k bit EEPROMs for direct connection to serial ports BR9010 / BR9010F / BR9010FV / BR9020 / BR9020F / BR9040 / BR9040F Features ••BR9010 / F / FV (1k bit): 64 words × 16 bits BR9020 / F (2k bit): 128 words × 16 bits BR9040 / F (4k bit): 256 words × 16 bits •Single power supply operation •Serial data input and output •Automatic erase-before-write •Low current consumption –1.5mA (max.) active current: 3V –2µA (max.) standby current: 3V •Noise filter built into SK pin •Compact DIP8, SOP8, SSOP-B8 packages (SSOPB8 is available only with BR9010). •100,000 ERASE / WRITE cycles •10 years Data Retention •Easily connects to serial port •Pin assignments CS SK DI DO 1 2 3 4 8 7 6 5 VCC R / B∗ 1 R / B∗ VCC 2 WC GND CS SK 3 4 8 WC GND DO DI BR9010 / BR9020 / 9040 BR9010F / BR9010FV / BR9020F / BR9040F 7 6 5 ∗ This pin is N.C. (non connection) on BR9010. •Pin description Pin name CS SK DI DO GND WC R /B VCC Chip select input Serial data clock input Operating code, address, and serial data input Serial data output Reference voltage for all I / O, 0V Write control input READY, BUSY status signal output Power supply connection Function •Overviewseries are serial EEPROMs that can be connected directly to a serial port and can be erased and written The BR90 electrically. Writing and reading is performed in word units, using four types of operation commands. Communication occurs through CS, SK, DI, and DO pins, WC pin control is used to initiate a write disabled state, enabling these EEPROMs to be used as one-time ROMs. During writing, operation is checked via the internal status check. 1 Memory ICs BR9010 / BR9010F / BR9010FV / BR9020 / BR9020F / BR9040 / BR9040F •Block diagram BR9010 / F / FV CS Command decode Control SK Clock generation Write disable High voltage generator WC Power supply voltage detector DI Command register Address buffer 6bit Address decoder 6bit 1024bit EEPROM DO Data register 16bit R/W amplifier array 16bit BR9020 / F, BR9040 / F R/B CS Command decode Control SK Clock generation Write disable Power supply voltage detector High voltage generator WC DI Command register Address buffer 7 (8) bit Address decoder 7 (8) bit 2,048 (4,096) bit EEPROM DO Data register 16bit R/W amplifier 16bit array ∗ Values in parentheses are for the BR9040 / F. 2 Memory ICs BR9010 / BR9010F / BR9010FV / BR9020 / BR9020F / BR9040 / BR9040F •Absolute maximum ratings (Ta = 25°C) Parameter Applied voltage Symbol VCC Limits – 0.3 ~ + 7.0 DIP8 Power dissipation Pd SOP8 SSOP-B8 Storage temperature Operation temperature Input voltage Tstg Topr — 500∗1 350∗2 300∗3 °C °C V mW Unit V – 65 ~ + 125 – 40 ~ + 85 – 0.3 ~ VCC + 0.3 ∗ Reduced by 5.0mw∗1 / 3.5mw∗2 / 3.0mw∗3 for each increase in Ta of 1°C over 25°C. •Recommended operating conditions Parameter Power supply voltage Input voltage Symbol VCC VIN Limits 2.7 to 5.5 (write) 2.0 to 5.5 (read) 0 ~ VCC Unit V V V 3 Memory ICs BR9010 / BR9010F / BR9010FV / BR9020 / BR9020F / BR9040 / BR9040F •ElectricalF characteristics otherwise noted, Ta = – 40 to + 85°C, V BR9010 / / FV: At 5V (unless Parameter Input low level voltage 1 Symbol VIL1 Min. — 0.7 × VCC Input low level voltage 2 VIL2 — 0.8 × VCC Output low level voltage Output high level voltage VOL VOH 0 VCC – 0.4 Input leak current Output leak current Consumption current during operation Standby current SK frequency ILI ILO ICC1 ICC2 ISB fSK –1 –1 — — — — — — — — — — 1 1 2 1 3 1 µA µA mA mA µA — — 0.4 VCC V V — 0.2 × VCC Input high level voltage 2 VIH2 — — V V Typ. — Max. 0.3 × VCC Input high level voltage 1 VIH1 — — V Unit V CC = 5V ± 10%) Conditions DI Pin DI Pin CS, SK, WC Pin CS, SK, WC Pin IOL = 2.1mA IOH = – 0.4mA VIN = 0V ~ VCC VOUT = 0V ~ VCC CS = VCC f = 1MHz tE / W = 10ms (WRITE) f = 1MHz (READ) CS, SK, DI, WC, = VCC DO = OPEN — MHz BR9010 / F / FV: At 3V (unless otherwise noted, Ta = – 40 to + 85°C, VCC = 3V ± 10%) Parameter Input low level voltage 1 Symbol VIL1 Min. — 0.7 × VCC Input low level voltage 2 VIL2 — 0.8 × VCC Output low level voltage Output high level voltage VOL VOH 0 VCC – 0.4 Input leak current Output leak current Consumption current during operation Standby current SK frequency Not designed for radiation resistance Typ. — Max. 0.3 × VCC Unit V DI Pin Conditions Input high level voltage 1 VIH1 — — 0.2 × VCC V DI Pin — V CS, SK, WC Pin Input high level voltage 2 VIH2 — — V CS, SK, WC Pin IOL = 100µA IOH = – 100µA — — 0.4 VCC V V µA µA mA µA µA MHz ILI ILO ICC1 ICC2 ISB fSK –1 –1 — — — — — — — — — — 1 1 1.5 500 2 1 VIN = 0 ~ VCC VOUT = 0 ~ VCC CS = VCC f = 1MHz tE / W = 15ms (WRITE) f = 1MHz (READ) CS, SK, DI, WC, = VCC DO = OPEN — 4 Memory ICs BR9010 / BR9010F / BR9010FV / BR9020 / BR9020F / BR9040 / BR9040F •Electrical/ characteristics otherwise noted, Ta = – 40 to + 85°C, V •BR9020 F: At 5V (unless Parameter Input low level voltage 1 Input high level voltage 1 Input low level voltage 2 Input high level voltage 2 Output low level voltage Output high level voltage Input leak current Output leak current Consumption current during operation Standby current SK frequency Symbol VIL1 VIH1 VIL2 VIH2 VOL VOH ILI ILO ICC1 ICC2 ISB fSK Min. — 0.7 × VCC — 0.8 × VCC 0 VCC – 0.4 –1 –1 — — — — Typ. — — — — — — — — — — — — Max. 0.3 × VCC — 0.2 × VCC — 0.4 VCC 1 1 2 1 3 1 CC = 5V ± 10%) Conditions DI Pin DI Pin CS, SK, WC Pin CS, SK, WC Pin IOL = 2.1mA IOH = – 0.4mA VIN = 0V ~ VCC VOUT = 0V ~ VCC CS = VCC fSK = 1MHz tE / W = 10ms (WRITE) fSK = 1MHz (READ) CS, SK, DI, WC, = VCC DO, R / B = OPEN — Unit V V V V V V µA µA mA mA µA MHz •BR9020 / F: At 3V (unless otherwise noted, Ta = – 40 to + 85°C, V Parameter Input low level voltage 1 Input high level voltage 1 Input low level voltage 2 Input high level voltage 2 Output low level voltage Output high level voltage Input leak current Output leak current Consumption current during operation Standby current SK frequency Symbol VIL1 VIH1 VIL2 VIH2 VOL VOH ILI ILO ICC1 ICC2 ISB fSK Min. — 0.7 × VCC — 0.8 × VCC 0 VCC – 0.4 –1 –1 — — — — Typ. — — — — — — — — — — — — Max. 0.3 × VCC — 0.2 × VCC — 0.4 VCC 1 1 1.5 500 2 1 CC = 3V ± 10%) Conditions DI Pin DI Pin CS, SK, WC Pin CS, SK, WC Pin IOL = 100µA IOH = – 100µA VIN = 0V ~ VCC VOUT = 0V ~ VCC CS = VCC fSK = 1MHz tE / W = 15ms (WRITE) fSK = 1MHz (READ) CS, SK, DI, WC, = VCC DO, R / B = OPEN — Unit V V V V V V µA µA mA µA µA MHz 5 Memory ICs BR9010 / BR9010F / BR9010FV / BR9020 / BR9020F / BR9040 / BR9040F •Electrical/ characteristics otherwise noted, Ta = – 40 to + 85°C, V •BR9040 F: At 5V (unless Parameter Input low level voltage 1 Input high level voltage 1 Input low level voltage 2 Input high level voltage 2 Output low level voltage Output high level voltage Input leak current Output leak current Consumption current during operation Standby current SK frequency Symbol VIL1 VIH1 VIL2 VIH2 VOL VOH ILI ILO ICC1 ICC2 ISB fSK Min. — 0.7 × VCC — 0.8 × VCC 0 VCC – 0.4 –1 –1 — — — — Typ. — — — — — — — — — — — — Max. 0.3 × VCC — 0.2 × VCC — 0.4 VCC 1 1 2 1 3 1 CC = 5V ± 10%) Conditions DI Pin DI Pin CS, SK, WC Pin CS, SK, WC Pin IOL = 2.1mA IOH = – 0.4mA VIN = 0V ~ VCC VOUT = 0V ~ VCC CS = VCC fSK = 1MHz tE / W = 10ms (WRITE) fSK = 1MHz (READ) CS, SK, DI, WC, = VCC DO, R / B = OPEN — Unit V V V V V V µA µA mA mA µA MHz •BR9040 / F: At 3V (unless otherwise noted, Ta = – 40 to + 85°C, V Parameter Input low level voltage 1 Input high level voltage 1 Input low level voltage 2 Input high level voltage 2 Output low level voltage Output high level voltage Input leak current Output leak current Consumption current during operation Standby current SK frequency Symbol VIL1 VIH1 VIL2 VIH2 VOL VOH ILI ILO ICC1 ICC2 ISB fSK Min. — 0.7 × VCC — 0.8 × VCC 0 VCC – 0.4 –1 –1 — — — — — Typ. — — — — — — — — — — — — — Max. 0.3 × VCC — 0.2 × VCC — 0.4 VCC 1 1 1.5 500 2 1 750 CC = 3V ± 10%) Conditions DI Pin DI Pin CS, SK, WC Pin CS, SK, WC Pin IOL = 100µA IOH = – 100µA VIN = 0V ~ VCC VOUT = 0V ~ VCC CS = VCC fSK = 1MHz tE / W = 15ms (WRITE) fSK = 1MHz (READ) CS, SK, DI, WC, = VCC DO, R / B = OPEN VCC = 3.0 ~ 3.3V VCC = 2.7 ~ 3.0V Unit V V V V V V µA µA mA µA µA MHz kHz 6 Memory ICs BR9010 / BR9010F / BR9010FV / BR9020 / BR9020F / BR9040 / BR9040F •Operation /timingAtcharacteristics BR9010 / F FV: 5V (unless otherwise noted, Ta = – 40 to + 85°C, V Parameter CS setup time CS hold time Data setup time Data hold time DO rise delay time DO fall delay time Self-timing programming cycle CS minimum high level time Time when DO goes High-Z (via CS) Data clock high level time Data clock low level time Write control setup time Write control hold time Symbol tCSS tCSH tDIS tDIH tPD1 tPD0 tE / W tCS tOH tWH tWL tWCS tWCH Min. 200 0 150 150 — — — 1 0 450 450 0 0 Typ. — — — — — — — — — — — — — CC = 5V ± 10%) Unit ns ns ns ns ns ns ms µs ns ns ns ns ns Max. — — — — 350 350 10 — 400 — — — — •BR9010 / F / FV: At 3V (unless otherwise noted, Ta = – 40 to + 85°C, V Parameter CS setup time CS hold time Data setup time Data hold time DO rise delay time DO fall delay time Self-timing programming cycle CS minimum high level time Time when DO goes High-Z (via CS) Data clock high level time Data clock low level time Write control setup time Write control hold time Symbol tCSS tCSH tDIS tDIH tPD1 tPD0 tE / W tCS tOH tWH tWL tWCS tWCH Min. 200 0 150 150 — — — 1 0 450 450 0 0 Typ. — — — — — — — — — — — — — — — — — CC = 3V ± 10%) Unit ns ns ns ns ns ns ms µs ns ns ns ns ns Max. 350 350 15 — 400 — — — — 7 Memory ICs BR9010 / BR9010F / BR9010FV / BR9020 / BR9020F / BR9040 / BR9040F •Operation /timingAtcharacteristics BR9020 / F FV: 5V (unless otherwise noted, Ta = – 40 to + 85°C, V Parameter CS setup time CS hold time Data setup time Data hold time DO rise delay time DO fall delay time Self-timing programming cycle CS minimum high level time READY / BUSY display valid time Time when DO goes High-Z (via CS) Data clock high level time Data clock low level time Write control setup time Write control hold time Symbol tCSS tCSH tDIS tDIH tPD1 tPD0 tE / W tCS tSV tOH tWH tWL tWCS tWCH Min. 200 0 150 150 — — — 1 — 0 450 450 0 0 Typ. — — — — — — — — — — — — — — CC = 5V ± 10%) Unit ns ns ns ns ns ns ms µs µs ns ns ns ns ns Max. — — — — 350 350 10 — 1 400 — — — — •BR9020 / F / FV: At 3V (unless otherwise noted, Ta = – 40 to + 85°C, V Parameter CS setup time CS hold time Data setup time Data hold time DO rise delay time DO fall delay time Self-timing programming cycle CS minimum high level time READY / BUSY display valid time Time when DO goes High-Z (via CS) Data clock high level time Data clock low level time Write control setup time Write control hold time Symbol tCSS tCSH tDIS tDIH tPD1 tPD0 tE / W tCS tSV tOH tWH tWL tWCS tWCH Min. 200 0 150 150 — — — 1 — 0 450 450 0 0 Typ. — — — — — — — — — — — — — — — — — — CC = 3V ± 10%) Unit ns ns ns ns ns ns ms µs µs ns ns ns ns ns Max. 350 350 15 — 1 400 — — — — 8 Memory ICs BR9010 / BR9010F / BR9010FV / BR9020 / BR9020F / BR9040 / BR9040F characteristics •Operation timing (unless otherwise noted, Ta = – 40 to + 85°C, V BR9040 / F: At 5V Parameter CS setup time CS hold time Data setup time Data hold time DO rise delay time DO fall delay time Self-timing programming cycle CS minimum high level time READY / BUSY display valid time Time when DO goes High-Z (via CS) Data clock high level time Data clock low level time Write control setup time Write control hold time Symbol tCSS tCSH tDIS tDIH tPD1 tPD0 tE / W tCS tSV tOH tWH tWL tWCS tWCH Min. 200 0 150 150 — — — 1 — 0 500 500 0 0 Typ. — — — — — — — — — — — — — — CC = 5V ± 10%) Max. — — — — 350 350 10 — 1 400 — — — — Unit ns ns ns ns ns ns ms µs µs ns ns ns ns ns •BR9040 / F: At 3V (unless otherwise noted, Ta = – 40 to + 85°C, V Parameter CS setup time CS hold time Data setup time Data hold time DO rise delay time VCC = 3.0 ~ 3.3V DO fall delay time VCC = 3.0 ~ 3.3V DO rise delay time VCC = 2.7 ~ 3.0V DO fall delay time VCC = 2.7 ~ 3.0V Self-timing programming cycle CS minimum high level time READY / BUSY display valid time Time when DO goes High-Z (via CS) Data clock high level time VCC = 3.0 ~ 3.3V Data clock low level time VCC = 3.0 ~ 3.3V Data clock high level time VCC = 2.7 ~ 3.0V Data clock low level time VCC = 2.7 ~ 3.0V Write control setup time Write control hold time Symbol tCSS tCSH tDIS tDIH tPD1 tPD0 tPD1 tPD0 tE / W tCS tSV tOH tWH tWL tWH tWL tWCS tWCH Min. 200 0 150 150 — — — — — 1 — 0 500 500 650 650 0 0 Typ. — — — — — — — — — — — — — — — — — — CC = 3V ± 10%) Unit ns ns ns ns ns ns ns ns ms µs µs ns ns ns ns ns ns ns Max. — — — — 350 350 500 500 15 — 1 400 — — — — — — 9 Memory ICs BR9010 / BR9010F / BR9010FV / BR9020 / BR9020F / BR9040 / BR9040F •Input / output circuits (1) Input circuits RESET int. CS int. CS SK CS int. WC DI (2) Output circuits DO DO ∗ DO: BR9010 // F / FV BR9020 F OE int. OE int. ∗ DO: BR9040 / F R/B R / B: BR9020 / F, BR9040 / F •Circuit operation (1) Command mode Command Read Write Erase / Write enabled Erase / Write disable (READ) (WRITE) (EWEN) (EWDS) 1 is ‘0’ 1 and 2 are ‘0’ Start bit 1010 1010 1010 1010 Operating code 1000 0100 0011 0000 Address A0 A1 A2 A3 A4 A5 (A6) A0 A1 A2 A3 A4 A5 (A6) 2 2 Data (A7) (A7) 1 1 D0 D1—D14 D15 ∗∗∗∗∗∗∗ ∗∗∗∗∗∗∗ ∗ ∗ ∗ Either VIH or VIL With BR9020 / F, With BR9010 / F / FV, 10 Memory ICs (2) Timing chart CS tCSS SK tWL tDIS DI tPD DO tDIH tWH BR9010 / BR9010F / BR9010FV / BR9020 / BR9020F / BR9040 / BR9040F tCS tCSH tPD tOH WC • Data is read in on the rising edge of SK. Data is output in synchronism with the SK falling edge. • During a READ operation, data is output from DO in synchronization with the SK rise. • WC is related to the write command only. Read, erase / write enable, erase / write disable commands can be executed irrespective of the state of WC. (3) Writing enabled / disabled H SK L H CS L H DI 1 L High-Z DO H R/B WC H or L Fig.1 1 4 8 ENABLE = 1 1 DISABLE = 0 0 12 16 0 1 0 0 0 1) When the power supply is turned on, the latch used to acknowledge writing is reset in the same way as when the write disable command is executed. Before entering the write mode, the write enabled mode must first be entered. Once the write enabled mode has been recognized, it remains valid until the write disabled mode is entered, or the power supply is turned off. 2) The clock is no longer necessary after the first 16 clock pulses have been received. Any subsequent input will be ignored. 3) WC does not exist for either the write enabled or write disabled command, so WC may be either HIGH or LOW when the command is being input. 4) Commands are received in these modes by means of 8-bit operating codes. Please be aware that, after an operating code has been entered, commands will not be canceled even if CS is set to HIGH. (To cancel a command, either turn off the power supply, or input the command once again.) 11 Memory ICs BR9010 / BR9010F / BR9010FV / BR9020 / BR9020F / BR9040 / BR9040F •Circuit operation (4) Read cycle H SK L H CS L STANDBY H DI L High-Z High-Z tOH WC H or L 1 0 1 0 1 0 0 0 A0 A5 0 0 1 4 8 16 32 tCS DO D0 D15 Fig.2 BR9010 / F / FV H SK L H CS L STANDBY H DI L High-Z High-Z tOH H 1 0 1 0 1 0 0 0 A0 A6 0 1 4 8 16 32 tCS DO D0 D15 R/B WC H or L Fig.3 BR9020 / F H SK L H CS L STANDBY H DI L High-Z High-Z tOH H 1 0 1 0 1 0 0 0 A0 A6 A7 1 4 8 16 32 tCS DO D0 D15 R/B WC H or L Fig.4 BR9040 / F 1) After the fall of the 16th clock pulse, 16-bit data is output from the DO pin in synchronization with the falling edge of the SK signal. (DO output changes at a time lag of tPD0, tPD1 because of internal circuit delay following the falling edge of the SK signal. During the tPD0 and tPD1 timing, the tPD time should be assured before data is read, to avoid the previous data being lost. See the synchronized data input / output timing chart in Fig. 1.) 12 Memory ICs BR9010 / BR9010F / BR9010FV / BR9020 / BR9020F / BR9040 / BR9040F •Circuit operation (5) Writing cycle H SK 1 L H CS L H DI L 1 0 1 0 0 1 0 0 A0 A5 0 0 D0 D15 High-Z tE / W H WC L tWCS tWCH tCS 4 8 16 32 DO High-Z Fig.5 BR9010 / F / FV H SK L H CS L H DI 1 High-Z DO tSV H R/B H WC L tWCS tWCH tE / W 0 1 0 0 1 0 0 A0 A6 0 D0 D15 High-Z tCS 1 4 8 16 32 Fig.6 BR9020 / F H SK L H CS L H DI 1 High-Z DO tSV H tE / W 0 1 0 0 1 0 0 A0 A6 A7 D0 D15 High-Z tCS 1 4 8 16 32 R/B H WC L tWCS tWCH Fig.7 BR9040 / F 13 Memory ICs BR9010 / BR9010F / BR9010FV / BR9020 / BR9020F / BR9040 / BR9040F 1) During input in the write mode, CS must be LOW, but once writing starts, CS may be either HIGH or LOW. However, if CS and WC share the same connection, both CS and WC should be set to LOW during writing operations. (If the WC pin is set to HIGH during a writing operation, writing will be forcibly interrupted at that point. If this happens, the data for that address may be lost, in which case it should be rewritten to that address.) 2) Following input of a write command, CS goes HIGH. If CS is then set to LOW, data will be received from SK and DI, because the command reception status has been entered. If CS remains LOW following command input, however, without first going HIGH, command input will be canceled until CS is set to HIGH. 3) Starting from the rising edge of the 32nd clock, the R / B pin goes LOW after RSV has elapsed. 4) The R / B pin is LOW during writing operations. (Following the rising edge of SK after the last data D15 has been read, the internal timer circuit is activated, and writing of data in the memory cell is automatically completed during tE / W.) At this point, SK input may be either HIGH or LOW during tE / W. 5) Following input of a write command, if CS falls while SK is LOW, the R / B status can be displayed from the DO pin. (See the section on READY / BUSY states.) (6) READY / BUSY display (R / B pin and DO pin) 1) This display outputs the internal status signal; the R / B pin outputs the HIGH or LOW status at all times. The display can also be output from the DO pin. Following completion of the writing command, if CS falls while SK is LOW, either HIGH or LOW is output. (The display can also be output without using the R / B pin, leaving it open.) 2) When writing data to a memory cell, the READY / BUSY display is output from the rise of the 32nd clock pulse of the SK signal after tSV, from the R / B pin. R / B display = LOW: writing in progress (The internal timer circuit is activated, and after the tE / W timing has been created, the timer circuit stops automatically. Writing of data to the memory cell is done during the tE / W timing, during which time other commands cannot be received.) R / B display = HIGH: command standby state (Writing of data to the memory cell has been completed and the next command can be received.) SK Clock CS DI Write command HIGH-Z tPD READY BUSY READY tOZ HIGH-Z DO R/B BUSY READY Fig.8 R / B status output timing 14 Memory ICs notes •Operation the power supply on and off (1) Turning BR9010 / BR9010F / BR9010FV / BR9020 / BR9020F / BR9040 / BR9040F 1) When the power supply is turned on and off, CS should be set to HIGH ( = VCC). 2) When CS is LOW, the command input reception state (active) is entered. If the power supply is turned on in this state, erroneous operations and erroneous writing can occur because of noise and other factors. To avoid this, make sure CS is set to HIGH ( = VCC) before turning on the power supply. (Good example) Here, the CS pin is pulled up to VCC. When turning off the power supply, wait at least 10msec before turning it on again. Failing to observe this condition can result in the internal circuit failing to be reset when the power supply is turned on. (Bad example) CS is LOW when the power supply is turned on or off In this case, because CS remains LOW, the EEPROM may perform erroneous operations or write erroneous data because of noise or other factors. ∗ Please be aware that the case shown in this example can also occur if CS input is HIGH-Z. VCC VCC GND VCC CS GND Good example Bad example (2) Noise countermeasures 1) SKnoise If noise occurs at the rise of the SK clock input, the clock is assumed to be excessive, and this can cause malfunction because the bits are out of alignment. 2) WC noise During a writing operation, noise at the WC pin can be erroneously judged to be data, and this can cause writing to be forcibly interrupted. 3) VCC noise Noise and surges on the power supply line can cause malfunction. We recommend installing a bypass capacitor between the power supply and ground to eliminate this problem. 15 Memory ICs (3) Canceling modes 1) Read commands BR9010 / BR9010F / BR9010FV / BR9020 / BR9020F / BR9040 / BR9040F SK CS 32 Clock DI Start bit 4 bits Operating code 4 bits Address 8 bits 16 bits DO Data D15 DO Cancel can be performed for the entire read mode space WC H or L Cancellation method: CS HIGH 2) Write commands SK CS 32 clock DI Start bit Operating code Address DO 4 bits 4 bits 8 bits Data D15 16 bits tE / W R/B a WC b c d Canceling methods a: Canceled by setting CS HIGH. The WC pin is not involved. b: If the WC pin goes HIGH for even a second, writing is forcibly interrupted. Cancellation occurs even if the CS pin is HIGH. At this point, data has not been written to the memory, so the data in the designated address has not yet been changed. c: The operation is forcibly canceled by setting the WC pin to HIGH or turning off the power supply (although we do not recommend using this method). The data in the designated address is not guaranteed and should be written once again. d: If CS is set to HIGH while the R / B signal is HIGH (following the tE / W timing), the IC is reset internally, and waits for the next command to be input. 16 Memory ICs BR9010 / BR9010F / BR9010FV / BR9020 / BR9020F / BR9040 / BR9040F •External dimensions (Units: mm) 9.3 ± 0.3 8 5 6.5 ± 0.3 3.0 ± 0.2 8 6.4 ± 0.3 4.4 ± 0.2 5 1 0.51Min. 4 7.62 3.2 ± 0.2 3.4 ± 0.3 0.1 0.3 ± 0.1 1.15 ± 0.1 1 4 2.54 0.5 ± 0.1 0°~15° (0.52) 0.65 0.22 ± 0.1 0.3Min. 0.1 DIP8 SSOP-B8 5.0 ± 0.2 8 6.2 ± 0.3 4.4 ± 0.2 5 1.5 ± 0.1 1 4 0.11 1.27 0.4 ± 0.1 0.3Min. 0.15 SOP8 0.15 ± 0.1 0.15 ± 0.1 17