BU1521GVW
Video Accessory IC Series
For portable image equipment
Upscaler IC
BU1521GVW
●
No.09069EAT02
Description
BU1521GVW upscales and interpolates images when upconverting to the HDTV (Maximum 1080P) format from the usual SDTV
(NTSC/PAL) format.
High quality IP change・up scale management is realized by the frame memory less operate.
It is the LSI which is the most suitable for the compact system of the mobile.
●
Features
1）Input format
480i or 576i(ITUR BT656) YCbCr 4:2:2(ITUR BT601) 8bit Digital Interface
2）Output Format
480i or 576i(ITUR BT656) YCbCr 4:2:2 8bit Digital Interface
480p or 576p(SMPTE 293・ITUR BT1358) YCbCr 4:2:2 16bit Digital Interface
1080/59.94i(SMPTE 274) YCbCr 4:2:2 16bit Digital Interface
1080/50i(SMPTE 274) YCbCr 4:2:2 16bit Digital Interface
1080/59.94p(SMPTE 274) YCbCr 4:2:2 16bit Digital Interface
1080/50p(SMPTE 274) YCbCr 4:2:2 16bit Digital Interface
3）IP conversion function
Conversion function from interlace to progressive
4）Upscale function
Horizontal direction: 720 pixels pass-through or upscaling to 1920 pixels
Vertical direction: up scaling to 480, 576, 540, and 1080 pixels
5）Filter function
5 × 5 filtering function over input data
Filter coefficient is programmable with registers
6）Register access
Register read/write through the SPI interface
Burst write/read support
7）Built-in PLL
Input frequency 27MHz
Output frequency 74.25MHz,74.175824MHz,148.5MHz,148.351648MHz
8）Power-down mode and through-mode support
Power-down mode can be controlled through STBY pin or register setting.
Through-mode can be selected by register setting.
9）Supply voltage
VDD(core voltage )1.15V～1.25V、AVDD(PLL)=2.7V~3.3V、
VDDIO1(SDTV input)=1.7V～3.6V、VDDIO2(control)=2.7V～3.3V、
VDDIO3(HDTV output)=1.7V～1.9V
10）Package
63 pin, BGA package (SBGA063W060, Size = 6 mm × 6 mm, 0.65 mm pitch)
●
Aplications
Digital Video Camera、Digital still camera , Video game, a portable DVD
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© 2009 ROHM Co., Ltd. All rights reserved.
1/15
2009.05 - Rev.A
Technical Note
BU1521GVW
●
Absolute Maximum Rating
Table. 1 Absolute maximum rating
Symbol
Rating
VDDIO1
-0.3～+4.2
VDDIO2
-0.3～+4.2
VDDIO3
-0.3～+4.2
AVDD
-0.3～+4.2
VDD
-0.3～+1.68
VIN1
-0.3～VDDIO1+0.3
VIN2
-0.3～VDDIO2+0.3
VIN3
-0.3～VDDIO3+0.3
Tstg
-25～+125
PD
330*1, 1200*2
Parameter
Supply voltage 1 (SD input)
Supply voltage 2 (Control)
Supply voltage 3 (HD output)
Supply voltage 4 (PLL)
Supply voltage 5 (CORE)
Input voltage 1
Input voltage 2
Input voltage 3
Storage temperature range
Power dissipation
Unit
V
V
V
V
V
V
V
V
ºC
mW
*1 IC only. In the case exceeding 25°C, 3.3 mW should be reduced at the rating 1C.
*2 When packaging a glass epoxy board of 114.3 × 76.2 × 1.6 mm. In the case exceeding 25°C, 12 mW should be reduced at t
* Has not been designed to withstand radiation.
* Operation is not guaranteed.
●
Operating Conditions
Table. 2 Operating conditions
Symbol
Min
Typ
VDDIO1
1.7
3.3
VDDIO2
2.7
3.0
VDDIO3
1.7
1.8
AVDD
2.7
3.0
VDD
1.15
1.2
Topr
-25
-
Parameter
Supply voltage 1 (SD input)
Supply voltage 2 (Control)
Supply voltage 3 (HD output)
Supply voltage 4 (PLL)
Supply voltage 5 (CORE)
Operating temperature range
●
he rating 1C.
Max
3.6
3.3
1.9
3.3
1.25
85
Unit
V
V
V
V
V
℃
Electrical Characteristics (DC Characteristics)
Table. 3 Electric characteristics
Parameter
Symbol
Specification
MIN
TYP
MAX
150
200
Unit
Operational current (CORE)
IDD1
Operational current (IO)
IDD2
-
40
80
mA
Operational current (CORE)
IDD3
-
15
20
mA
Operational current (IO)
IDD4
-
10
20
mA
Static current
Input “H” current
Input “L” current
IDDst
IIH
IIL
-
VIH1
V
Ordinary input (Including input mode of I/O pin)
Input “L” voltage 1
VIL1
-0.3
-
V
Ordinary input (Including input mode of I/O pin)
Input “H” voltage 2
VIH2
VDDIO1
*0.85
-
V
Hysteresis input
Input “L” voltage 2
VIL2
-0.3
-
V
Hysteresis input
Hysteresis voltage range 2
Vhys2
0.75
V
Hysteresis input
Output “H” voltage 1
VOH1
-
VDDIO2
V
IOH1=-1.0mA(DC)
Output “L” voltage 1
VOL1
-
0.4
V
IOL1=1.0mA(DC)
Output “H” voltage 2
VOH2
-
VDDIO3
V
IOH1=-1.0mA(DC)
Output “L” voltage 2
VOL2
VDDIO2
-0.4
0.0
VDDIO3
-0.2
0.0
800
10
10
VDDIO1
+0.3
VDDIO1
*0.2
VDDIO1
+0.3
VDDIO1
*0.15
-
μA
μA
μA
Input “H” voltage 1
-10
-10
VDDIO1
*0.8
When operated with HDCLK = 148.5 MHz
When operated with HDCLK = 148.5 MHz and
external capacitor of 5pF
When operated with DCLK = 27 MHz
When operated with HDCLK = 27 MHz and
external capacitor of 5pF
In standby mode
VIH=VDDIO1/2
VIL=GND
-
0.2
V
IOL1=1.0mA(DC)
-
mA
Conditions
SDOUT
SDOUT
HD output pin
HD output pin
(When not otherwise specified, under the conditions of VDD = 1.20 V, VDDIO1 = 3.3 V, VDDIO3 = 1.8 V, VDDIO2 = AVDD = 3.0 V, AVSS = GND = 0.0 V, and Ta = 25C)
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© 2009 ROHM Co., Ltd. All rights reserved.
2/15
2009.05 - Rev.A
Technical Note
BU1521GVW
●
Electrical Characteristics (AC Characteristics)
1.
3-wire serial interface timing
SCSB
tword
tWt
SCLK
0
1
5
6
7
0
1
5
6
7
twcs
SCSB
tcss
twsclk
tcsh
SCLK
tsds
tsdh
SDIN
tsdo
tsdo
SDOUT
Fig. 1 3-wire serial interface format
Symbol
twsclk
twcs
tcss
tsds
tcsh
tsdh
tsdo
tword
twt
Table. 4 3-wire serial interface format
Description
MIN
SCLK clock cycle
200
SCSB access interval
1
SCSB setup time
200
SDIN setup time
30
SCSB holding time
1
SDIN holding time
30
Time from trailing of the clock to the establishment of SDOUT
1 word write time
2.5
1 word write interval
1
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3/15
TYP
-
MAX
60
-
Unit
ns
μs
ns
ns
μs
ns
ns
μs
μs
2009.05 - Rev.A
Technical Note
BU1521GVW
2.
Image Data Input Timing
ｔCIP
ｔCIL
ｔCIH
CLKIN
DI0-15
ｔDIS ｔDIH
Fig. 2 Image Data Input Timing
Table. 5 Image Data Input Timing
Symbol
3.
Description
MIN
TYP
MAX
Unit
-
37.03
-
ns
tCIP
CLKIN Clock cycle
dCKI
CLKIN clock duty (tCIL/tCIP or tCIH/tCIP)
45
50
55
%
tDIS
Data setup time from the CLKIN rise
2
-
-
ns
tDIH
Data holding time from the CLKIN rise
3
-
-
ns
MIN
TYP
MAX
Unit
6.734
-
-
ns
Image Data Output Timing
ｔCOP
ｔCOL
ｔCOH
CLKOUT
DO0-15
ｔDOD
Fig. 3 Image Data Output Timing
Table. 6 Image Data Output Timing
Symbol
Description
tCOP
CLKOUT Clock cycle
dCKO
CLKOUT clock duty (tCOL/tCOP or tCOH/tCOP) *
45
-
55
%
tDOD
1
-
12
ns
tDOD
Time from the rise of CLKOUT to the establishment of DO0-15
(Wh
27MH
i of CLKOUT
)
Time from
the rise
to the establishment of DO0-15
1
-
5.734
ns
tJIT
(Wh PLL i
d)
Output jitter of CLKOUT (1 us cycle)
-
-
2
ns
* When PLL is used. When 27 MHz is output, the input clock duty is 50%.
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© 2009 ROHM Co., Ltd. All rights reserved.
4/15
2009.05 - Rev.A
Technical Note
BU1521GVW
●
Pin configuration diagram (Bottom View)
Fig. 4 Pin configuration diagram of BU1521GVW (Bottom view).
H
G
F
E
D
16
GND
19
DI15
21
DI1
24
SCSB
25
SDIN
28
STBY
30
DO1
32
GND
14
DI13
17
DI11
20
DI2
23
SCLK
26
SDOUT
29
CLKOUT
33
DO0
35
DO2
12
DI10
13
DI7
15
GND
22
RESETB
27
VDDIO2
31
VDD
36
DO4
37
DO3
9
DI14
10
DI0
11
GND
18
VDD
34
VDDIO3
38
GND
39
DO6
40
DO5
8
DI9
7
DI12
6
VDDIO1
2
AVDD
50
GND
43
VDD
42
DO8
41
DO7
4
DI5
63
GND
59
AVSS
54
VDDIO3
47
GND
45
DO10
44
DO9
3
DI6
1
DI3
61
DI8
58
GND
55
TEST0
52
DO14
49
DO12
46
DO11
64
GND
62
DI4
60
CLKIN
57
TEST2
56
TEST1
53
DO15
51
DO13
48
GND
1
2
3
4
5
6
7
8
C
B
A
Fig. 4 BU1521GVW Pin configuration diagram(Bottom View)
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© 2009 ROHM Co., Ltd. All rights reserved.
5/15
2009.05 - Rev.A
Technical Note
BU1521GVW
●
Pin Function
PIN No. Ball No. PIN Name
1
B2
DI3
2
D4
AVDD
3
B1
DI6
4
C2
DI5
5
-N.C *1
6
D3
VDDIO1
7
D2
DI12
8
D1
DI9
9
E1
DI14
10
E2
DI0
11
E3
GND
12
F1
DI10
13
F2
DI7
14
G1
DI13
15
F3
GND
16
H1
GND
17
G2
DI11
18
E4
VDD
19
H2
DI15
20
G3
DI2
21
H3
DI1
22
F4
RESETB
23
G4
SCLK
24
H4
SCSB
25
H5
SDIN
26
G5
SDOUT
27
F5
VDDIO2
28
H6
STBY
29
G6
CLKOUT
30
H7
DO1
31
F6
VDD
32
H8
GND
33
G7
DO0
34
E5
VDDIO3
35
G8
DO2
36
F7
DO4
37
F8
DO3
38
E6
GND
39
E7
DO6
40
E8
DO5
41
D8
DO7
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© 2009 ROHM Co., Ltd. All rights reserved.
In/Out
In
-In
In
--In
In
In
In
-In
In
In
--In
-In
In
In
In
In
In
In
Out
-In
Out
Out
--Out
-Out
Out
Out
-Out
Out
Out
Table. 7 BU1521GVW terminal function(1)
Init
Function Description
-3rd bit of SD input data
-Power Source for PLL
-6th bit of SD input data
-5th bit of SD input data
---Data input IO voltage (Typical 3.3 V)
-12th bit of SD input data
-9th bit of SD input data
-14th bit of SD input data
-0th bit of SD input data
-GND
-10th bit of SD input data
-7th bit of SD input data
-13th bit of SD input data
-GND
-GND
-11th bit of SD input data
-Core power supply (1.2 V)
-15th bit of SD input data
-2nd bit of SD input data
-1st bit of SD input data
-Reset pin (low active)
-3-wire serial I/F clock
-3-wire serial I/F chip select
-3-wire serial I/F data input
Low
3-wire serial I/F data output
-Control signal IO voltage (typically 3.3 V)
-IC stand-by control
Low
HD clock output
PD
1st bit of HD output pin
-Core power supply (1.2 V)
-GND
PD
0th bit of HD output pin
-Data output IO voltage (typically 1.8 V)
PD
2nd bit of HD output pin
PD
4th bit of HD output pin
PD
3rd bit of HD output pin
-GND
PD
6th bit of HD output pin
PD
5th bit of HD output pin
PD
7th bit of HD output pin
6/15
I/O Type
B
-B
B
--B
B
B
B
-B
B
B
--B
-B
B
B
B*2
B*2
B*2
B*2
C*3
-A
D
C
--C
-C
C
C
-C
C
C
I/O System
VDDIO1
-VDDIO1
VDDIO1
--VDDIO1
VDDIO1
VDDIO1
VDDIO1
-VDDIO1
VDDIO1
VDDIO1
--VDDIO1
-VDDIO1
VDDIO1
VDDIO1
VDDIO2
VDDIO2
VDDIO2
VDDIO2
VDDIO2
-VDDIO2
VDDIO3
VDDIO3
--VDDIO3
-VDDIO3
VDDIO3
VDDIO3
-VDDIO3
VDDIO3
VDDIO3
2009.05 - Rev.A
Technical Note
BU1521GVW
PIN No. Ball No. PIN Name
42
D7
DO8
43
D6
VDD
44
C8
DO9
45
C7
DO10
46
B8
DO11
47
C6
GND
48
A8
GND
49
B7
DO12
50
D5
GND
51
A7
DO13
52
B6
DO14
53
A6
DO15
54
C5
VDDIO3
55
B5
TEST0
56
A5
TEST1
57
A4
TEST2
58
B4
GND
59
C4
AVSS
60
A3
CLKIN
61
B3
DI8
62
A2
DI4
63
C3
GND
64
A1
GND
Table. 8 BU1521GVW terminal function(2)
In/Out
Init
Function Description
Out
PD
8th bit of HD output pin
--Core power supply (1.2 V)
Out
PD
9th bit of HD output pin
Out
PD
10th bit of HD output pin
Out
PD
11th bit of HD output pin
--GND
--GND
Out
PD
12th bit of HD output pin
--GND
Out
PD
13th bit of HD output pin
Out
PD
14th bit of HD output pin
Out
PD
15th bit of HD output pin
--Data output IO voltage (Typical 1.8 V)
In
-Test pin 0 (Connect to GND)
In
-Test pin 1 (Connect to GND)
In
-Test pin 2 (Connect to GND)
--GND
--GND for PLL
In
-SD clock input (27 MHz)
In
-8th bit of SD input data
In
-4th bit of SD input data
--GND
--GND
I/O Type
C
-C
C
C
--C
-C
C
C
-A
A
A
--B
B
B
---
I/O System
VDDIO3
-VDDIO3
VDDIO3
VDDIO3
--VDDIO3
-VDDIO3
VDDIO3
VDDIO3
-VDDIO3
VDDIO3
VDDIO3
--VDDIO1
VDDIO1
VDDIO1
---
Init column indicates pin status when released from reset. Low: L output
PD: Pull-down
*1: No balls
*2: Input suspend function is fixed to OFF by an internal signal
*3: No pull-down function
●
Block Diagram
DIN[15:0]
Filter(5x5)
Interpolator
Upscaler
Output
controller
DOUT[15:0]
CLKOUT
Memory CTL
CLKIN
(27MHz)
PLL
Line memory
Line memory
STBY
RESETB
Register Array
SPI I/F
SCLK,SCSB,SDIN,SDOUT
Fig. 5 BU1521GVW Block diagram
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© 2009 ROHM Co., Ltd. All rights reserved.
7/15
2009.05 - Rev.A
Technical Note
BU1521GVW
●
Functions Discpriction
1. Input format
The following is the input format for BU1521GVW
480i or 576i(ITUR BT656) YCbCr 4:2:2 8bit(ITUR BT601) Digital Interface
Table. 9 Input format
Format
Data
bit width
Pixel
clock (MHz)
Size including
blank (HxV)
Active
Size (HxV)
480/59.94i
8
27
858x525
720x(244/243)
576/50i
8
27
864x625
720x(288/288)
Standard
ITUR BT656-4
SYS2 register (0 × 12) setting allows applying whether Y data and CbCr data to be assigned to lower DI [7:0] or upper DI [15:8].
2.
Output format
480(I),576(I)
CLKIN[27MHz]
0x80
0x10
0x80
0x10
0x80
0x10
0xFF
0x00
0x00
0x80
Cb0
Y0
Cr0
Y1
Cb1
Y2
Cr1
Y3
Cb2
Y4
Blanking
480(I)=276Clocks
576(I)=288Clocks
SAV
Cr359
Y718
Cb359
Y719
0xFF
0x00
0x00
0x9D
0x80
0x10
0x80
0x10
0x80
0x10
EAV
0x80
0x10
0x80
0x10
0x80
0x10
0xFF
0x00
0x00
0x80
Cb0
Y0
Cr0
Y1
SAV
0xFF
0x00
0x00
0x9D
0x80
0x10
0x80
0x10
0x80
0x10
EAV
Input Data
(DI7-DI0)
720Pixels(Y=720,Cb/Cr=360)
[1440Clocks]
Clock/Line
480(I)=1716Clock
576(I)=1728Clock
The following is the output format for BU1521GVW:
480i or 576i(ITUR BT656) YCbCr 4:2:2 8bit (ITUR BT601)Digital Interface
480p or 576p(ITUR BT1358) YCbCr 4:2:2 16bit(ITUR BT601) Digital Interface
1080/59.94i(SMPTE 274) YCbCr 4:2:2 16bit(ITUR BT601) Digital Interface
1080/50i(SMPTE 274) YCbCr 4:2:2 16bit(ITUR BT601) Digital Interface
1080/59.94p(SMPTE 274) YCbCr 4:2:2 16bit(ITUR BT601) Digital Interface
1080/50p(SMPTE 274) YCbCr 4:2:2 16bit(ITUR BT601) Digital Interface
Table. 10 Output format
Format
Data
bit width
Pixel
Clock
Frequency
(MHz)
480/59.94i
8
27
858x525
720x(244/243)
576/50i
8
27
864x625
720x(288/288)
480/59.94p
16
27
858x525
720x483
576/50p
16
27
864x625
720x576
1080/59.94i
16
74.25/1.001
2200x1125
1920x1080
Blanking
Size including
Line (HxV)
Active Image
Size (HxV)
1080/50i
16
74.25
2640x1125
1920x1080
1080/59.94p
16
148.5/1.001
2200x1125
1920x1080
1080/50p
16
148.5
2640x1125
1920x1080
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© 2009 ROHM Co., Ltd. All rights reserved.
8/15
Standard
ITUR BT656-4
ITUR BT1358
SMPTE 293M
SMPTE 274
2009.05 - Rev.A
Technical Note
BU1521GVW
3. IP conversion, upscale function
BU1521GVW upscales and interpolates images when upconverting to output format.
Supported image data I/O conversion is shown in Table. 11 .
Only input size of 720 or upscale to 1920 are supported for the horizontal direction.
The edge of the upscaled image can be enhanced (3 levels) by changing the UPC_SEL register.
When upscaling the 480i input, upscaling is applied to 240 lines among the overall effective lines
Table. 11 Image data I/O conversion table
Output (HD)
Input (SD)
480/
59.94i
480/
59.94p
576/
50i
576/
50p
1080/
59.94i
1080/
50i
1080/
59.94p
1080/
50p
480/59.94i
○
○※
--
--
○
--
○
--
--
○
576/50i
--○
○
-○
* Immediately after reset and when standby mode is set, 480i becomes 480p.
4. Filter fiunction
BU1521GVW can apply 5 taps of filtering both horizontally and vertically.
5 taps of filter tap coefficients can be set independently on horizontal and vertical directions using filter coefficient registers (0x14–0x1B).
5 x 5 Filter tap coefficients = Horizontal filter tap coefficients x Vertical filter tap coefficients.
The values of the horizontal and vertical filter taps must be set to make the sum of the coefficients 64.
The initial value makes the filter invalid.
[Horizontal filter tap coefficients]
1
2
3
4
5
TH1
TH2
TH3
TH4
TH5
/64
[Vertical filter tap coefficients]
1
TV1
2
TV2
3
TV3
4
TV4
5
TV5
/64
[5 × 5 filter tap coefficients]
列番号
行番号
1
2
3
4
5
1
TH1*TV1
TH2*TV1
TH3*TV1
TH4*TV1
TH5*TV1
2
TH1*TV2
TH2*TV2
TH3*TV2
TH4*TV2
TH5*TV2
3
TH1*TV3
TH2*TV3
TH3*TV3
TH4*TV3
TH5*TV3
4
TH1*TV4
TH2*TV4
TH3*TV4
TH4*TV4
TH5*TV4
5
TH1*TV5
TH2*TV5
TH3*TV5
TH4*TV5
TH5*TV5
/4096
Fig. 6 5 × 5 filter tap coefficients
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© 2009 ROHM Co., Ltd. All rights reserved.
9/15
2009.05 - Rev.A
Technical Note
BU1521GVW
5. Register access
Registers are accessed by 3 wire serial interfaces (SCSB, SCLK, SDIN, SDOUT).
Burst write/read is supported; therefore, consecutive writing is possible.
Regular write sequence
The address 8 bits and data 8 bits should be written in this order.
Both address and data have MSB first.
SCSB
SCLK
0
SDIN
1
5
6
7
0
Address 8bit (MSB First)
7
1
5
6
7
WriteData 8bit (MSB First)
0 7
0
Fig. 7 Regular write sequence
Regular read sequence
For reading, the address of the register to be read out should be written in the SADR register (0 × 70), then SRDAT register (0 × 80) should be read
out. Both address and data have MSB first.
SCSB
SCLK
0
SDIN
1
5
6
7
0
1
5
6
7
0x80 (MSB First)
7
0
SDOUT
ReadData 8bit (MSB First)
7
0
Fig. 8 Regular read sequence
6. PLL
BU1521GVW has an integrated PLL to generate and output the clock for HD format from the 27 MHz pixel clock.
The PLL output frequency is selected and output is executed according to the output format only, by setting the output format to the register.
The input frequency is 27 MHz and the output frequency can be 74.25 MHz, 74.25/1.001 MHz, 148.5 MHz, or 148.5/1.001 MHz.
With 480i/576i output format, the 27 MHz input clock is output without going through the PLL.
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© 2009 ROHM Co., Ltd. All rights reserved.
10/15
2009.05 - Rev.A
Technical Note
BU1521GVW
● Typical application circuit
The typical application circuit of BU1521GVW is shown in Fig. 9 It does not guarantee
+1.8V
AVSS
GND
CLKIN
49
DO12
50
GND
51
DO13
DO14
DO15
52
10kΩ
53
54
VDDIO3
55
TESET0
10kΩ
56
TEST1
57
TEST2
58
GND
59
AVSS
60
61
DI8
CLKIN
62
DI4
63
GND
GND
64
GND
10kΩ
0.1uF
DI[15:0]
1
DI3
GND
48
2
AVDD
GND
47
0.1uF
3
DI6
DO11
46
GND
4
DI5
DO10
45
+3.3V
5
N.C
DO9
44
+3.0V
6
VDDIO1
VDD
43
0.1uF
7
DI12
DO8
42
GND
8
DI9
DO7
41
9
DI14
DO5
40
10
DI0
DO6
39
11
GND
GND
38
12
DI10
DO3
37
13
DI7
DO4
36
14
DI13
DO2
35
GND
BU1521GVW
15
GND
VDDIO3
34
16
GND
DO0
33
GND
+1.2V
0.1uF
GND
GND
+1.8V
0.1uF
GND
VDD
GND
32
DO1
31
30
STBY
VDDIO2
CLKOUT
29
28
27
SDOUT
26
SCSB
SCLK
RESETB
SDIN
25
24
23
22
DI1
21
DI15
DI2
20
VDD
19
18
17
DI11
GND
DO[15:0]
CLKOUT
RESETB
+1.2V
+3.3V
+1.2V
0.1uF
0.1uF
0.1uF
GND
GND
GND
SCLK
SCSB
SDIN
SDOUT
STBY
Note 1) Adjust the output damping resistance for CLKOUT and DO [15:0] with the line load.
Note 2) When the STBY pin is unused, pull it down with a 10 k resistor.
Fig. 9 BU1521GVW typical application circuit
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© 2009 ROHM Co., Ltd. All rights reserved.
11/15
2009.05 - Rev.A
Technical Note
BU1521GVW
● I/O pin equivalent circuit diagram
Fig. 10 An I/O pin equivalent circuit diagram.
Type
The equivalent circuit structure
Type
The equivalent circuit structure
Internal signal
Internal signal
VDDIO
VDDIO
VDDIO
To internal
A
To internal
B
GND
GND
GND
GND
Internal signal
GND
Input pin with Pull ｰ Down
Input pin with hysteresis and suspend
VDDIO
VDDIO
VDDIO
VDDIO
Internal signal
Internal signal
Internal signal
C
D
Internal signal
GND
GND
GND
GND
Internal signal
GND
Output pin with a built-in pull ｰ down
Output pin
Fig. 10 BU1521GVW I/O pin equivalent circuit diagram
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© 2009 ROHM Co., Ltd. All rights reserved.
12/15
2009.05 - Rev.A
Technical Note
BU1521GVW
●
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
Not for uses
Absolute Maximum Ratings
An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down
devices, thus making impossible to identify breaking mode such as a short circuit or an open circuit. If any special mode exceeding the
absolute maximum ratings is assumed, consideration should be given to take physical safety measures including the use of fuses, etc.
Operating conditions
These conditions represent a range within which characteristics can be provided approximately as expected. The electrical characteristics
are guaranteed under the conditions of each parameter.
Reverse connection of power supply connector
The reverse connection of power supply connector can break down ICs. Take protective measures against the breakdown due to the
reverse connection, such as mounting an external diode between the power supply and the IC’s power supply terminal.
Power supply line
Design PCB pattern to provide low impedance for the wiring between the power supply and the GND lines.
In this regard, for the digital block power supply and the analog block power supply, even though these power supplies has the same level
of potential, separate the power supply pattern for the digital block from that for the analog block, thus suppressing the diffraction of digital
noises to the analog block power supply resulting from impedance common to the wiring patterns. For the GND line, give consideration to
design the patterns in a similar manner.
Furthermore, for all power supply terminals to ICs, mount a capacitor between the power supply and the GND terminal. At the same time,
in order to use an electrolytic capacitor, thoroughly check to be sure the characteristics of the capacitor to be used present no problem
including the occurrence of capacity dropout at a low temperature, thus determining the constant.
GND voltage
Make setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state. Furthermore, check to
be sure no terminals are at a potential lower than the GND voltage including an actual electric transient.
Short circuit between terminals and erroneous mounting
In order to mount ICs on a set PCB, pay thorough attention to the direction and offset of the ICs. Erroneous mounting can break down the
ICs. Furthermore, if a short circuit occurs due to foreign matters entering between terminals or between the terminal and the power supply
or the GND terminal, the ICs can break down.
Operation in strong electromagnetic field
Be noted that using ICs in the strong electromagnetic field can malfunction them.
Inspection with set PCB
On the inspection with the set PCB, if a capacitor is connected to a low-impedance IC terminal, the IC can suffer stress. Therefore, be sure
to discharge from the set PCB by each process. Furthermore, in order to mount or dismount the set PCB to/from the jig for the inspection
process, be sure to turn OFF the power supply and then mount the set PCB to the jig. After the completion of the inspection, be sure to turn
OFF the power supply and then dismount it from the jig. In addition, for protection against static electricity, establish a ground for the
assembly process and pay thorough attention to the transportation and the storage of the set PCB.
Input terminals
In terms of the construction of IC, parasitic elements are inevitably formed in relation to potential. The operation of the parasitic element can
cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the input terminal. Therefore, pay thorough
attention not to handle the input terminals, such as to apply to the input terminals a voltage lower than the GND respectively, so that any
parasitic element will operate. Furthermore, do not apply a voltage to the input terminals when no power supply voltage is applied to the IC.
In addition, even if the power supply voltage is applied, apply to the input terminals a voltage lower than the power supply voltage or within
the guaranteed value of electrical characteristics.
Ground wiring pattern
If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND pattern from the
small-signal GND pattern and establish a single ground at the reference point of the set PCB so that resistance to the wiring pattern and
voltage fluctuations due to a large current will cause no fluctuations in voltages of the small-signal GND. Pay attention not to cause
fluctuations in the GND wiring pattern of external parts as well.
External capacitor
In order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a degradation in the
nominal capacitance due to DC bias and changes in the capacitance due to temperature, etc.
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© 2009 ROHM Co., Ltd. All rights reserved.
13/15
2009.05 - Rev.A
Technical Note
BU1521GVW
●
External Dimensional Drawing and Mark Drawing
U1521GVW
Top View
Lot.No.
Bottom View
Fig. 11 BU1521GVW Package external view (SBGA063W060)
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© 2009 ROHM Co., Ltd. All rights reserved.
14/15
2009.05 - Rev.A
Technical Note
BU1521GVW
●
Ordering part number
B
U
ROHM
model name
1
5
2
Part No.
1
G
V
W
Package
GVW: SBGA
E
2
Packaging and forming specification
E2: Embossed tape and reel
SBGA063W060
Embossed carrier tape(with dry pack)
Tape
Quantity
2000pcs
E2
Direction
(The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand.)
1234
Reel
(Unit:mm)
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© 2009 ROHM Co., Ltd. All rights reserved.
1234
1234
1Pin
1234
1234
1234
Direction of feed
※When you order , please order in times the amount of package quantity.
15/15
2009.05 - Rev.A
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.
The Products specified in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard
against the possibility of physical injury, fire or any other damage caused in the event of the
failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM
shall bear no responsibility whatsoever for your use of any Product outside of the prescribed
scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or
system which requires an extremely high level of reliability the failure or malfunction of which
may result in a direct threat to human life or create a risk of human injury (such as a medical
instrument, transportation equipment, aerospace machinery, nuclear-reactor controller,
fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of
any of the Products for the above special purposes. If a Product is intended to be used for any
such special purpose, please contact a ROHM sales representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may
be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to
obtain a license or permit under the Law.
Thank you for your accessing to ROHM product informations.
More detail product informations and catalogs are available, please contact us.
ROHM Customer Support System
http://www.rohm.com/contact/
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