HDMI Switch ICs
1 for input 1 output buffer with Termination sense correspondence (Sync with HPD_SINK)
BU16024KV
No.09063EDT03
●Description BU16024KV is 1 for input 1output HDMI/DVI buffer LSI. Each port supports 2.25Gbps. (HDMI 1.3a). This device control is simple. It requires only 3.3V and a few GPIO controls. Terminated resistors(50Ω) are integrated at each input port. When HPD_SINK is L, termination resistors are turned off. TMDS inputs are high impedance. This device is integrated equalization function and DDC buffer function, so It can adapt long cable.
●Features 1) Supports 2.25 Gbps signaling rate for 480i/p, 720i/p, and 1080i/p resolution to 12-bit color depth 2) Compatible with HDMI 1.3a 3) 5V tolerance to all DDC and HPD_SINK inputs 4) Integrated DDC buffer 5) Integrated switchable 50Ωreceiver termination 6) Integrated equalizer circuit to adapt long cable 7) Selectable output De-Emphasis Supports 8) High Impedance outputs when disabled 9) HBM ESD protection exceed 10kV 10) 3.3-V supply operation 11) 48-Pin VQFP package 12) ROHS compatible
●Applications Digital TV, DVD Player, Set-Top-Box, Audio Video Receiver, Digital Projector, DVI or HDMI Switch Box, PC
●Line up matrix
Part No. BU16020KV BU16018KV BU16027KV BU16006KV BU16024KV Power Supply (V) 3 to 3.6 3 to 3.6 3 to 3.6 3 to 3.6 3 to 3.6 ESD (KV) 10 10 10 10 10 Input (ch) HDMI 4ch HDMI 3ch HDMI 3ch HDMI 2ch HDMI 1ch Output (ch) HDMI 1ch HDMI 1ch HDMI 1ch HDMI 1ch HDMI 1ch Data rate (Gbps) 2.7 2.25 2.25 2.25 2.25 Hot Plug Control Yes Yes Yes Yes Yes Termination Sense Correspondence Yes Yes Yes Yes Yes Switching Method GPIO/I C GPIO GPIO GPIO 2
DDC Buffer Yes Yes Yes Yes Yes
Equalizer Yes (adaptive) Yes Yes Yes Yes
De emphasis Yes Yes Yes (Always ON) Yes (Always ON) Yes
Package VQFP100 VQFP80 VQFP64 VQFP64 VQFP48C
RoHS Yes Yes Yes Yes Yes
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●OUTSIDE DIMENSION CHART
Technical Note
BU16024KV
1PIN MARK
Lot No.
Figure 1-1 Outside dimension chart
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●BLOCK DIAGRAM
VSADJ OE PRE
VCC RINT
Technical Note
A4 B4
VCC RINT
TMDS Rx TMDS Driver
Y4 Z4
A3
TMDS Rx TMDS Driver
Y3 Z3
B3
VCC RINT
A2
TMDS Rx TMDS Driver
Y2
B2
VCC RINT
Z2
A1
TMDS Rx TMDS Driver
Y1
B1
Z1
SCL
SCL_SINK
SDA I2CEN SELREF
SDA_SINK
HPD
HPD_SINK(*)
(*) when HPD_SINK = “L”. Termination resistor is turned off.
Figure 2-1 Block Diagram
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●PIN EXPLANATION
Technical Note
1). PIN ASSIGNMENT (TOP VIEW)
SDA_SINK SCL_SINK
27
SELREF
VSADJ SCL
TEST3
36
35
34
33
32
31
30
29
28
26
25
TEST2
GND
GND
SDA
Vcc
Vcc
HPD GND B11 A11 Vcc B12 A12 GND B13 A13 Vcc NC
37 38 39 40 41 42 43 44 45 46 47 48 10 11 12 1 2 3 4 5 6 7 8 9
24 23 22 21
1 6024KV (48-pin VQFP)
20 19 18 17 16 15 14 13
HPD_SINK GND Z1 Y1 Vcc Z2 Y2 GND Z3 Y3 Vcc NC
TEST0
Figure 3-1 Pin Location
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TEST1
GND
GND
PRE
B14
A14
I2CEN
OEB
Vcc
Y4 Z4
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2). PIN LIST TERMINAL NAME No. B1, B2, B3, B4 39, 42, 45, 2 A1, A2, A3, A4 40, 43, 46, 3 Z1, Z2, Z3, Z4 22, 19, 16, 11 Y1, Y2, Y3, Y4 21, 18, 15, 10 HPD 37 HPD_SINK 24 SCL 34 SDA 33 SCL_SINK 27 SDA_SINK 28 VSADJ I2CEN SELREF TEST0, 1, 2, 3 N.C OEB PRE VCC GND 35 6 30 1, 12, 25, 36 13, 48 7 8 5, 14, 20, 29, 32, 41, 47 4, 9, 17, 23, 26, 31, 38, 44 I/O I I O O O I I/O I/O I/O I/O I I I I DESCRIPTION
Technical Note
I I -
TMDS Negative inputs TMDS Positive inputs TMDS Negative outputs TMDS Positive outputs Hot plug detector output Hot plug detector input DDC Bus clock line to source DDC Bus data line to source DDC Bus clock line to sink DDC Bus data line to sink TMDS Compliant voltage swing control(via 4.64k Ω to GND) I2C Repeater enable Low : High-Z High : Active SCL_SINK/SDA_SINK Output voltage select Open or GND connect (recommend) Open or GND connect (recommend) TMDS Output enable Low : Active High : High-Z TMDS Output de-emphasis adjustment Low : OFF High : ON Power supply Ground
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Technical Note
●
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
TMDS Input Stage VDD
TMDS Output Stage VDD VDD Y Z PRE OE
Control Input Stage VDD
50Ω
50Ω
A
B
10mA
R-Side I2C Input/Output Stage VDD SCL_SINK SDA_SINK SCL SDA
T-Side I2C Input/Output Stage VDD
Control Input Stage VDD VDD
HPD_SINK
VDD
SELREF
Control Input Stage VDD VDD
HPD Output Stage VDD
I2 CEN
HPD
Figure 4-1 I/O pin schematic diagram
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●ERECTRICAL SPECIFICATIONS 1.) ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range (unless otherwise noted) ITEM MIN. TYP. MAX. Supply voltage (Vcc) -0.3 4.0 SCL, SCL_SINK, SDA, SDA_SINK, -0.3 6.0 HPD_SINK input voltage Differential input voltage 2.5 4 PRE, I2CEN, SELREF, OEB input voltage -0.3 4 Power dissipation 1200 ※1 Storage temperature range -55 125 ※70mm×70mm×1.6mm glass epoxy board mount.(Reverse Cu occupation rate:15mm×15mm) When it’s used by than Ta=25℃, it’s reduced by 12mW/℃.
Technical Note
UNIT V V V V mW ℃
2.) RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER VCC Supply voltage TA Operating free-air temperature TMDS DIFFERENTIAL PINS (A/B) VID Receiver peak-to-peak differential input voltage VIC Input common mode voltage RVSADJ Resistor for TMDS compliant voltage swing range AVCC TMDS output termination voltage, see Figure 5-1 RT Termination resistance, see Figure 5-1 Signaling rate STATUS(HPD_SINK) VIH LVTTL High-level input voltage VIL LVTTL Low-level input voltage DDC PINS (SCL_SINK, SDA_SINK,SDA,SCL) VI(DDC) Input voltage
MIN. 3.0 0 150 VCC-0.6 4.6 3 45 0 2.4 GND GND
TYP. 3.3 4.64 3.3 50 -
MAX. 3.6 70 1560 VCC+0.01 4.68 3.6 55 2.25 5.5 0.8 5.5
UNIT V ℃ mVp-p V kΩ V Ω Gbps V V V
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3.) ELECTRICAL CHARACTERISTICS Over recommended operating conditions (unless otherwise noted) LIMITS
SYMBOL
Technical Note
PARAMETER
TEST CONDITIONS
MIN.
TYP.(1)
MAX.
UNIT
Icc
Supply current
PD
Power dissipation
VIH = Vcc,VIL = Vcc-0.4V,RVSADJ = 4.64kΩ RT = 50Ω,AVcc = 3.3V Am/Bm = 2.25 Gbps HDMI data pattern, m = 2,3,4 A1/B1 = 225 MHz clock VIH = Vcc,VIL = Vcc-0.4V,RVSADJ = 4.64kΩ RT = 50Ω,AVcc = 3.3V Am/Bm = 2.25Gbps HDMI data pattern, m = 2,3,4 A1/B1 = 225 MHz clock
-
140
170
mA
-
480
700
mW
TMDS DIFFERENTIAL PINS (A/B; Y/Z) Single-ended high-level output VOH voltage Single-ended low-level output VOL voltage Single-ended low-level swing VSWING voltage Overshoot of output differential VOD(O) voltage Undershoot of output VOD(U) differential voltage
AVcc 10 AVcc 600 AVcc = 3.3V, RT = 50Ω,PRE = 0V 400 PRE = Vcc Am/Bm = 225 Mbps HDMI data pattern, m = 2,3,4 A1/B1 = 225 MHz clock VIN = 2.9V
6% 12%
AVcc + 10 AVcc 400 600 15% 25%
mV mV mV 2xVswing 2xVswing
VOD(pp)
Steady state output differential voltage with de-emphasis
600
-
920
mVp-p
RINT ⊿VOC(SS)
Input termination resistance Change in steady-state common-mode output voltage between logic states
45 -
50 5
55 -
Ω mV
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Technical Note
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
LIMITS TYP.(1)
MAX
UNIT
DDC Input and output Tx (SDA_SINK , SCL_SINK ) IlkR① Input leak current, IlkT② IOHT IILT VOLT Input leak current, High-level output current Low-level input current Low-level output voltage
VI = 5.5V VI = Vcc VO = 3.6V VIL = GND RL = 4.7kΩ SELREF = NC SELREF= GND SELREF = Vcc SELREF = NC SELREF= GND SELREF = Vcc
-10 -10 -10 -10 0.43 0.58 0.73 -10 -10 -10 -10 2.4 0 -10 -10 -45 -45 10 5 -10
100 250 400 50 30 -
10 10 10 10 0.57 0.72 0.87 10 10 10 10 0.2 Vcc 0.4 10 10 45 45 100 80 10
uA uA uA uA V
Low-level input voltage below output low-level voltage Rx (SDA, SCL) Il kR① Input leak current Il kR② Input leak current I OHR High-level output current I I LR Low-level input current VOLR Low-level output voltage STATUS PINS ( HPD ) VOH (TT L) TTL High–level output voltage VOL (TT L) TTL Low–level output voltage CONTROL PINS (PRE, OEB) IIH High–level digital input current IIL Low–level digital input current VOLT - VIL CONTROL PINS (I2CEN, SELREF,) IIH IIL High–level digital input current Low–level digital input current
mV
VI = 5.5V VI = Vcc VO = 3.6V VIL = GND IOUT = 4mA IOH = - 8mA IOL = 8mA VIH = Vcc VIL = GND VIH = Vcc VIL = GND VIH = 5.5V VIH = Vcc VIL = GND
uA uA uA uA V V V uA uA uA uA uA uA uA
STATUS PINS (HPD_SINK) II H II L High–level digital input current Low–level digital input current
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Technical Note
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP.(1)
MAX.
UNIT
TMDS DIFFERENTIAL PINS (Y/Z) Propagation delay time tPLH low-high-level output Propagation delay time tPHL high-low-level output Differential output signal rise tr See Figure5-2, AVCC = 3.3V, time (20%-80%) RT = 50Ω, PRE =”H” Differential output signal fall tf time (20%-80%) tsk(p) Pulse skew (|tPHL - tPLH |) Intra-pair differential skew, see tsk(D) Figure5-3 DDC I/O PINS (SCL, SCL_SINK, SDA, SDA_SINK) Propagation delay time, tpdLHTR low-to-high-level output Tx to (DDC) Rx RL = 4.7KΩ CL = 100pF Propagation delay time, tpdHLTR high-to-low-level output Tx to (DDC) Rx Propagation delay time, tpdLHRT low-to-high-level output Rx to (DDC) Tx RL = 1.67KΩ CL = 400pF Propagation delay time, tpdHLRT high-to-low-level output Rx to (DDC) Tx tr Tx(DDC) Tx output Rise time RL = 4.7KΩ CL = 100pF tf Tx(DDC) Tx output Fall time tr Rx(DDC) Rx output Rise time CL=10pF tf Rx(DDC) Rx output Fall time CIO Input/output capacitance VI=0V STATUS PINS(HPD) Propagation delay time, tpdLH(HPD) low-to-high-level output from HPD_SINK to HPD Propagation delay time, tpdHL(HPD) high-to-low-level output from HPD_SINK to HPD Switch time from port select to tsx(HPD) the latest valid status of HPD
-
320 335 120 120 15 25
-
ps ps ps ps ps ps
-
650
-
ns
-
200
-
ns
-
500
-
ns
-
350 800 150 950 50 15
-
ns ns ns ns ns pF
CL=10pF
-
5
-
ns
CL=10pF
-
5
-
ns
CL=10pF
-
8
-
ns
Note: All typical values are at 25℃ and with a 3.3V supply.
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BU16024KV
●MEASUREMENT SYMBOL AND CIRCUIT
Technical Note
AVCC RT Z o = RT
TMDS Driver
RT
TMDS Receiver
Zo = RT
Figure 5-1 Termination for TMDS Output Driver
Vcc R INT R INT Y
TMDS Driver T MDS Receiver
RT VY VZ RT AV CC
VA
A V ID B VB
CL 0.5pF Z
V ID = V A - V B
V swing = V Y - V Z
DC Coupled VA VB VID VID(pp) VIC Vcc V Vcc-0.4 V 0.4 V 0V -0.4 V tPLH Vswing VOD(pp) tf VOC 80% VOD(O) 20% tr VOD(U) △VOC(SS) tPLH 100%
AC Coupled Vcc+0.2 V Vcc-0.2 V
0V Differential 0%
Figure 5-2 Timing Test Circuit and Definitions
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Technical Note
VY
VCH 50%
VZ
tsk(D)
VOL
Figure 5-3 Definition of Intra-Pair Differential Skew
VDD 2
HPD_SINK
VDD 2
HPD tpdHL(HPD) tpdHLRT(DDC) tpdLHRT(DDC) SDA_SINK SDA
1.5V 80% 20% 1.5V
tpdLH(HPD) tpdHLTR(DDC) tpdLHTR(DDC)
V IL 80% 20%
tfTX(DDC)
trTX(DDC)
tfRX(DDC) TX to RX
trRX(DDC)
RX to TX
Figure 5-4 DDC and HPD Timing Definitions
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1). Y and Z terminal ESD Diode notice. Y and Z terminals are connected ESD diode. When VCC+0.4 < AVCC. BU16024KV flow leak current from AVCC to VCC. In order to pass the compliance test. You must use mandatory application, refer Figure 6-1 for “Repeater” or “output Buffer” application. If you use “Repeater” or “output Buffer”
Technical Note
power down controler
10kΩ
AVCC
VCC
10kΩ
10kΩ TEST0
TEST2
TEST1
Figure 6-1 Leak current control
2). HPD_SINK Pull down resistance. HPD_SINK is a 5V tolerant structure shown in Figure 6-2. It needs some drive current to pull down HPD_SINK "H" to "L"(max10uA@HPD_SINK=2V). So to pull down HPD_SINK, please use 10kΩ(or under 10kΩ) resistor.
VCC BU16024KV
HPD_SINK
1 0kΩ
Figure 6-2 HPD_SINK I/O schematic
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3). About don’t use terminal. Unused TMDS input channel can be opened.
Technical Note
BU16024KV
Vcc R INT R INT RT A T MDS Receiver TMDS Driver Y AVcc
B
Z
RT
Figure 6-3 TMDS Input Fail-Safe Recommendation
Unused DDC Buffers of R side polled up to Vdd .
VCC 4.7k RSCL RSDA R T TSCL TSDA
Figure 6-4 DDC Buffers in BU16024KV
Open unused HPDn.
Figure 6-5 Open unused HPDn
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4). About serial connect notice. When HDMI sw output connect to other HDMI sw input like following application. There is possibility that. 1080p(12bit) image isn’t displayed. It’s depend on receiver IC characteristic. When system is required 1080p (12bit), Rohm doesn’t recommend serial connect application.
Technical Note
Vcc RINT RINT RINT
Vcc RINT RT
A
TMDS Receiver
TMDS Driver
Y
A
TMDS Receiver
TMDS Driver
Y Z
AVCC
B
Z
B
RT
Figure 6-6 serial connect notice
5). AC Coupling capable.
Figure 6-7 AC Coupling capable
6). Offset voltage appearance. If differential input is opened, offset voltage appear at differential output OE is set to low to avoid it.
Figure 6-8 Offset voltage avoid
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7). Limitation of Master and slave direction.
Technical Note
Figure 6-9 Limitation of Master and slave direction
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BU16024KV
Ordering part number
Technical Note
B U1 6 0 24
ROHM model name
KV
Package type VQFP48C
E2
Packaging and forming specification E2 =Reel-shaped emboss taping
Package specification
VQFP48C
9.0 ± 0.2 7.0 ± 0.1
36 37 25 24
Tape Quantity Embossed carrier tape 1500pcs E2
direction the at left when you ( The on the leftishand1pin of product is thethe upperthe right hand hold ) reel and you pull out tape on
9.0 ± 0.2
7.0 ± 0.1
48 1 12
13
0.75
1.6MAX
1PIN MARK
+0.05 0.145 -0.03
4 +6 –4
1.4 ± 0.05 0.1 ± 0.05
0.5 ± 0.1
0.08 S +0.05 0.22 -0.04 0.08
0.5±0.15
1.0±0.2
0.75
Direction of feed
M
1pin
Direction of feed
(Unit : mm)
Reel
∗ Order quantity needs to be multiple of the minimum quantity.
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Notice
Notes
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