BU1840AMUV-E2

Datasheet For 2Cell Solar, Synchronous Switch-Mode Charger IC BU1840AMUV ●General Description The BU1840AMUV device provides the best system to the product charged with 1cell Li-ion battery and 3cell Nickel-metal-hydride batteries using the 2cell, 3cell, and 4cell solar panel. It is possible to boost it according to the voltage of 2 cell solar panel with built-in the function to boost the low voltage input. Moreover, the solar battery maximum dissipation can be drawn out with built-in the peak power track function. It is possible to select the the switching frequency according to the terminal SEL. It is also possible to monitor the charging current by the I2C interface. Built in heat reckless driving protection (Thermal shutdown), decrease voltage protection, and input current protection for protection function ●Applications „ Solar mobile phone „ Solar audio „ Solar portable charger „ Solar LED illumination ●Package(s) VQFN024V4040 ●Features „ Synchronous Switch-Mode Charger for 2Cell Solar 400mA@Battery=3.7V,VIN=1V „ MPPT control voltage range：0.7V～1.5V „ Charging current completion voltage： 5.0V (hysteresis: 0.075V) „ Built in MPPT „ Switching frequency (160kHz,320kHz) „ Charging current monitor by I2C „ UVLO-detect Voltage:0.625V „ UVLO-release Voltage:0.700V „ Thermal Shutdown „ 24 pin VQFN024V4040 (4.1mm×4.1mm) W(Typ.) x D(Typ.) x H(Max.) 4.00mm x 4.00mm x 1.00mm VQFN024V4040 ●Typical Application Circuit(s) ●Typical Performance characteristics (VINMON=1.0V, OUTS=3.7V, Pin = 50mW ～ 2W) 100 SEL=GND Efficiency [%] SEL=VIN 90 80 70 10 ○Product structure：Silicon monolithic integrated circuit .www.rohm.com © 2012 ROHM Co., Ltd. All rights reserved. TSZ22111・14・001 100 Pin [mW] 1000 10000 ○This product is not designed protection against radioactive rays 1/14 TSZ02201-0Q1Q0AJ00130-1-2 2.AUG.2012 Rev.001 Datasheet BU1840AMUV ●Absolute maximum ratings (Ta=25℃) Parameter Symbol Ratings Unit Maximum applied voltage 1 Vmax1 7.0 V Maximum applied voltage 2 Vmax2 2.5 V Power dissipation1 Pd1 560 ｍW Power dissipation2 Pd2 1766 ｍW Operating temperature range Topr -30～+85 ℃ Storage temperature range Tstr -55～+150 ℃ Conditions VIO,SDA,SCL,SW1,2,3, ENB COREVDD,OUTP1,2,OUTPM,OUTS VIN,VINMON,V18,IMON,PCOMP, SEL,OSC 1layer(74.2x74.2mm)boad 2 (Surface heat radiation copper foil：6.28mm ) 4layer(74.2x74.2mm)boad 2 (1,4layer heat radiation copper foil：6.28mm ) 2 (2,3layer heat radiation copper foil：5500mm ) *1 When it is used by more than Ta=25℃, it is reduced by 5.6mW/℃. *1 *2 When it is used by more than Ta=25℃, it is reduced by 17.66mW/℃. ●Operating conditions (Ta=25℃) Parameter Symbol Ratings Unit Power supply voltage range 1 VCC1 0.625～1.98 V VIN terminal voltage Power supply voltage range 2 VCC2 1.7～5.5 V VIO terminal ●Electrical characteristics (Unless otherwise specified: Ta=25℃, VIN=1.0V) Rating Parameter Symbol Min. Typ. Max. Conditions Unit Conditions MPPT control minimum voltage MPPTL - - 0.7 V VINMON-monitor MPPT control maximum voltage MPPTH 1.5 - - V VINMON-monitor MPPT-VIN control voltage resolution PPTVT 12.5 25.0 37.5 mV UVLO Release Threshold VuvloR 0.6 0.7 0.8 V VIN-rising UVLO Detect Threshold VuvloD 0.575 0.625 0.675 V VIN-falling Vuvlohys 30 80 130 mV MPPT start up voltage Vst1 2.45 2.6 2.75 V Charging current completion voltage Vch2 4.93 5.0 5.07 V Circuit current 1 (VIN-CURRENT) ICC1 - - 1.0 mA Circuit current 2 (OUTS-CURRENT) ICC2 - - 2 uA ICC3 - - 4 uA UVLO Hysteresis COREVDD-monitor (hys=0.3V) OUTS-monitor RISING. (hysteresis=0.075V) ENB=1V, SW=VIN ENB=1V, OUTS,P=5.2V, COREVDD=3.7V ENB=0V, OUTS,P=5.2V COREVDD=3.7V Circuit current 3 (OUTS-CURRENT) Not-Switching Nch-SW ON registor Rnsw - 60 - mΩ Pch-SW ON registor Rpsw - 100 - mΩ Input over current limiter DCDC switching frequency 1 (SEL=VIN) DCDC switching frequency 2 (SEL=GND) Charging current voltage range VIlim 3.0 4.0. 5.0 A Fosc1 260 320 380 kHz OSC2OUT Fosc2 130 160 190 kHz OSC2OUT VImon 0 40 mV V(OUTPM)-V(OUTS) Charging current monitor accuracy 1 Imon1 0D 2B 49 Hex V(OUTPM)-V(OUTS)=0mV Charging current monitor accuracy 2 Imon2 88 A6 BF Hex V(OUTPM)-V(OUTS)=40mV Logic operating clock Logosc - 30 - kHz C4=100pF ENB ”H” level voltage Venh 1.1 - - V POWER-OFF ENB ”L” level voltage Venl 0 - 0.2 V POWER-ON .www.rohm.com © 2012 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 2/14 TSZ02201-0Q1Q0AJ00130-1-2 2.AUG.2012 Rev.001 Datasheet BU1840AMUV ●Electrical characteristics (Unless otherwise specified: Ta=25℃, VIO=1.8V) Item Symbol Min. Typ. Max. Unit L level input voltage VIL1 -0.3 - 0.25 × VIO V H level input voltage VIH1 - VIO +0.3 V Hysteresis width Vhys1 - - V Conditions 2 【I C input (SDA, SCL)】 L level output voltage (Sink current = 3mA) Input current 0.75 × VIO 0.05 × VIO VOL1 0 - 0.3 V Iin1 -3 - 3 μA SDA pin Pin voltage=0～VIO 2 ●I C BUS format 2 The writing/reading operation is based on the I C slave standard. ・Slave address A7 1 A6 1 A5 1 A4 0 A3 0 ・Bit Transfer SCL transfers 1-bit data during H. SCL cannot change signal of SDA during H at the time of bit transfer. If SDA changes while SCL is H, START conditions or STOP conditions will occur and it will be interpreted as a control signal. ・START and STOP condition When SDA and SCL are H, data is not transferred on 2 the I C- bus. This condition indicates, if SDA changes from H to L while SCL has been H, it will become START (S) conditions, and an access start, if SDA changes from L to H while SCL has been H, it will become STOP (P) conditions and an access end. ・Acknowledge It transfers data 8 bits each after the occurrence of START condition. A transmitter opens SDA after transfer 8bits data, and a receiver returns the acknowledge signal by setting SDA to L. A2 0 A1 1 R/W 1/0 SDA SCL SDA SDA a state of stability： It can change Data are effective SDA SCL S P STOP condition START condition DATA OUTPUT BY TRANSMITTER ・Protocol not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL 1 2 8 9 S START condition clock pulse for acknowledgement Legend The mastering side is a transmitter. The slave side is a receiver. A Acknowledge S Start condition The slave side is a transmitter. The mastering side is a receiver. A Unacknowledged P Stop condition .www.rohm.com © 2012 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 3/14 Sr Repetition start condition TSZ02201-0Q1Q0AJ00130-1-2 2.AUG.2012 Rev.001 Datasheet BU1840AMUV 1. Writing protocol A register address is transferred by the next 1 byte that transferred the slave address and the write-in command. The 3rd byte writes data in the internal register written in by the 2nd byte, and after 4th byte or, the increment of register address is carried out automatically. However, when a register address turns into the last address, it is set to 00h by the next transmission. After the transmission end, the increment of the address is carried out. *1 S X X X X X X X 0 A A7 A6 A5 A4 A3 A2 A1 A0 A D7 D6 D5 D4 D3 D2 D1 D0 A slave address register address *1 D7 D6 D5 D4 D3 D2 D1 D0 A P DATA DATA register address increment R/W=0(write) register address increment A=acknowledge(SDA LOW) A=not acknowledge(SDA HIGH) S=START condition P=STOP condition *1: Write Timing from master to slave from slave to master 2. Reading protocol It reads from the next byte after writing a slave address and R/W bit. The register to read considers as the following address accessed at the end, and the data of the address that carried out the increment is read after it. If an address turns into the last address, the next byte will read out 00h. After the transmission end, the increment of the address is carried out. S X X X X X X X 1 A D7 D6 D5 D4 D3 D2 D1 D0 A slave address D7 D6 D5 D4 D3 D2 D1 D0 A P DATA DATA register address increment R/W=1(read) register address increment A=acknowledge(SDA LOW) A=not acknowledge(SDA HIGH) S=START condition P=STOP condition from master to slave from slave to master 3. Multiple reading protocols After specifying an internal address, it reads by repeated START condition and changing the data transfer direction. The data of the address that carried out the increment is read after it. If an address turns into the last address, the next byte will read out 00h. After the transmission end, the increment of the address is carried out. S X X X X X X X 0 A A7 A6 A5 A4 A3 A2 A1 A0 A Sr X X X X X X X 1 A slave address register address slave address R/W=0(write) R/W=1(read) D7 D6 D5 D4 D3 D2 D1 D0 A D7D6 D5D4D3D2D1D0 A P DATA DATA register address increment from master to slave from slave to master register address increment A=acknowledge(SDA LOW) A=not acknowledge(SDA HIGH) S=START condition P=STOP condition Sr=repeated START condition ※ As for reading protocol and multiple reading protocols, please do A(not acknowledge) after doing the final reading operation. It stops with read when ending by A (acknowledge), and SDA stops in the state of Low when the reading data of that time is 0. However, this state returns usually when SCL is moved, data is read, and A (not acknowledge) is done. .www.rohm.com © 2012 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 4/14 TSZ02201-0Q1Q0AJ00130-1-2 2.AUG.2012 Rev.001 Datasheet BU1840AMUV ●Electrical Characteristics(Unless otherwise specified, Ta=25 ℃, VIO=1.8V) Item Symbol 【I2C BUS format】 SCL clock frequency fSCL Standard-mode Fast-mode Typ. Min. Typ. Max. Min. Typ. Max. - 100 - 0 1.3 - 400 - kHz LOW period of the SCL clock tLOW 0 4.7 HIGH period of the SCL clock tHIGH 4.0 - - 0.6 - - μs tHD;STA 4.0 - - 0.6 - - μs Set-up time for a repeated START condition tSU;STA 4.7 - - 0.6 - - μs Data hold time tHD;DAT 0 - 3.45 0 - 0.9 μs Data set-up time tSU;DAT 250 - - 100 - - ns Set-up time for STOP condition tSU;STO 4.0 - - 0.6 - - μs tBUF 4.7 - - 1.3 - - μs Hold time for a repeated START condition Bus free time between a STOP and START condition μs ●Timing diagram SDA t BUF t SU;DAT t LOW t HD;STA SCL t HD;STA t SU;STO t SU;STA t HD;DAT S Sr t HIGH P S D0 INITIAL ●Register Map Address Symbol Name R/W D7 D6 D5 D4 D3 D2 D1 00h SFTRST W - - - - - - - 01h ADCDATA R ADC DATA7 ADC DATA6 ADC DATA5 ADC DATA4 ADC DATA3 ADC DATA2 ADC DATA1 SFT RST ADC DATA0 Function 00h 00h Please input "0" to "-". In an empty address, there is a possibility of doing assign to the register for the test. The access to a register for the test and an undefined register is prohibited. The I2C control timing and the internal operation of IC timing become asynchronous relations when reading out data from the outside. I hope measures so as not to become a problem on the application as the agreement sequence is compare three times. .www.rohm.com © 2012 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 5/14 TSZ02201-0Q1Q0AJ00130-1-2 2.AUG.2012 Rev.001 Datasheet BU1840AMUV ●Register Explanation Address 00h Symbol Name SFTRST R/W D7 D6 D5 D4 D3 D2 D1 D0 INITIAL データ内容 W - - - - - - - SFT RST 00h ソフトウェア リセット制御入力 Bit name Bit SFTRST D0 Function RST (All registers are initialized.) 0 1 Normal Reset After initializing this all registers when SFTRST: D0=1 is done in WRITE, the value of this register returns to an initial value, too. Address 01h Symbol Name ADCDATA D7-D0: R/W R D7 ADC DATA7 D6 ADC DATA6 D5 ADC DATA5 D4 ADC DATA4 D3 ADC DATA3 D2 D1 D0 INITIAL ADC DATA2 ADC DATA 1 ADC DATA0 00h データ内容 ADCDATA7-0 8bitADC data（Initial 00h） Note）When not charging it (V18