BU2374FV-E2

Video Accessory ICs High Performance VCOs for Image Sampling BU2373FV,BU2374FV No.11069EBT07 ●Description General-purpose VCO Series ICs (BU2373FV and BU2374FV) have a built-in VCO and phase comparator and facilitate the configuration of a PLL system through the external connection of a LPF and frequency divider. Furthermore, in order to facilitate the loop constant settings of the PLL system, the application manual has been enhanced to ensure studies on the application. ●Features 1) The VCO enables midpoint settings within the range of oscillation through the external resistance. 2) The rising edge trigger type of phase comparator is built in. 3) Power-down mode setting can be made independently with the VCO and the phase comparator. 4) The VCO output frequency division can be selected on the SELECT pin. 5) Compact SSOP-B14 Package is adopted. ●Applications CRT, LCD monitor, and CD-RW ●Line up matrix BU2373FV VDD=3.0V Supply voltage VDD=3.3V VDD=5.0V VDD=3.0V Frequency range VDD=3.3V VDD=5.0V VCO-Frequency dividing mode Operating temperature range Package ○ ○ ○ 37～60MHz 37～65MHz 43～100MHz 1/2 -20～75℃ SSOP-B14 BU2374FV － ○ － － 37～60MHz － 1/4 -20～75℃ SSOP-B14 ●Absolute maximum ratings (Ta=25℃) Symbol Supply voltage Input voltage Storage temperature range Ratings -0.5～7.0 -0.5～VDD+0.5 -30～125 400 Unit V V ℃ mW VDD VIN Tstg Pd Power dissipation *1 *2 *3 *4 Operating is not guaranteed. In the case of exceeding Ta = 25℃, 4.0mW should be reduced per 1℃. The radiation-resistance design is not carried out. Power dissipation is measured when the IC is mounted to the printed circuit board. www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 1/18 2011.08 - Rev.B BU2373FV,BU2374FV ●Electrical characteristics ◎BU2373FV(Ta=25℃, VDD=3.0V, unless otherwise specified.) Limits Parameter Symbol Min. Typ. (VCO) VCO_IN input impedance Consumption current (while in normal mode) Consumption current (while in standby mode) Control voltage Oscillation range Bias resistor range Frequency sensitivity Output duty (PFD) Consumption current (while in normal mode) Consumption current (while in standby mode) *1 Design guaranteed figures Technical Note Max. Unit Conditions Zi Idd(VCO) Idd_st(VCO) VI frange Rbias β1 Duty 0.5 37 1.5 45 10 15 23 50 1 VDD-0.5 60 2.0 55 MΩ mA µA V MHz KΩ MHz/V % *1 With 60 MHz output VCO_INHIBIT=”H”, VCOIN=”L” *2 Measured at a voltage of 1/2 of VDD When 1 MHz is input to the FIN_A and B PFD_INHIBIT=”H”, FIN_A,B=”L” Idd(PFD) Idd_st(PFD) - 0.5 - 1 mA µA 37 MHz to 45 MHz when Rbias = 2.0 kΩ 50 MHz to 60 MHz when Rbias = 1.5 kΩ *2 Frequency sensitivity { f1 (VCOIN=2.0V)  f2 (VCOIN = 1.0V) } / 1.0V *3 If the SELECT pin is set to “H” and the output frequency is reduced to 1/2, the frequency range and the frequency sensitivity will be all reduced to 1/2. BU2373FV(Ta=25℃, VDD=5.0V, unless otherwise specified.) Parameter (VCO) VCO_IN input impedance Consumption current (while in normal mode) Consumption current (while in standby mode) Control voltage Oscillation range Bias resistor range Frequency sensitivity Output duty (PFD) Consumption current (while in normal mode) Consumption current (while in standby mode) *1 Design guaranteed figures Symbol Limits Min. Typ. Max. Unit Conditions Zi Idd(VCO) Idd_st(VCO) VI frange Rbias β1 Duty 0.5 43 1.6 45 10 25 25 50 1 VDD-0.5 100 2.5 55 MΩ mA µA V MHz KΩ MHz/V % *1 With 60 MHz output VCO_INHIBIT=”H”, VCOIN=”L” *2 Measured at a voltage of 1/2 of VDD When 1 MHz is input to the FIN_A and B PFD_INHIBIT=”H”, FIN_A&B=”L” Idd(PFD) Idd_st(PFD) - 1 - 1 mA µA 43 MHz to 77 MHz when Rbias = 2.5 kΩ 75 MHz to 100 MHz when Rbias = 1.6 kΩ *2 Frequency sensitivity { f1 (VCOIN = 3.5V)  f2 (VCOIN=1.5 V) } / 2.0V *3 If the SELECT pin is set to “H” and the output frequency is reduced to 1/2, the frequency range and the frequency sensitivity will be all reduced to 1/2. www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 2/18 2011.08 - Rev.B BU2373FV,BU2374FV ◎BU2374FV(Ta=25℃, VDD=3.3V, unless otherwise specified.) Limits Parameter Symbol Min. Typ. (VCO) VCO_IN input impedance Consumption current (while in normal mode) Consumption current (while in standby mode) Control voltage Oscillation range Bias resistor range Frequency sensitivity Output duty (PFD) Consumption current (while in normal mode) Consumption current (while in standby mode) *1 Design guaranteed figures Technical Note Max. Unit Conditions Zi Idd(VCO) Idd_st(VCO) VI frange Rbias β1 Duty 0.5 37 2.0 45 10 12.5 23 50 1 VDD-0.5 60 3.0 55 MΩ mA µA V MHz KΩ MHz/V % *1 With 50 MHz output VCO_INHIBIT=”H”, VCOIN=”L” *2 Measured at a voltage of 1/2 of VDD When 1 MHz is input to the FIN_A and B PFD_INHIBIT=”H”, FIN_A, B=”L” Idd(PFD) Idd_st(PFD) - 0.5 - 1 mA µA 37 MHz to 54 MHz when Rbias =2 .0 kΩ 53 MHz to 60 MHz when Rbias = 3.0 kΩ *2 Frequency sensitivity { f1 (VCOIN = 2.0V)  f2 (VCOIN = 1.0 V) } / 1.0V *3 If the SELECT pin is set to “H” and the output frequency is reduced to 1/4, the frequency range and the frequency sensitivity will be all reduced to 1/4. www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 3/18 2011.08 - Rev.B BU2373FV,BU2374FV ●Reference data (BU2373FV－Power Voltage Fluctuation Data) 55 54 53 52 Duty：Duty[%] 51 50 49 48 47 46 45 -25 0 25 50 75 Temperature：T[℃] 100 Duty：Duty[%] 55 54 Technical Note 100 52 51 50 49 48 47 46 45 -25 0 25 50 Temperature：T[℃] 75 100 Output Frequency：f[MHz] 53 80 60 40 From top:VDD=3.15V VDD=3.00V VDD=2.85V From top:VDD=3.15V VDD=3.00V VDD=2.85V 20 From top: VDD=3.15V VDD=3.00V VDD=2.85V 0.0 0.5 1.0 1.5 2.0 2.5 Control Voltage：VI[V] 3.0 3.5 0 Fig.1 Control Vole  Output Frequency (VDD=3.0V,Rbias=1.5KΩ,Ta=25℃) Fig.2 Control Voltage – Output Frequency (VDD=3.0V,Rbias=1.8KΩ,Ta=25℃) Fig.3 Control Voltage – Output Frequency (VDD=3.0V,Rbias=2.0KΩ,Ta=25℃) 100 100 100 Output Frequency：f[MHz] Output Frequency：f[MHz] Output Frequency：f[MHz] 80 80 80 60 60 60 40 20 From top: VDD=3.45V VDD=3.30V VDD=3.15V 40 40 20 From top:VDD=3.45V VDD=3.30V VDD=3.15V 20 From top:VDD=3.45V VDD=3.30V VDD=3.15V 0 0.0 0.5 1.0 1.5 2.0 2.5 Control Voltage：VI[V] 3.0 3.5 0 0.0 0.5 1.0 1.5 2.0 2.5 Control Voltage：VI[V] 3.0 3.5 0 0.0 0.5 1.0 1.5 2.0 2.5 Control Voltage：VI[V] 3.0 3.5 Fig.4 Control Voltage – Output Frequency (VDD=3.3V,Rbias=1.6KΩ,Ta=25℃) Fig.5 Control Voltage – Output Frequency (VDD=3.3V,Rbias=2.0 KΩ,Ta=25℃) Fig.6 Control Voltage – Output Frequency (VDD=3.3V,Rbias=2.2 KΩ,Ta=25℃) 150 125 Output Frequency：f[MHz] Output Frequency：f[MHz] 100 75 50 25 0 0.0 1.0 2.0 3.0 4.0 Control Voltage：VI[V] 5.0 150 125 100 75 50 25 0 0.0 1.0 2.0 3.0 4.0 Control Voltage：VI[V] 5.0 Output Frequency：f[MHz] 150 125 100 75 50 25 0 0.0 1.0 2.0 3.0 4.0 5.0 Control Voltage：VI[V] From top:VDD=5.25V VDD=5.00V VDD=4.75V From top:VDD=5.25V VDD=5.00V VDD=4.75V From top:VDD=5.25V VDD=5.00V VDD=4.75V Fig.7 Control Voltage – Output Frequency (VDD=5.0V,Rbias=1.6KΩ,Ta=25℃) Fig.8 Control Voltage – Output Frequency (VDD=5.0V,Rbias=2.4KΩ,Ta=25℃) Fig.9 Control Voltage – Output Frequency (VDD=5.0V,Rbias=2.7KΩ,Ta=25℃) www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 4/18 2011.08 - Rev.B BU2373FV,BU2374FV ●Reference data (BU2373FV－Temperature Fluctuation Data) 100 100 100 Technical Note Output Frequency：f[MHz] Output Frequency：f[MHz] Output Frequency：f[MHz] 80 80 80 60 60 60 40 40 40 20 From top:T=25℃ T=-20℃ T=75℃ 20 From top:T=75℃ T=25℃ T=-20℃ 20 From top:T=75℃ T=25℃ T=-20℃ 0 0.0 0.5 1.0 1.5 2.0 Control Voltage：VI[V] 2.5 3.0 0 0.0 0.5 1.0 1.5 2.0 2.5 Control Voltage：VI[V] 3.0 0 0.0 0.5 1.0 1.5 2.0 2.5 Control Voltage：VI[V] 3.0 Fig.10 Control Voltage – Output Frequency (VDD=3.0V,Rbias=1.5KΩ) Fig.11 Control Voltage – Output Frequency (VDD=3.0V,Rbias=1.8KΩ) Fig.12 Control Voltage – Output Frequency (VDD=3.0V,Rbias=2.0 KΩ) 100 100 100 Output Frequency：f[MHz] Output Frequency：f[MHz] 60 60 Output Frequency：f[MHz] 80 80 80 60 40 40 40 20 From top:T=75℃ T=25℃ T=-20℃ 20 From top:T=75℃ T=25℃ T=-20℃ 20 From top:T=75℃ T=25℃ T=-20℃ 0 0.0 0.5 1.0 1.5 2.0 2.5 Control Voltage：VI[V] 3.0 3.5 0 0.0 0.5 1.0 1.5 2.0 2.5 Control Voltage：VI[V] 3.0 3.5 0 0.0 0.5 1.0 1.5 2.0 2.5 Control Voltage：VI[V] 3.0 3.5 Fig.13 Control Voltage – Output Frequency (VDD=3.3V,Rbias=1.6KΩ) Fig.14 Control Voltage – Output Frequency (VDD=3.3V,Rbias=2.0KΩ) Fig.15 Control Voltage – Output Frequency (VDD=3.3V,Rbias=2.2KΩ) 150 125 Output Frequency：f[MHz] 100 75 50 25 0 0.0 1.0 2.0 3.0 4.0 Control Voltage：VI[V] 5.0 150 125 Output Frequency：f[MHz] 100 75 50 25 0 0.0 1.0 2.0 Output Frequency：f[MHz] 150 125 100 75 50 25 0 0.0 1.0 From top:T=75℃ T=25℃ T=-20℃ From top:T=75℃ T=25℃ T=-20℃ 3.0 4.0 5.0 Control Voltage：VI[V] From top:T=75℃ T=25℃ T=-20℃ 2.0 3.0 4.0 Control Voltage：VI[V] 5.0 Fig.16 Control Voltage – Output Frequency (VDD=5.0V,Rbias=1.6KΩ) Fig.17 Control Voltage– Output Frequency (VDD=5.0V,Rbias=2.4KΩ) Fig.18 Control Voltage – Output Frequency (VDD=5.0V,Rbias=2.7KΩ) www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 5/18 2011.08 - Rev.B BU2373FV,BU2374FV ●Reference data (BU2373FV－Recommended Oscillation Range, Frequency - Frequency Sensitivity) 65 Technical Note Recommended Oscillation Range”H” 60 Output Frequency：f[MHz] 35 ： Frequency Sensitivity ß1[MHz/v] 30 Recommended Oscillation Range”H” Output Frequency：f[MHz] 30 25 20 15 10 5 0 55 50 45 40 35 30 1.5 1.6 1.7 1.8 1.9 Bias Resistor:Rbias[KO] 2.0 25 20 Recommended Oscillation Range”L” Recommended Oscillation Range”L” 15 1.5 1.6 1.7 1.8 1.9 Bias Resistor:Rbias[KO] 2.0 35 40 45 50 55 Output Frequency：f[MHz] 60 Fig.19 Bias Resistance - Recommended Oscillation Range (VDD=3.0V, Select=”L”) Fig.20 Bias Resistance - Recommended Oscillation Range (VDD=3.0V, Select=”H”) Fig.21 Output Frequency - Frequency Sensitivity (VDD=3.0V, Select=”L”) 70 65 Output Frequency：f[MHz] 60 55 50 45 40 35 35 30 Recommended Oscillation Range”H” Output Frequency：f[MHz] 30 Recommended Oscillation Range”H” ： Frequency Sensitivity ß1[MHz/v] 25 20 15 10 5 0 25 20 Recommended Oscillation Range”L” 30 1.6 1.7 1.8 1.9 2.0 2.1 Bias Resistor:Rbias[KO] 2.2 Recommended Oscillation Range”L” 15 1.6 1.7 1.8 1.9 2.0 2.1 Bias resistor:Rbias[KO] 2.2 35 40 45 50 55 60 Output Frequency：f[MHz] 65 Fig.22 Bias Resistance - Recommended Oscillation Range (VDD=3.3V, Select=”L”) Fig.23 Bias Resistance Recommended Oscillation Range (VDD=3.3V, Select=”H”) Fig.24 Output Frequency - Frequency Sensitivity (VDD=3.3V, Select=”L”) 110 100 Output Frequency：f[MHz] 90 80 70 60 50 40 30 1.6 55 Recommended Oscillation Range”H” Output Frequency：f[MHz] 45 Recommended Oscillation Range”H” ： Frequency Sensitivity ß1[MHz/v] 30 25 20 15 10 5 0 40 50 60 70 80 90 Output Frequency：f[MHz] 100 35 25 Recommended Oscillation Range”L” 15 1.6 1.8 2.0 2.2 2.4 Resistor:Rbias[KO] 2.6 Recommended Oscillation Range”L” 1.8 2.0 2.2 2.4 Bias Resistor:Rbias[KO] 2.6 Fig.25 Bias Resistance – Recommended Oscillation Range (VDD=5.0V, Select=”L”) Fig.26 Bias Resistance – Recommended Oscillation Range (VDD=5.0V, Select=”H”) Fig.27 Output Frequency - Frequency Sensitivity (VDD=5.0V, Select=”L”) www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 6/18 2011.08 - Rev.B BU2373FV,BU2374FV ●Reference data (BU2374FV－Power Voltage Fluctuation Data) 100 100 100 Technical Note Output Frequency：f[MHz] Output Frequency：f[MHz] 60 60 Output Frequency：f[MHz] 80 80 80 60 40 From top:VDD=3.45V VDD=3.30V VDD=3.15V 40 20 20 From top:VDD=3.45V VDD=3.30V VDD=3.15V 40 20 From top:VDD=3.45V VDD=3.30V VDD=3.15V 0 0.0 0.5 1.0 1.5 2.0 2.5 Control Voltage：VI[V] 3.0 3.5 0 0.0 0.5 1.0 1.5 2.0 2.5 Control Voltage：VI[V] 3.0 3.5 0 0.0 0.5 1.0 1.5 2.0 2.5 Control Voltage：VI[V] 3.0 3.5 Fig.28 Control Voltage  Output Frequency (VDD=3.3V,Rbias=2.0KΩ,Ta=25℃) Fig.29 Control Voltage  Output Frequency (VDD=3.3V,Rbias=2.4 KΩ,Ta=25℃) Fig.30Control Voltage  Output Frequency (VDD=3.3V,Rbias=3.0KΩ,Ta=25℃) ●Reference data (BU2374FV－Temperature Fluctuation Data) 100 100 100 Output Frequency：f[MHz] 60 60 Output Frequency：f[MHz] Output Frequency：f[MHz] 80 80 80 60 40 40 40 From top:T=75℃ T=25℃ T=-20℃ 20 From top:T=75℃ T=25℃ T=-20℃ 20 From top:T=75℃ T=25℃ T=-20℃ 20 0 0.0 0.5 1.0 1.5 2.0 2.5 Control Voltage：VI[V] 3.0 3.5 0 0.0 0.5 1.0 1.5 2.0 2.5 Control Voltage：VI[V] 3.0 3.5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Control Voltage：VI[V] Fig.31 Control Voltage  Output Frequency (VDD=3.3V,Rbias=2.0KΩ) Fig.32 Control Voltage  Output Frequency (VDD=3.3V,Rbias=2.4KΩ) Fig.33 Control Voltage  Output Frequency (VDD=3.3V,Rbias=3.0KΩ) ●Reference data (BU2374FV－Recommended Oscillation Range, Frequency - Frequency Sensitivity) 100 25 50 Frequency sensitivity: ß1[MHz/v] 45 40 35 30 25 20 15 10 5 0 2.0 2.2 2.4 2.6 2.8 Resistor:Rbias[KO] 3.0 Output Frequency：f[MHz] Recommended Oscillation Range”H” Output Frequency：f[MHz] 80 20 Recommended Oscillation Range”H” 60 15 40 10 20 Recommended Oscillation Range”L” 5 Recommended Oscillation Range”L” 0 2.0 2.2 2.4 2.6 2.8 Resistor:Rbias[KO] 3.0 0 35 40 45 50 55 60 Frequency: f[MHz] Fig.34 Bias Resistance – Recommended Oscillation Range (VDD=3.3V, Select=”L”) Fig.35 Bias Resistance – Recommended Oscillation Range (VDD=3.3V, Select=”H”) Fig.36 Output Frequency - Frequency Sensitivity (VDD=3.3V, Select=”L”) www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 7/18 2011.08 - Rev.B BU2373FV,BU2374FV ●Reference data (BU2373FV－VCO Free-run Output Characteristics) RBW:30kHz VBW:30kHz Technical Note 10dB/div 100kHz/div 1V/div 5nsec/div 1V/div 500psec/div Fig.37 Spectrum Waveform (VDD=3.0V,Select=”L”,Output=50MHz) RBW:30kHz VBW:30kHz Fig.38 Output Waveform (VDD=3.0V,Select=”L”,Output=50MHz) Fig.39 Period-Jitter Waveform (VDD=3.0V,Select=”L”,Output=50MHz) 10dB/div 1V/div 100kHz/div 5nsec/div 1V/div 500psec/div Fig40 Spectrum Waveform (VDD=3.3V,Select=”L”,Output=50MHz) RBW:30kHz VBW:30kHz Fig.41 Output Waveform (VDD=3.3V, Select=”L”, Output=50MHz) Fig.42 Period-Jitter Waveform (VDD=3.3V,Select =”L”, Output=50MHz) 10dB/div 100kHz/div 1V/div 1V/div 2nsec/div 500psec/div Fig.43 Spectrum Waveform (VDD=5.0V,Select=”L”,Output=75MHz) Fig.44 Output Waveform (VDD=5.0V,Select=”L”,Output=75MHz) Fig.45 Period-Jitter Waveform (VDD=5.0V,Select=”L”,Output=75MHz) ●Reference data (BU2374FV－VCO Free-run Output Characteristics) RBW:30kHz VBW:30kHz 10dB/div 100kHz/div 1V/div 1V/div 5nsec/div 500psec/div Fig.46 Spectrum Waveform (VDD=3.3V,Select=”L”,Output=50MHz) Fig.47 Output Waveform (VDD=3.3V,Select=”L”,Output=50MHz) Fig.48 Period-Jitter Waveform (VDD=3.3V,Select=”L”,Output=50MHz) www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 8/18 2011.08 - Rev.B BU2373FV,BU2374FV ●Block diagram (BU2373FV) Technical Note 2PIN： SELECT Through or 1/2 Level Shifter 13PIN：BIAS ＶＣＯ 12PIN：VCO_IN 3PIN： VCO_OUT 1:LOGIC_VDD 2:SELECT 3:VCO_OUT 4:FIN_A 5:FIN_B 6:PFD_OUT 7:LOGIC_GND 14:VCO_VDD 13:BIAS (BU2374FV) BU2373FV SSOP-B14 BU2374FV SSOP-B14 4PIN：FIN_A 12:VCO_IN 11:VCO_GND 10:VCO_INHIBIT 9:PFD_INHIBIT 8:TEST 5PIN： FIN_B 10PIN：VCO_INHIBIT Pmos Gate 6PIN：PFD_OUT Nmos Gate Phase Detector 9PIN：PFD_INHIBIT Fig.49 2PIN： SELECT Through or 1/4 Level Shifter 13PIN：BIAS ＶＣＯ 12PIN：VCO_IN 1:LOGIC_VDD 2:SELECT 3:VCO_OUT 4:FIN_A 5:FIN_B 6:PFD_OUT 7:LOGIC_GND 14:VCO_VDD 13:BIAS 12:VCO_IN 11:VCO_GND 10:VCO_INHIBIT 9:PFD_INHIBIT 8:TEST 3PIN： VCO_OUT 4PIN：FIN_ A 5PIN： FIN_B 10PIN：VCO_INHIBIT Pmos Gate 6PIN：PFD_OUT Nmos Gate Phase Detector 9PIN：PFD_INHIBIT Fig.50 www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 9/18 2011.08 - Rev.B BU2373FV,BU2374FV ●Pin assignment function PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PIN name LOGIC_VDD SELECT VCO_OUT FIN-A FIN-B PFD_OUT Function Technical Note Power supply for the internal Logic and the VCO output, which should be separated from power supply for the VCO_VDD (analog block). VCO output frequency dividing mode selection pin. H: Frequency dividing output, L: Through output VCO output pin. If the VCO_INHIBIT is set to “H”, the VCO_OUT will be fixed to L. Reference frequency input pin VCO block frequency dividing input pin, which inputs after the VCO output frequency is divided through the external counter. Phase comparator output pin. If the PFD_INHIBIT is set to “H”, the PFD_OUT will be set to Hi-Z output. LOGIC_GND GND for the internal Logic and the VCO output Test mode pin, which is normally used with set to OPEN or fixed to L. Equipped with Pull-down resistor. Phase comparator inhibit control pin. PFD_INHIBIT If the PFD_INHIBIT is set to “H”, the PFD_OUT will be set to Hi-Z output. VCO inhibit control pin. VCO_INHIBIT If the VCO_INHIBIT is set to “H”, the VCO_OUT will be fixed to L output. TEST VCO_GND VCO_IN BIAS VCO_VDD GND for VCO (Analog block GND) VCO control pin, to which loop filter output for the PLL system is connected due to frequency control on normal system. Bias current setting pin for the shift of VCO oscillation range. A resistor is connected to the VCO_VDD for the control of bias current. VDD for VCO (power supply for analog block) ●Example of application circuit Please separate completely the bypass capacitor between an analog power supply and GND from a digital power supply and GND. Please insert an about 0.01µF bypass capacitor near the pin as much as possible. Please adjust so that the voltage of VCO_IN is set to 1/2VDD. 1 H:VCO_OUT divide 2 L： VCO_OUT normal LOGIC_VDD VCO_VDD 14 SELECT BIAS 13 R2 recommend a lug lead filter. 3 VCO_OUT VCO_IN 12 C1 R1 C2 11 H:VCO_OUT disable 4 FIN_A VCO_GND 1/N Divider 5 FIN_B VCO_INHIBIT 10 L:VCO_OUT enable H:PFD_OUT disable 6 PFD_OUT PFD_INHIBIT 9 L:PFD_OUT enable 7 LOGIC_GND TEST 8 The bypass capacitor between a digital power supply and GND should set aside an analog power supply and GND. Please insert an about 0.01uF bypass capacitor near the pin as much as possible. Fig.51 * * It is recommended to use bypass capacitors of good high-frequency characteristics. It is recommended to apply power supply in the LOGIC_VDD and LOGIC_GND circuits for the SELECT. PFD_INHIBIT, and VCO_INHIBIT control pins. www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 10/18 2011.08 - Rev.B BU2373FV,BU2374FV Technical Note ●Description of operations VCO Block Our VCO block consists of ring oscillators using 5-step reverse Amp. Setting the 2PIN: SELECT to “H” makes it possible to set the system to output frequency dividing mode. (The frequency is divided to 1/2 on the BU2373FV, while 1/4 on the BU2374FV.) 50% of the frequency is guaranteed even to the duty at this time. Furthermore, setting the 10Pin: VCO_INHIBIT to “H” makes it possible to set the system to power-down mode. While in power-down mode, the VCO_OUT output is fixed to “L”, thus achieving reduction in Analog consumption current approximately by 80%. In addition, through the adjustment of external resistance value for the BIAS terminal on 13Pin, the fine adjustment of output frequency can be made. (VCO I/O Characteristics) frequency (MHz) It is possible to adjust center frequency with biasresistor 0 Fig.52 VCO_IN (V) * The VCO built in the BU2373FV has been designed to provide the lowest frequency sensitivity when using the VCO_IN at about VDD/2. To make use of the VCO, it is recommended to adjust the BIAS resistance so that the voltage of the VCO_IN will reach VDD/2. (Configuration of VCO Block) VCOIN Bias block Level Shifter VCO_INHIBIT L 1/2 1/2 H SELECT VCO_OUT Fig.53 www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 11/18 2011.08 - Rev.B BU2373FV,BU2374FV Technical Note Phase Comparator Our phase comparator is of rising edge detection type. This phase comparator shows the characteristics shown below. (1) The phase comparator outputs an error pulse (UP signal) after the rising edge is detected at the FIN-A until the rising edge is detected at the FIN-B, and then it is reset. (2) The phase comparator outputs an error pulse (DOWN signal) after the rising edge is detected at the FIN-B until the rising edge is detected at the FIN-A, and then it is reset. Furthermore, setting the 9Pin: PFD_INHIBIT to “H” makes it possible to set the system to power-down mode. While in power-down mode, the PFD_OUT outputs high impedance. In other words, it is brought to reset state with the Logic power supply. (A leak current of 1 A or less is guaranteed.) (I/O Characteristics of Phase Comparator) FIN-A FIN-B PFD_OUT Fig.54 ●Reference data (Common to BU2373FV & BU2374FV – Phase Comparator I/O Waveform) 1V/div 1V/div Upper：FIN_A Middle：FIN_B Lower PFD_OUT ： Upper：FIN_A 50µsec/div Middle：FIN_B Lower PFD_OUT ： 50µsec/div 1V/div Upper：FIN_A Middle：FIN_B Lower PFD_OUT ： 50µsec/div Fig.55 UP Signal Output (VDD=3.3V, FIN_A > FIN_B) Fig.56 No Error Signal Output (VDD=3.3V, FIN_A = FIN_B) Fig.57 DOWN Signal Output (VDD=3.3V, FIN_A < FIN_B) www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 12/18 2011.08 - Rev.B BU2373FV,BU2374FV Technical Note (Functioning of PLL System) In order to configure the stable PLL system, the following section describes the functional principle, open loop characteristics, and closed loop characteristics by block shown in the Block Diagram below. PLL System Block Diagram Phase-comparator Kp FIN-B θo LPF F(s) VCO Kv/s VCO_OUT FIN-A θi 1/N Divider Fig.58 ① Phase Comparator The phase comparator shows the characteristics shown in figure below. Assuming that the Gain is Kp, Kp=(VOHVOL)/4(V/rad) VCO (Voltage Controlled Oscillator) The VCO shows the characteristics shown in figure below. Assuming that the Gain is Kv, Kv=2   (fmax-fmin)/(Vmax-Vmin)(rad/s/V) frequency 　 (MHz) ② VOH fmax -2π 0 2π fmin VOL 0 Vmin Vmax VCO_IN (V) Fig.59 Phase Comparator Characteristics Fig.60 VCO Characteristics ③ LPF (Lag-Lead Filter) Calculate the Gain of the lag-lead filter. It is recommended to use the filter having the pattern shown below. R2 PDOUT R1 C2 C1 VCOIN Fig.61 www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 13/18 2011.08 - Rev.B BU2373FV,BU2374FV Technical Note For the lag-lead filter afore-mentioned, assuming that C1  C2 (C2 is used at a value approx. 10 times as high as C1), break this filter into two portions as shown below to facilitate the calculation, thus proceeding with the calculation. (1) R2 (2) R1 R2 R1 C1 C2 Fig.62 LPF Portion ① In the case of (1) above, Fig.63 LPF Portion ② VOUT F(s) = = VIN 2 1 S・C2 1 R1+R2+ S・C2 R1+ 2 2 = S・C2・R1+1 S・C2・(R1+R2)+1 (S=jω) | F(jω) | = -1 1+ω ・C2 ・R1 2 1+｛ω・C2・(R1+R2) ｝ -1 (ω=2πf) φ(ω) = tan （ω・C2・R1）-tan ｛ω・C2・（R1+R2) ｝ ・By the expression above, the Gain and the Phase are given as shown in graphs below. Gain(dB) φ fC1 -6dB/oct π/4 fC2 f 20log{R1/(R1+R2)} fC1 fC2 f π/2 Fig.64 (Fig.62) Frequency  Gain Characteristics Fig.65 (Fig.62) Frequency  Phase Characteristics fC1 = 1 2π × 1 C2・（R1+R2) , fc2 = 1 2π × 1 C2・R1 In the case of (2) above, VOUT F(s) = = VIN R1 R1 R1+R2 1+S・C1・R1 = R1 R1・R2 R2+ S・C1・ R1+R2 1+S・C1・R1 R1 2 (R1+R2) 2 (S=jω) +1 | F(jω) | = R1 ・R2 1+ω ・C1 ・ (R1+R2)2 2 2 2 2 (ω=2πf) φ( ω ) = R1・R2 -1 ｝ -tan ｛ω・C1・ （R1+R2) www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 14/18 2011.08 - Rev.B BU2373FV,BU2374FV ・By the expression aforementioned, the Gain and the Phase are given as shown in graphs below. Gain(dB) 20log{R1/(R1+R2)} -6dB/oct π /4 φ fC3 Technical Note f π/2 f Fig.67 (Fig.63) Frequency  Phase Characteristics fC3 Fig.66 (Fig.63) Frequency  Gain Characteristics 1 fC3 = 2 × π R1+R2 C1・R1・R2 By combining (1) and (2), finding the Gain and the Phase of the lag-lead filter, F(s) = VOUT VIN 1+S・C2・R1 = ｛1+S・C2・(R1+R2)｝ × ｛1+ S・C1・ R1・R2 R1+R2 (S=jω) ｝ The gain and the Phase are given as shown below, respectively. Gain=20・log｛ G1= G2= G3= 2 G2 G1×G3 2 ｝ , 2 Phase=θ2-θ1-θ3 , , θ1= -tan ｛2πf・C2・（R1+R2)｝ θ2= tan （2πf・C2・R1） θ3= -tan ｛2πf・C1・ -1 -1 -1 1+C2 ・(R1+R2) ・(2πf) 1+C2 ・R1 ・(2πf) 1+C1 ・R1 ・ 2 2 2 2 2 1 2 2 ・(2πf) (R1+R2) , R1・R2 ｝ （R1+R2) Gain(dB) φ -6dB/oct fC1 fC2 fC3 f π/4 20log{R1/(R1+R2)} π/2 f fC1 fC2 fC3 Fig.68 (Fig.61) Frequency  Gain Characteristics Fig.69 (Fig.61) Frequency  Phase Characteristics www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 15/18 2011.08 - Rev.B BU2373FV,BU2374FV Technical Note ・Where, find the Gain for the open loop of PLL system. Assuming that the transfer function is H(s), Kv 1 H(s)= Kp×F(s)× × S N Kp× Kv S × 1 N = S× 2 1 N Kp×Kv θ0= -tan (2πf・ -1 G0= 2πf×N Kp×Kv , G2 G1×G3×G0 N Kp×Kv )= π 2 PLL-Gain=20・log｛ ｝ , Phase=-θ0+θ2-θ1-θ3 Gain(dB) φ fC1 fC2 fC3 f π/2 fC1 fC2 fC3 f π Fig.70 (Fig.58) Frequency  Gain Characteristics Fig.71 (Fig.58) Frequency  Phase Characteristics If, by the expression above, the LPF constant is selected so that a phase margin of 45 or more is secured when the Gain for the open loop becomes 0 dB, the PLL system will stably function. Note) ・As to the jitters, the TYP values vary with the substrate, power supply, output loads, noises, and others. Besides, for the use of the BU2373FV or the BU2374FV, the operating margin should be thoroughly checked. ・The Analog power supply and the Logic power supply should be separated from each other so that noises generated with the Logic power supply have no adverse influences on the Analog power one. ・Bypass capacitors between the power supply and GND should be mounted as close as possible. ・Power to control pins (i.e., VCO_INHIBIT, PFD_INHIBIT and SELECT) should be supplied from the logic power supply. ・In order to configure the PLL system, the LPF GND should be connected to the Analog GND and mounted in the proximity of the VCO_IN. www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 16/18 2011.08 - Rev.B BU2373FV,BU2374FV Technical Note ●Notes for use (1) Absolute Maximum Ratings An excess in the absolute maximum ratings, such as applied voltage (VDD or VIN), operating temperature range (Topr), etc., can break down devices, thus making impossible to identify breaking mode such as a short circuit or an open circuit. If any special mode exceeding the absolute maximum ratings is assumed, consideration should be given to take physical safety measures including the use of fuses, etc. (2) Recommended operating conditions These conditions represent a range within which characteristics can be provided approximately as expected. The electrical characteristics are guaranteed under the conditions of each parameter. (3) Reverse connection of power supply connector The reverse connection of power supply connector can break down ICs. Take protective measures against the breakdown due to the reverse connection, such as mounting an external diode between the power supply and the IC’s power supply terminal. (4) Power supply line Design PCB pattern to provide low impedance for the wiring between the power supply and the GND lines. In this regard, for the digital block power supply and the analog block power supply, even though these power supplies has the same level of potential, separate the power supply pattern for the digital block from that for the analog block, thus suppressing the diffraction of digital noises to the analog block power supply resulting from impedance common to the wiring patterns. For the GND line, give consideration to design the patterns in a similar manner. Furthermore, for all power supply terminals to ICs, mount a capacitor between the power supply and the GND terminal. At the same time, in order to use an electrolytic capacitor, thoroughly check to be sure the characteristics of the capacitor to be used present no problem including the occurrence of capacity dropout at a low temperature, thus determining the constant. (5) GND voltage Make setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state. Furthermore, check to be sure no terminals are at a potential lower than the GND voltage including an actual electric transient. (6) Short circuit between terminals and erroneous mounting In order to mount ICs on a set PCB, pay thorough attention to the direction and offset of the ICs. Erroneous mounting can break down the ICs. Furthermore, if a short circuit occurs due to foreign matters entering between terminals or between the terminal and the power supply or the GND terminal, the ICs can break down. (7) Operation in strong electromagnetic field Be noted that using ICs in the strong electromagnetic field can malfunction them. (8) Inspection with set PCB On the inspection with the set PCB, if a capacitor is connected to a low-impedance IC terminal, the IC can suffer stress. Therefore, be sure to discharge from the set PCB by each process. Furthermore, in order to mount or dismount the set PCB to/from the jig for the inspection process, be sure to turn OFF the power supply and then mount the set PCB to the jig. After the completion of the inspection, be sure to turn OFF the power supply and then dismount it from the jig. In addition, for protection against static electricity, establish a ground for the assembly process and pay thorough attention to the transportation and the storage of the set PCB. (9) Input terminals In terms of the construction of IC, parasitic elements are inevitably formed in relation to potential. The operation of the parasitic element can cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the input terminal. Therefore, pay thorough attention not to handle the input terminals, such as to apply to the input terminals a voltage lower than the GND respectively, so that any parasitic element will operate. Furthermore, do not apply a voltage to the input terminals when no power supply voltage is applied to the IC. In addition, even if the power supply voltage is applied, apply to the input terminals a voltage lower than the power supply voltage or within the guaranteed value of electrical characteristics. (10) Ground wiring pattern If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well. (11) External capacitor In order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a degradation in the nominal capacitance due to DC bias and changes in the capacitance due to temperature, etc. www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 17/18 2011.08 - Rev.B BU2373FV,BU2374FV ●Ordering part number Technical Note B U 2 Part No. 2373 2374 3 7 3 F V - E 2 Part No. Package F: SSOP-B14 Packaging and forming specification E2: Embossed tape and reel SSOP-B14 5.0 ± 0.2 14 8 Tape Quantity 0.3Min. Embossed carrier tape 2500pcs E2 The direction is the 1pin of product is at the upper left when you hold 6.4 ± 0.3 4.4 ± 0.2 Direction of feed ( reel on the left hand and you pull out the tape on the right hand ) 1 7 0.15 ± 0.1 1.15 ± 0.1 0.10 0.65 0.1 0.22 ± 0.1 1pin (Unit : mm) Direction of feed Reel ∗ Order quantity needs to be multiple of the minimum quantity. www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 18/18 2011.08 - Rev.B Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. 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Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuelcontroller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law. Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact us. ROHM Customer Support System http://www.rohm.com/contact/ www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. R1120A