BU2396KN

TECHNICAL NOTE High-performance Clock Generator Series 3ch Clock Generator for Digital Cameras BU2394KN,BU2396KN ●Description These clock generators are an IC generating three types of clocks – CCD, USB, and VIDEO clocks – necessary for digital still camera systems and digital video camera systems, with a single chip through making use of the PLL technology. Generating these clocks with a single chip allows for the simplification of clock system, little space occupancy, reduction in the number of components used for mobile camera equipment, which is becoming increasingly downsized and less costly. ●Features 1) Connecting a crystal oscillator generates multiple clock signals with a built-in PLL. 2) The CCD clock provides switching selection outputs. 3) Providing the output of low period-jitter clock. 4) Incorporating compact package VQFN20 most suited for mobile devices. 5) Single power supply of 3.3 V ●Applications Generation of clocks used in digital still camera and digital video camera systems ●Lineup BU2394KN Supply voltage Operating temperature range Reference input clock Output CCD clock 3.0V～3.6V -5～＋70℃ 14.318182MHz 28.636363MHz 135.000000MHz 110.000000MHz 108.000000MHz 98.181818MHz Output USB clock Output VIDEO clock 48.008022MHz 14.318182MHz 17.734450MHz 27.000000MHz 12.000000MHz 36.000000MHz 30.000000MHz 24.000000MHz BU2396KN 3.0V～3.6V -5～＋70℃ 12.000000MHz ●Absolute Maximum Ratings（Ta=25℃） Parameter Supply voltage Input voltage Storage Temperature range Symbol VDD VIN Tstg PD Limit -0.5～7.0 -0.5～VDD+0.5 -30～125 530 Unit Ｖ Ｖ ℃ mW Power dissipation *1 Operating temperature is not guaranteed. *2 In the case of exceeding Ta = 25℃, 5.3mW should be reduced per 1℃. *3 The radiation-resistance design is not carried out. *4 Power dissipation is measured when the IC is mounted to the printed circuit board. Sep. 2008 ●Recommended Operating Range Parameter Supply voltage Input H voltage Input L voltage Operating temperature Output load ● Symbol VDD VINH VINL Topr CL Limit 3.0～3.6 0.8VDD～VDD 0.0～0.2VDD -5～70 15(MAX) Unit Ｖ Ｖ Ｖ ℃ pF Electrical characteristics BU2394KN(VDD=3.3V, Ta=25℃, unless otherwise specified.) XTAL_SEL=H with crystal oscillator at a frequency of 28.636363 MHz, while XTAL_SEL=L at 14.318182 MHz Parameter Symbol IDD VOH1 VOH2 VOHR VOL1 VOL2 VOLR Limit Min. － VDD-0.5 VDD-0.5 VDD-0.5 － － － Typ. 45 VDD-0.2 VDD-0.2 VDD-0.2 0.2 0.2 0.2 Max. 60 － － － 0.5 0.5 0.5 Unit mA V V V V V V At no load When current load = - 9.0mA When current load = - 7.0mA When current load = - 4.5mA When current load =11mA When current load =9.0mA When current load =5.5mA Specified by a current value running when a voltage of 0V is applied to a measuring pin. (R=VDD／I) XTAL×(1188/63)/2 XTAL×(1056/70)/2 XTAL×(864/63)/2 XTAL×(968/63)/2 XTAL×(228/17)/4 XTAL Output XTAL×(706/57)/10 Measured at a voltage of 1/2 of VDD Measured at a voltage of 1/2 of VDD Period of transition time required for the output to reach 80% from 20% of VDD. Period of transition time required for the output to reach 20% from 80% of VDD. ※1 ※2 Condition 【Action circuit current】 【Output H voltage】 CLK1 CLK2 REF_CLK 【Output L voltage】 CLK1 CLK2 REF_CLK 【Pull-Up resistance value】 FS1, FS2, FS3, CLK2ON, XTAL_SEL Pull-Up R 125 250 375 Ω 【Output frequency】 CLK1 FS2:H FS3:H CLK1 FS2:H FS3:L CLK1 FS2:L FS3:L CLK1 FS2:L FS3:H CLK2 REF_CLK FS1:H REF_CLK FS1:L 【Output waveform】 Duty1 100MHz or less Duty2 100MHz or more Rise time Tr Fall time Tf 【Jitter】 Period-Jitter 1σ Period-Jitter MIN-MAX P-J1σ P-J MIN-MAX － － 30 180 － － psec psec － 2.5 － nsec － 2.5 － nsec Duty1 Duty2 45 － 50 50 55 － ％ ％ Fclk1-1 Fclk1-2 Fclk1-3 Fclk1-4 Fclk2-2 Fref1-1 Fref1-2 － － － － － － － 135.000000 108.000000 98.181818 110.000000 48.008022 14.318182 17.734450 － － － － － － － MHz MHz MHz MHz MHz MHz MHz 【Output Lock-Time】 Tlock － － 1 msec ※3 Note) The output frequency is determined by the arithmetic (frequency division) expression of a frequency input to XTALIN. If the input frequency is set to values shown below, the output frequency will be as listed above. When XTAL_SEL is set to H, the input frequency on XTALIN will be 28.636363 MHz. When XTAL_SEL is set to L, the input frequency on XTALIN will be 14.318182 MHz. 2/16 BU2396N(VDD=3.3V, Ta=25℃, Crystal =12.000000MHz, unless otherwise specified.) Parameter 【Action circuit current】 【Output H voltage】 TGCLK VCLK UCLK 【Output L voltage】 TGCLK VCLK UCLK 【Pull-Up resistance value】 TGCLK_SEL1 TGCLK_SEL2 Pull-up R Specified by a current value running when a voltage of 0V is applied to a measuring pin. (R=VDD／I) Specified by a current value running when a VDD is applied to a measuring pin. (R=VDD／I) XTAL×(48/4)/6 XTAL×(60/4)/6 XTAL×(54/3)/6 XTAL×(54/3)/8 XTAL output Measured at a voltage of 1/2 of VDD Symbol IDD VOHT VOHV VOHU VOLT VOLV VOLU Limit Min. － VDD-0.5 VDD-0.5 VDD-0.5 － － － Typ. 23 － － － － － － Max. 35 － － － 0.5 0.5 0.5 Unit mA V V V V V V At no load Condition When current load =-5.0mA When current load =-5.0mA When current load =-5.0mA When current load =5.0mA When current load =5.0mA When current load =5.0mA 125 250 375 KΩ 【Pull-Down resistance value】 TGCLK_EN, TGCLK_PD VCLK_EN, VCLK_PD Pull-down R 25 50 75 KΩ 【Output frequency】 TGCLK TGCLK TGCLK VCLK UCLK 【Output waveform】 Duty Rise time Tr Fall time Tf 【Jitter】 Period-Jitter 1σ Period-Jitter MIN-MAX 【Output Lock-Time】 P-J1σ P-J MIN-MAX 50 300 psec psec ※1 ※2 2.0 nsec 2.0 nsec Duty 45 50 55 ％ Period of transition time required for the output to reach 80% from 20% of VDD. Period of transition time required for the output to reach 20% from 80% of VDD. SEL1:L SEL2:L SEL1:L SEL2:H SEL1:H TGCLK1 TGCLK2 TGCLK3 VCLK UCLK 24.000000 30.000000 36.000000 27.000000 12.000000 MHz MHz MHz MHz MHz Tlock 1 msec ※3 Note) The output frequency is determined by the arithmetic (frequency division) expression of a frequency input to XTALIN. If the input frequency is set to 12.000000MHz, the output frequency will be as listed above. Common to BU2394KN, BU2396KN ※1 Period-Jitter 1σ This parameter represents standard deviation (=1σ) on cycle distribution data at the time when the output clock cycles are sampled 1000 times consecutively with the TDS7104 Digital Phosphor Oscilloscope of Tektronix Japan, Ltd. ※2 Period-Jitter MIN-MAX This parameter represents a maximum distribution width on cycle distribution data at the time when the output clock cycles are sampled 1000 times consecutively with the TDS7104 Digital Phosphor Oscilloscope of Tektronix Japan, Ltd. ※3 Output Lock-Time The Lock-Time represents elapsed time after power supply turns ON to reach a 3.0V voltage, after the system is switched from Power-Down state to normal operation state, or after the output frequency is switched, until it is stabilized at a specified frequency, respectively. 3/16 ●Reference data (BU2394KN basic data) RBW=1KHz VBW=100Hz 10dB／div 500psec／div Fig.2 135MHz Period-Jitter At VDD=3.3V and CL=15pF 1.0V／div 1.0V／div 1.0nsec／div Fig.1 135MHz output wave At VDD=3.3V and CL=15pF 10KHz／div Fig.3 135MHz Spectrum At VDD=3.3V and CL=15pF RBW=1KHz VBW=100Hz 10dB／div 500psec／div Fig.5 110MHz Period-Jitter At VDD=3.3V and CL=15pF 1.0V／div 1.0V／div 2.0nsec／div Fig.4 110MHz output wave At VDD=3.3V and CL=15pF 10KHz／div Fig.6 110MHz Spectrum At VDD=3.3V and CL=15pF RBW=1KHz VBW=100Hz 10dB／div 500psec／div Fig.8 108MHz Period-Jitter At VDD=3.3V and CL=15pF 1.0V／div 1.0V／div 2.0nsec／div Fig.7 108MHz output wave At VDD=3.3V and CL=15pF 10KHz／div Fig.9 108MHz Spectrum At VDD=3.3V and CL=15pF RBW=1KHz VBW=100Hz 10dB／div 500psec／div Fig.11 98MHz Period-Jitter At VDD=3.3V and CL=15pF 1.0V／div 1.0V／div 2.0nsec／div Fig.10 98MHz output wave At VDD=3.3V and CL=15pF 10KHz／div Fig.12 98MHz Spectrum At VDD=3.3V and CL=15pF 4/16 ●Reference data (BU2394KN basic data) RBW=1KHz VBW=100Hz 10dB／div 500psec／div Fig.14 48MHz Period-Jitter At VDD=3.3V and CL=15pF 1.0V／div 1.0V／div 5.0nsec／div Fig.13 48MHz output wave At VDD=3.3V and CL=15pF 10KHz／div Fig.15 48MHz Spectrum At VDD=3.3V and CL=15pF RBW=1KHz VBW=100Hz 10dB／div 500psec／div Fig.17 17.7MHz Period-Jitter At VDD=3.3V and CL=15pF 1.0V／div 1.0V／div 10.0nsec／div Fig.16 17.7MHz output wave At VDD=3.3V and CL=15pF 10KHz／div Fig.18 17.7MHz Spectrum At VDD=3.3V and CL=15pF RBW=1KHz VBW=100Hz 10dB／div 500psec／div Fig.20 14.3MHz Period-Jitter At VDD=3.3V and CL=15pF 1.0V／div 1.0V／div 10.0nsec／div Fig.19 14.3MHz output wave At VDD=3.3V and CL=15pF 10KHz／div Fig.21 14.3MHz Spectrum At VDD=3.3V and CL=15pF 5/16 ●Reference data (BU2394KN 55 Temperature and Supply voltage variations data) 100 Period-jitter1σ：PJ-1σ[psec] 90 70 60 50 40 30 20 10 0 80 600 500 400 300 200 100 0 -25 0 25 50 75 100 54 53 52 51 50 49 48 47 46 45 -25 0 25 50 75 100 Temperature：T[℃] Period-jitterMIN-MAX： PJ-MIN-MAX[psec] Duty：Duty[%] VDD=2.9V VDD=3.3V VDD=3.7V VDD=2.9V VDD=3.3V VDD=3.7V VDD=2.9V VDD=3.3V VDD=3.7V -25 0 25 50 75 100 Temperature：T[℃] Temperature：T[℃] Fig.22 135MHz Temperature－Duty Fig.23 135MHz Temperature－Period-Jitter 1σ Fig.24 135MHz Temperature－Period-Jitter MIN-MAX 55 Period-jitter1σ：PJ-1σ[psec] 100 90 70 60 50 40 30 20 10 0 Period-jitterMIN-MAX： PJ-MIN-MAX[psec] 80 600 500 400 300 200 100 0 -25 0 25 50 75 100 -25 0 25 50 75 100 Temperature：T[℃] Temperature：T[℃] 54 53 52 51 50 49 48 47 46 45 -25 0 25 50 75 100 Temperature：T[℃] Duty：Duty[%] VDD=2.9V VDD=3.3V VDD=3.7V VDD=2.9V VDD=3.3V VDD=3.7V VDD=2.9V VDD=3.3V VDD=3.7V Fig.25 110MHz Temperature－Duty Fig.26 110MHz Temperature－Period-Jitter 1σ Fig.27 110MHz Temperature－Period-Jitter MIN-MAX 55 Period-jitter1σ：PJ-1σ[psec] 54 53 52 51 50 49 48 47 46 45 -25 0 25 50 75 100 Temperature：T[℃] 100 90 70 60 50 40 30 20 10 0 -25 0 25 50 75 100 Temperature：T[℃] Period-jitterMIN-MAX： PJ-MIN-MAX[psec] 80 600 500 400 300 200 100 0 -25 0 25 50 75 100 Temperature：T[℃] Duty：Duty[%] VDD=2.9V VDD=3.3V VDD=3.7V VDD=2.9V VDD=3.3V VDD=3.7V VDD=2.9V VDD=3.3V VDD=3.7V Fig.28 108MHz Temperature－Duty Fig.29 108MHz Temperature－Period-Jitter 1σ Fig.30 108MHz Temperature－Period-Jitter MIN-MAX 55 Period-jitter1σ：PJ-1σ[psec] 54 53 52 51 50 49 48 47 46 45 -25 0 25 50 75 100 Temperature：T[℃] 100 90 70 60 50 40 30 20 10 0 -25 0 25 50 75 100 Temperature：T[℃] Period-jitterMIN-MAX： PJ-MIN-MAX[psec] 80 600 500 400 300 200 100 0 -25 0 25 50 75 100 Temperature：T[℃] Duty：Duty[%] VDD=2.9V VDD=3.3V VDD=3.7V VDD=2.9V VDD=3.3V VDD=3.7V VDD=2.9V VDD=3.3V VDD=3.7V Fig.31 98MHz Temperature－Duty Fig.32 98MHz Temperature－Period-Jitter 1σ 6/16 Fig.33 98MHz Temperature－Period-Jitter MIN-MAX ●Reference data (BU2394KN 55 Temperature and Supply voltage variations data) 100 Period-jitter1σ：PJ-1σ[psec] 90 Period-jitterMIN-MAX： PJ-MIN-MAX[psec] 80 70 60 50 40 30 20 10 0 0 -25 0 25 50 75 100 -25 0 25 50 75 100 Temperature：T[℃] Temperature：T[℃] 600 54 53 52 51 50 49 48 47 46 45 -25 0 25 50 75 100 Temperature：T[℃] Duty：Duty[%] VDD=3.7V VDD=3.3V VDD=2.9V 500 400 300 200 100 VDD=3.7V VDD=3.3V VDD=2.9V VDD=2.9V VDD=3.3V VDD=3.7V Fig.34 48MHz Temperature－Duty Fig.35 48MHz Temperature－Period-Jitter 1σ Fig.36 98MHz Temperature－Period-Jitter MIN-MAX 55 Period-jitter1σ：PJ-1σ[psec] 54 53 52 51 50 49 48 47 46 45 -25 0 25 50 75 100 Temperature：T[℃] 100 90 Period-jitterMIN-MAX： PJ-MIN-MAX[psec] 80 70 60 50 40 30 20 10 0 -25 0 25 50 75 100 Temperature：T[℃] 600 500 400 300 200 100 0 -25 0 25 50 75 100 Temperature：T[℃] Duty：Duty[%] VDD=3.7V VDD=3.3V VDD=2.9V VDD=3.7V VDD=3.3V VDD=2.9V VDD=2.9V VDD=3.3V VDD=3.7V Fig.37 17.7MHz Temperature－Duty Fig.38 17.7MHz Temperature－Period-Jitter 1σ Fig.39 17.7MHz Temperature－Period-Jitter MIN-MAX 55 Period-jitter1σ：PJ-1σ[psec] 54 53 52 51 50 49 48 47 46 45 -25 0 25 50 75 100 Temperature：T[℃] 100 90 70 60 50 40 30 20 10 0 -25 0 25 50 75 100 Temperature：T[℃] Period-jitterMIN-MAX： PJ-MIN-MAX[psec] 80 600 500 400 300 200 100 0 -25 0 25 50 75 100 Temperature：T[℃] Duty：Duty[%] VDD=3.7V VDD=3.3V VDD=2.9V VDD=3.7V VDD=3.3V VDD=2.9V VDD=2.9V VDD=3.3V VDD=3.7V Fig.40 14.3MHz Temperature－Duty Fig.41 14.3MHz Temperature－Period-Jitter 1σ Fig.42 14.3MHz Temperature－Period-Jitter MIN-MAX 60 50 IDD：IDD[mA] 40 30 20 10 0 -25 0 25 50 75 100 Temperature：T[℃] VDD=3.7V VDD=3.3V VDD=2.9V Fig.43 At 1chip operation Temperature－Consumption current 7/16 ●Reference data (BU2396KN basic data) z RBW=1KHz VBW=100Hz 10dB／div 500psec／div Fig.45 136MHz Period-Jitter At VDD=3.3V and CL=15pF 1.0V／div 1.0V／div 5.0nsec／div Fig.44 36MHz output waveform At VDD=3.3V and CL=15pF 10KHz／div Fig.46 36MHz Spectrum At VDD=3.3V and CL=15pF RBW=1KHz VBW=100Hz 10dB／div 500psec／div Fig.48 30MHz Period-Jitter At VDD=3.3V and CL=15pF 1.0V／div 1.0V／div 5.0nsec／div Fig.47 30MHz output waveform At VDD=3.3V and CL=15pF 10KHz／div Fig.49 30MHz Spectrum At VDD=3.3V and CL=15pF RBW=1KHz VBW=100Hz 10dB／div 500psec／div Fig.51 24MHz Period-Jitter At VDD=3.3V and CL=15pF 1.0V／div 1.0V／div 5.0nsec／div Fig.50 24MHz output waveform At VDD=3.3V and CL=15pF 10KHz／div Fig.52 24MHz Spectrum At VDD=3.3V and CL=15pF RBW=1KHz VBW=100Hz 10dB／div 500psec／div Fig.54 27MHz Period-Jitter At VDD=3.3V and CL=15pF 1.0V／div 1.0V／div 5.0nsec／div Fig.53 27MHz output waveform At VDD=3.3V and CL=15pF 10KHz／div Fig.55 27MHz Spectrum At VDD=3.3V and CL=15pF 8/16 ●Reference data (BU2396KN basic data) RBW=1KHz VBW=100Hz 10dB／div 500psec／div Fig.57 12MHz Period-Jitter At VDD=3.3V and CL=15pF 1.0V／div 1.0V／div 5.0nsec／div Fig.56 12MHz output waveform At VDD=3.3V and CL=15pF 10KHz／div Fig.58 12MHz Spectrum At VDD=3.3V and CL=15pF ●Reference data (BU2396KN 55 54 53 52 51 50 49 48 47 46 45 -25 0 25 50 75 Temperature and Supply voltage variations data) 100 Period-jitter1σ：PJ-1σ[psec] 90 80 70 60 50 40 30 20 10 0 100 -25 0 25 50 75 100 Period-jitterMIN-MAX ： PJ-MIN-MAX[psec] 600 500 400 300 200 100 0 -25 0 25 50 75 100 Duty：Duty[%] VDD=2.9V VDD=3.3V VDD=3.7V VDD=2.9V VDD=3.3V VDD=3.7V VDD=2.9V VDD=3.3V VDD=3.7V Temperature：T[℃] Temperature：T[℃] Temperature： T[ ℃] Fig.59 36MHz Temperature－Duty Fig.60 36MHz Temperature－Period-Jitter 1σ Fig.61 36MHz Temperature－Period-Jitter MIN-MAX 55 Period-jitter1σ：PJ-1σ[psec] 54 53 52 51 50 49 48 47 46 45 -25 0 25 50 75 100 Temperature：T[℃] 100 90 80 70 60 50 40 30 20 10 0 -25 0 25 50 75 100 Temperature：T[℃] Period-jitterMIN-MAX ： PJ-MIN-MAX[psec] 600 500 400 300 200 100 0 -25 0 25 50 75 100 Duty：Duty[%] VDD=2.9V VDD=3.3V VDD=3.7V VDD=2.9V VDD=3.3V VDD=3.7V VDD=2.9V VDD=3.3V VDD=3.7V Temperature： T[ ℃] Fig.62 30MHz Temperature－Duty Fig.63 30MHz Temperature－Period-Jitter 1σ Fig.64 30MHz Temperature－Period-Jitter MIN-MAX 55 Period-jitter1σ：PJ-1σ[psec] 54 53 52 51 50 49 48 47 46 45 -25 0 25 50 75 100 Temperature：T[℃] 100 90 70 60 50 40 30 20 10 0 -25 0 25 50 75 100 Temperature：T[℃] Period-jitterMIN-MAX： PJ-MIN-MAX[psec] 80 600 500 400 300 200 100 0 -25 0 25 50 75 100 Temperature：T[℃] Duty：Duty[%] VDD=2.9V VDD=3.3V VDD=3.7V VDD=2.9V VDD=3.3V VDD=3.7V VDD=2.9V VDD=3.3V VDD=3.7V Fig.65 24MHz Temperature－Duty Fig.66 24MHz Temperature－Period-Jitter 1σ 9/16 Fig.67 24MHz Temperature－Period-Jitter MIN-MAX ●Reference data (BU2396KN 55 53 54 52 51 50 49 48 47 46 45 -25 0 25 50 75 Temperature and Supply voltage variations data) 100 80 70 60 50 40 30 20 10 0 100 -25 0 25 50 75 100 Period-jitterMIN-MAX ： PJ-MIN-MAX[psec] 600 500 400 300 200 100 0 -25 0 25 50 75 100 Duty：Duty[%] VDD=2.9V VDD=3.3V VDD=3.7V Period-jitter1σ：PJ-1σ[psec] 90 VDD=3.7V VDD=3.3V VDD=2.9V VDD=3.7V VDD=3.3V VDD=2.9V Temperature：T[℃] Temperature：T[℃] Temperature： T[ ℃] Fig.68 27MHz Temperature－Duty Fig.69 27MHz Temperature－Period-Jitter 1σ Fig.70 27MHz Temperature－Period-Jitter MIN-MAX 55 53 100 80 70 60 50 40 30 20 10 0 -25 0 25 50 75 100 -25 0 25 50 75 100 Temperature：T[℃] Temperature：T[℃] Period-jitterMIN-MAX ： PJ-MIN-MAX[psec] 600 500 400 300 200 100 0 -25 0 25 50 75 100 Duty：Duty[%] 52 51 50 49 48 47 46 45 VDD=2.9V VDD=3.3V VDD=3.7V Period-jitter1σ：PJ-1σ[psec] 54 90 VDD=2.9V VDD=3.3V VDD=3.7V VDD=2.9V VDD=3.3V VDD=3.7V Temperature： T[ ℃] Fig.71 12MHz Temperature－Duty Fig.72 12MHz Temperature－Period-Jitter 1σ Fig.73 12MHz Temperature－Period-Jitter MIN-MAX 40 30 IDD：IDD[mA] 20 10 VDD=3.7V VDD=3.3V VDD=2.9V 0 -25 0 25 50 75 100 Temperature：T[℃] Fig.74 At 1chip operation Temperature－Consumption current 10/16 ●List of BU2396KN Operation Modes When XTAL_SEL=L, (When a crystal oscillator of 14.318182-MHz frequency is used) Xtal(MHz) 14.318182 14.318182 14.318182 14.318182 14.318182 14.318182 14.318182 14.318182 14.318182 14.318182 14.318182 14.318182 14.318182 14.318182 14.318182 14.318182 CLK2ON Ｈ Ｈ Ｌ Ｌ Ｈ Ｈ Ｌ Ｌ Ｈ Ｈ Ｌ Ｌ Ｈ Ｈ Ｌ Ｌ FS1 Ｈ Ｌ Ｈ Ｌ Ｈ Ｌ Ｈ Ｌ Ｈ Ｌ Ｈ Ｌ Ｈ Ｌ Ｈ Ｌ FS2 Ｈ Ｈ Ｈ Ｈ Ｈ Ｈ Ｈ Ｈ Ｌ Ｌ Ｌ Ｌ Ｌ Ｌ Ｌ Ｌ FS3 Ｈ Ｈ Ｈ Ｈ Ｌ Ｌ Ｌ Ｌ Ｌ Ｌ Ｌ Ｌ Ｈ Ｈ Ｈ Ｈ CLK1(MHz) 135.000000 135.000000 135.000000 135.000000 108.000000 108.000000 108.000000 108.000000 98.181818 98.181818 98.181818 98.181818 110.000000 110.000000 110.000000 110.000000 CLK2(MHz) 48.008022 48.008022 Fixed to L Fixed to L 48.008022 48.008022 Fixed to L Fixed to L 48.008022 48.008022 Fixed to L Fixed to L 48.008022 48.008022 Fixed to L Fixed to L REF_CLK(MHz) 14.318182 17.734450 14.318182 17.734450 14.318182 17.734450 14.318182 17.734450 14.318182 17.734450 14.318182 17.734450 14.318182 17.734450 14.318182 17.734450 When XTAL_SEL=H, (When a crystal oscillator of 28.636363MHz frequency is used) Xtal(MHz) 28.636363 28.636363 28.636363 28.636363 28.636363 28.636363 28.636363 28.636363 28.636363 28.636363 28.636363 28.636363 28.636363 28.636363 28.636363 28.636363 CLK2ON Ｈ Ｈ Ｌ Ｌ Ｈ Ｈ Ｌ Ｌ Ｈ Ｈ Ｌ Ｌ Ｈ Ｈ Ｌ Ｌ FS1 Ｈ Ｌ Ｈ Ｌ Ｈ Ｌ Ｈ Ｌ Ｈ Ｌ Ｈ Ｌ Ｈ Ｌ Ｈ Ｌ FS2 Ｈ Ｈ Ｈ Ｈ Ｈ Ｈ Ｈ Ｈ Ｌ Ｌ Ｌ Ｌ Ｌ Ｌ Ｌ Ｌ FS3 Ｈ Ｈ Ｈ Ｈ Ｌ Ｌ Ｌ Ｌ Ｌ Ｌ Ｌ Ｌ Ｈ Ｈ Ｈ Ｈ CLK1(MHz) 135.000000 135.000000 135.000000 135.000000 108.000000 108.000000 108.000000 108.000000 98.181818 98.181818 98.181818 98.181818 110.000000 110.000000 110.000000 110.000000 CLK2(MHz) 48.008022 48.008022 Fixed to L Fixed to L 48.008022 48.008022 Fixed to L Fixed to L 48.008022 48.008022 Fixed to L Fixed to L 48.008022 48.008022 Fixed to L Fixed to L REF_CLK(MHz) 14.318182 17.734450 14.318182 17.734450 14.318182 17.734450 14.318182 17.734450 14.318182 17.734450 14.318182 17.734450 14.318182 17.734450 14.318182 17.734450 11/16 ●List of BU2396KN Operation Modes TGCLK_SEL1 TGCLK_SEL 2 TGCLK_EN VCLK_EN TGCLK_PD VCLK_PD TGCLK Output VCLK Output UCLK Output PLL1 30M,24M PLL2 36M,27M 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 Normal operation 0 0 1 0 Fixed to L Power-Down Power-Down 0 1 1 0 Fixed to L Normal operation Power-Down Normal operation Power-Down Normal operation Power-Down Normal operation Power-Down Normal operation 0 Fixed to L Power-Down 0 24MHz output 30MHz output Normal operation Power-Down 1 36MHz output 1 36MHz output Normal operation 0 Fixed to L Power-Down 1 24MHz output 30MHz output 36MHz output Power-Down 36MHz output 12MHz output Normal operation 1 0 0 Fixed to L 1 0 Fixed to L Power-Down 0 27MHz output 1 1 Normal operation Fixed to L Power-Down 0 24MHz output 30MHz output 36MHz output Fixed to L Normal operation Power-Down 1 36MHz output Normal operation Fixed to L Power-Down 27MHz output 1 24MHz output 30MHz output 36MHz output Normal operation Power-Down 36MHz output 12/16 ●BU2394KN Application Circuit / Description of Terminal for Video 14.318182MHz 0.1uF 17.734450MHz for USB 48.008022MHz 16：CLK2OUT 19：REF_CLK 20：TEST2 18：VDD2 17：VSS2 DATA PLL1 XIN 15：VDD1 14：VDD1 135.000000MHz 108.000000MHz 110.000000MHz 98.181818MHz 11 CLK1 4 5 1：AVDD 2：AVDD XTAL OSC 48.008022MHz 1／4 XOUT 0.1uF 3：AVSS 4：XIN BU2394KN VQFN-20 0.1uF 13：VSS1 12：CLK2ON 11：CLK1OUT PLL2 1 ／2 XTAL_SEL 7 12 10 9 8 PLL3 16 CLK2 R 5：XOUT 7：XTAL_SEL 6：TEST1 10：FS1 9：FS2 8：FS3 for CCD 135.000000MHz 110.000000MHz 108.000000MHz 98.181818MHz CLK2ON FS1 FS2 FS3 1／10 17.734450MHz 19 14.318182MHz REF_CLK Fig.75 Fig.76 Description of Terminal PIN No. PIN NAME 1 AVDD 2 AVDD 3 AVSS 4 XIN 5 XOUT 6 TEST1 7 XTAL_SEL 8 FS3 9 FS2 10 FS1 11 CLK1OUT 12 CLK2ON 13 VSS1 14 VDD1 15 VDD1 16 CLK2OUT 17 VSS2 18 VDD2 19 REF_CLK 20 TEST2 Function Analog power source Analog power source Analog GND Crystal IN Crystal OUT TEST pin, normally open, equipped with pull-down Crystal oscillator selection, H: 28.636 MHz, L: 14.318 MHz, equipped with pull-up CLK1,2 output selection, equipped with pull-up CLK1,2 output selection, equipped with pull-up REFCLK output selection, equipped with pull-up 110M/98M/108M/135M output CLK2 output control, H: Enable, L: Disable, equipped with pull-up CLK1/CLK2 & Internal digital GND CLK1/2 & Internal digital power supply CLK1/2 & Internal digital power supply 48M output REFCLK GND REFCLK power supply 14.3M/17.7M output TEST pin, normally open, equipped with pull-down Note) Basically, mount ICs to the substrate for use. If the ICs are not mounted to the substrate, the characteristics of ICs may not be fully demonstrated. Mount 0.1uF as bypass capacitors in the vicinity of the IC pins between 1&2 PIN and 3PIN, 13PIN and 14&15PIN, and 17PIN and 18PIN, respectively. ※Even though we believe that the example of the application circuit is worth of a recommendation, please be sure to thoroughly recheck the characteristics before use. ※As to the jitters, the TYP values vary with the substrate, power supply, output loads, noises, and others. Besides, for the use, the operating margin should be thoroughly checked. 13/16 ●BU2396KN Application Circuit / Description of Terminal XIN 4 5 for Video 27.000000MHz 0.1uF for USB 12.000000MHz 20 ： VCLK_PD 18 ： VDD2 19 ： VCLK 17 ： VSS2 16 ： UCLK XOUT XTAL OSC 12.000000MHz 16 UCLK TGCLK_EN 10 TGCLK_SEL2 7 DATA 30.000000MHz 24.000000MHz PLL1 36.000000MHz 11 TGCLK 1： AVDD 2： AVDD 15： VDD1 TGCLK_SEL1 14： VDD1 8 9 1／6 TGCLK_PD 0.1uF 3： AVSS 4： XIN BU2396KN VQFN-20 0.1uF 13： VSS1 12： VCLK_EN 11： TGCLK 10 ： TGCLK_EN R 5： XOUT 9： TGCLK_PD 7： TGCLK_SEL2 8： TGCLK_SEL1 6： TEST for CCD 36.000000MHz 30.000000MHz 24.000000MHz PLL2 1／8 27.000000MHz 19 VCLK VCLK_PD 20 VCLK_EN 12 Fig.77 Fig.78 Description of Terminal PIN No. PIN NAME 1 AVDD 2 AVDD 3 AVSS 4 XIN 5 XOUT 6 TEST 7 TGCLK_SEL2 8 TGCLK_SEL1 9 TGCLK_PD 10 TGCLK_EN 11 TGCLK 12 VCLK_EN 13 VSS1 14 VDD1 15 VDD1 16 UCLK 17 VSS2 18 VDD2 19 VCLK 20 VCLK_PD Function Analog power source Analog power source Analog GND Crystal IN Crystal OUT TEST pin, normally open, equipped with pull-down TGCLK frequency selection, equipped with pull-up TGCLK frequency selection, equipped with pull-up TGCLK Power-Down control, H:enable, L:Power-Down, equipped with pull-down TGCLK output control, H: Enable, L: Output fixed to L, equipped with pull-down 36M, 30M, 24M output VCLK output control, H:enable, L: Output fixed to L, equipped with pull-down TGCLK,UCLK & Internal digital GND TGCLK,UCLK & Internal digital power supply TGCLK,UCLK & Internal digital power supply 12M output VCLK GND VCLK power source 27M output VCLK Power-Down control, H:enable, L:Power-Down, equipped with pull-down Note) Basically, mount ICs to the substrate for use. If the ICs are not mounted to the substrate, the characteristics of ICs may not be fully demonstrated. Mount 0.1uF as bypass capacitors in the vicinity of the IC pins between 1&2 PIN and 3PIN, 13PIN and 14&15PIN, and 17PIN and 18PIN, respectively. ※Even though we believe that the example of the application circuit is worth of a recommendation, please be sure to thoroughly recheck the characteristics before use. ※As to the jitters, the TYP values vary with the substrate, power supply, output loads, noises, and others. Besides, for the use, the operating margin should be thoroughly checked. 14/16 ●Cautions on use (1) Absolute Maximum Ratings An excess in the absolute maximum ratings, such as applied voltage (VDD or VIN), operating temperature range (Topr), etc., can break down devices, thus making impossible to identify breaking mode such as a short circuit or an open circuit. If any special mode exceeding the absolute maximum ratings is assumed, consideration should be given to take physical safety measures including the use of fuses, etc. (2) Recommended operating conditions These conditions represent a range within which characteristics can be provided approximately as expected. The electrical characteristics are guaranteed under the conditions of each parameter. (3) Reverse connection of power supply connector The reverse connection of power supply connector can break down ICs. Take protective measures against the breakdown due to the reverse connection, such as mounting an external diode between the power supply and the IC’s power supply terminal. (4) Power supply line Design PCB pattern to provide low impedance for the wiring between the power supply and the GND lines. In this regard, for the digital block power supply and the analog block power supply, even though these power supplies has the same level of potential, separate the power supply pattern for the digital block from that for the analog block, thus suppressing the diffraction of digital noises to the analog block power supply resulting from impedance common to the wiring patterns. For the GND line, give consideration to design the patterns in a similar manner. Furthermore, for all power supply terminals to ICs, mount a capacitor between the power supply and the GND terminal. At the same time, in order to use an electrolytic capacitor, thoroughly check to be sure the characteristics of the capacitor to be used present no problem including the occurrence of capacity dropout at a low temperature, thus determining the constant. (5) GND voltage Make setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state. Furthermore, check to be sure no terminals are at a potential lower than the GND voltage including an actual electric transient. (6) Short circuit between terminals and erroneous mounting In order to mount ICs on a set PCB, pay thorough attention to the direction and offset of the ICs. Erroneous mounting can break down the ICs. Furthermore, if a short circuit occurs due to foreign matters entering between terminals or between the terminal and the power supply or the GND terminal, the ICs can break down. (7) Operation in strong electromagnetic field Be noted that using ICs in the strong electromagnetic field can malfunction them. (8) Inspection with set PCB On the inspection with the set PCB, if a capacitor is connected to a low-impedance IC terminal, the IC can suffer stress. Therefore, be sure to discharge from the set PCB by each process. Furthermore, in order to mount or dismount the set PCB to/from the jig for the inspection process, be sure to turn OFF the power supply and then mount the set PCB to the jig. After the completion of the inspection, be sure to turn OFF the power supply and then dismount it from the jig. In addition, for protection against static electricity, establish a ground for the assembly process and pay thorough attention to the transportation and the storage of the set PCB. (9) Input terminals In terms of the construction of IC, parasitic elements are inevitably formed in relation to potential. The operation of the parasitic element can cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the input terminal. Therefore, pay thorough attention not to handle the input terminals, such as to apply to the input terminals a voltage lower than the GND respectively, so that any parasitic element will operate. Furthermore, do not apply a voltage to the input terminals when no power supply voltage is applied to the IC. In addition, even if the power supply voltage is applied, apply to the input terminals a voltage lower than the power supply voltage or within the guaranteed value of electrical characteristics. (10) Ground wiring pattern If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well. (11) External capacitor In order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a degradation in the nominal capacitance due to DC bias and changes in the capacitance due to temperature, et 15/16 ●Name selection of ordered type B U 2 3 9 X K N - E 2 Part No. Type 2394, 2396 Package Type KN：VQFN20 Packing specification E2: Reel-like emboss taping VQFN20 4.2±0.1 4.0±0.1 15 16 11 Tape Quantity Direction of feed Embossed carrier tape(with dry pack) 2500pcs E2 (The direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand) (1.1) 3− 10 .3 (0 .5 (0 4.0±0.1 4.2±0.1 5) 1 0.22±0.05 5 0.5 +0.03 0.02 −0.02 0.95MAX 0.05 0.22 ± 0.05 (0 . 20 6 22 ) ) 1234 1234 1234 1234 1234 1234 +0.1 (0.6 −0.3) 0.05 Reel 1pin Direction of feed (Unit:mm) ※When you order , please order in times the amount of package quantity. Catalog No.08T802A '08.9 ROHM © Appendix Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM CO.,LTD. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law. Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact your nearest sales office. ROHM Customer Support System www.rohm.com Copyright © 2009 ROHM CO.,LTD. THE AMERICAS / EUROPE / ASIA / JAPAN Contact us : webmaster @ rohm.co. jp 21 Saiin Mizosaki-cho, Ukyo-ku, Kyoto 615-8585, Japan TEL : +81-75-311-2121 FAX : +81-75-315-0172 Appendix-Rev4.0