BU2506FV_11

DACs for Electronic Adjustment High-precision 10bit 8ch/10ch D/A Converters BU2506FV,BU2505FV No.11052EBT03 ●Description BU2506FV and BU2505FV ICs are high performance 10bit R-2R type DACs with 8ch and 10ch outputs, respectively. Cascade connection is possible, ensuring suitability with multi-channel applications. Each channel incorporates a full swing output-type buffer amplifier with high speed output response characteristics, resulting in a greatly shortened wait time. The ICs also utilize the TTL level input method, and with the RESET pin the output voltage can be kept in the lower reference voltage range. ●Features 1) High performance, multi-channel R-2R-type 10bit D/A converter built-in (BU2506FV: 8 channels, BU2505FV: 10 channels) 2) Full swing output type buffer amplifier incorporated at each output channel 3) The RESET terminal can keep the output voltage at all channels within the lower reference voltage range 4) Digital input compatible with TTL levels 5) 14bit 3-line serial data + RESET signal input (address 4bit + data 10bit) 6) Cascade connection available 7) LSB first / MSB first of 10bit data can be changed by the REVERSE terminal 8) Compact package: 0.65mm pitch, 20 pins (SSOP-B20) ●Applications DVDs, CD-Rs, CD-RWs, Digital cameras ●Lineup Parameter Power source voltage range Number of channels Differential non linearity error Integral non linearity error Data transfer frequency Package ●Absolute Maximum Ratings(Ta=25℃) Parameter Power source voltage D/A converter upper standard voltage Input voltage Output voltage Storage temperature range Power dissipation BU2505FV 4.5 to 5.5V 10ch ±1.0LSB ±3.5LSB 10MHz SSOP-B20 BU2506FV 4.5 to 5.5V 8ch ±1.0LSB ±3.5LSB 10MHz SSOP-B20 Symbol VCC VDD VIN VOUT Tstg Pd Ratings -0.3 to 6.0 -0.3 to 6.0 -0.3 to 6.0 -0.3 to 6.0 -55 to 125 400 * Unit V V V V ℃ mW * Derated at 4mW/℃ at Ta>25℃, mounted on a 70x70x1.6mm FR4 glass epoxy board (copper foil area less than 3%) Note: These products are not robust against radiation ●Recommended Operating Conditions(Ta=25℃) Parameter Symbol Power supply voltage range Operating temperature range VCC Topr Limits 4.5 to 5.5 -30 to 85 Unit V ℃ www.rohm.com © 2011ROHM Co., Ltd. All rights reserved. 1/10 2011.04 - Rev.B BU2506FV,BU2505FV ●Electrical Characteristics(Unless otherwise specified, VCC=5V, VrefH=5V, VrefL=0V, Ta=25℃) Limits Parameter Symbol Unit MIN. TYP. MAX. Power source current Input leak current Input voltage L Input voltage H Output voltage L Output voltage H Consumption current D/A converter upper standard voltage setting range D/A converter lower standard voltage setting range Buffer amplifier output voltage range IrefH VrefH VrefL VO 3.0 0 0.1 0.2 -2 -1.0 -3.5 -25 -25 12.5 4.5 3.7 5 25 7.5 6.2 5 1.5 4.9 4.75 2 1.0 3.5 25 25 15 37.5 mA mA (*1) Technical Note Conditions ICC IILK VIL VIH VOL VOH -5 2.0 0 4.6 0.85 - 2.8 5 0.8 0.4 5 mA μA V V V V At CLK=10MHz, IAO=0μA VIN=0 to VCC IOL=2.5mA IOH=-2.5mA Data condition : at maximum current Outputs are not necessarily within the standard voltage setting range, but ARE within the buffer amplifier output voltage range (VO). IO=±100μA IO=±1.0mA Upper side saturation voltage =0.35V (on full scale setting, current sourcing) Lower side saturation voltage =0.23V (on zero scale setting, current sinking) VrefH =4.796V VrefL=0.7V VCC=5.5V (4mV/LSB) At no load (IO=+0mA ) Input voltage 0V (Resistance value changes according to voltage supplied) V V V Buffer amplifier output drive range Differential non-linearity error Precision Integral non-linearity error Zero point error Full scale error Buffer amplifier output impedance Pull-up I/O internal resistance value IO DNL INL SZERO SFULL RO Rup mA LSB mV Ω kΩ *1 Value in the case where CH1 ~ CH8 are set to maximum current after reset www.rohm.com © 2011ROHM Co., Ltd. All rights reserved. 2/10 2011.04 - Rev.B BU2506FV,BU2505FV Technical Note ●Timing Characteristics(Unless otherwise specified, VCC=5V, VrefH=5V, VrefL=0V, Ta=25℃) Limits Conditions Parameter Symbol Unit MIN. TYP. MAX. Judgment level is 80% / 20% of VCC. Reset L pulse width Clock L pulse width Clock H pulse width Clock rise time Clock fall time Data setup time Data hold time Load setup time Load hold time Load H pulse width Data output delay time DA output settling time tRTL tCKL tCKH tcr tcf tDCH tCHD tCHL tLDC tLDH tDO tLDD 50 50 50 20 40 50 50 50 7 50 50 90 20 μS CL=100pF CL≦100pF, VO: 0.5V⇔4.5V. Until output value deference from final value becomes 1/2LSB. nS - RESET tRTL CLK tCKL DI tLDH LD DA OUTPUT tDo DO OUTPUT tDCH tCHD tCHL tLDD tLDC tcr tCKH tcf (note) LD signal is level triggered. When LD input is on H level, internal shift-register state is loaded to DAC control latch. Clock transition during LD=H is inhibited. www.rohm.com © 2011ROHM Co., Ltd. All rights reserved. 3/10 2011.04 - Rev.B BU2506FV,BU2505FV Technical Note ●Cascade Connection A data output terminal for cascade connection (DO) is available for reducing the number of parts when it is increased. The DO terminal can be connected to a data input terminal (DI) of the next IC. However, DO transition is synchronized with rising edge of clock signal, DO signal should be delayed, to keep a limit of data hold time. For example RC passive filter can be used. Also in some cases, an operation frequency of logic signal have to be decreased to ensure a margin of data setup time. DO LD CLK DI BU2505 FV BU2506 FV (#2) DO LD CLK CPU DI LD CLK DI BU2505 FV BU2506 FV (#1) Therefore, it is better to control LD port of each LSI separately, if extra CPU ports are available. In this case, more ports to control LD signals are needed, but a consideration described above doesn’t have do be done. LD1 LD CLK DI BU2505FV BU2506FV (#1) LD CLK DI BU2505FV BU2506FV (#2) LD2 DI CLK www.rohm.com © 2011ROHM Co., Ltd. All rights reserved. 4/10 2011.04 - Rev.B BU2506FV,BU2505FV BU2505FV VDD (VrefH) VCC 11 10 Technical Note BU2506FV VDD (VrefH) VSS (VrefL) AO3 AO4 AO5 Reverse Reset AO6 AO7 AO8 VCC 11 10 D/A 8 D/A 7 D/A ・・・ D13 TEST1 AO9 AO8 D/A D/A 12 12 9 L L 9 8 TEST2 AO10 AO7 D/A D/A 13 13 8 L L 10 7 AO6 DO D/A DO 14 14 7 L Address decoder ・・・ 6 D13 D10 11 12 Reset 14bit Shift register 14bit Shift register D10 11 12 LD 15 LD 15 6 Address decoder 6 D9 Reverse 8 CLK 7 CLK 16 16 5 6 7 8 D9 5 4 3 2 1 D0 AO5 D/A 17 DI D0 1 2 3 4 5 D/A 17 DI 4 L 5 AO1 AO4 AO1 D/A D/A 18 D/A 5 D/A 18 3 L L 1 4 1 10bit Latch 10bit Latch 10bit R-2R DA converter 10bit R-2R DA converter 10bit Latch 10bit R-2R DA converter 10bit Latch 4 10bit R-2R DA converter AO2 AO3 AO2 19 ・・・ 19 ・・・ 2 Ch2 Ch3 Ch2 Ch3 Buffer operation amplifier VSS (VrefL) GND GND 20 20 1 Buffer operation amplifier ●Terminal Descriptions Terminal No. Name 1 VSS 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 AO3 AO4 AO5 Reverse Reset AO6 AO7 AO8 VDD VCC AO9(TEST1) AO10(TEST2) DO LD CLK DI AO1 AO2 GND Analog / Digital Analog Analog Analog Analog Digital Digital Analog Analog Analog Analog Analog Analog Digital Digital Digital Digital Analog Analog - I/O O O O I I O O O O O O I I I O O - Description DA converter lower standard voltage (VrefL) input terminal 10bit D/A output(CH3) 10bit D/A output(CH4) 10bit D/A output(CH5) The reverse LSB and MSB of data designation 10bit in 14bit. All ch analog output L fixed 10bit D/A output(CH6) 10bit D/A output(CH7) 10bit D/A output(CH8) DA converter upper standard voltage (VrefH) input terminal Power source terminal 10bit D/A output(CH9) (BU2506FV : test terminal) 10bit D/A output(CH10) (BU2506FV : test terminal) This outputs bit data of LSB of 14bit shift register. LD terminal. When High level is input, the value of 14bit shift register is loaded to decoder and D/A output register. Shift clock input terminal. At rise of shift clock, the signal from DI terminal is input to 14bit shift register. Serial data input terminal. Serial data whose data length is 14bit (address 4bit + data 10bit) is input. 10bit D/A output(CH1) 10bit D/A output(CH2) GND terminal Equivalent Circuit 6 4 4 4 2 2 4 4 4 5 4 4 3 1 1 1 4 4 - *In the case of BU2506FV, be sure to leave the TEST1 and TEST2 terminals open www.rohm.com © 2011ROHM Co., Ltd. All rights reserved. 5/10 2011.04 - Rev.B 1 2 3 L L 4 L 5 6 6 7 L 8 L 9 L BU2506FV,BU2505FV ●Command Transmission 1) Reverse = open (or VCC short-circuit) setting (1) Data format Technical Note For D/A converter output setting For address selection (2) Data timing diagram ADDRESS LSB ADDRESS MSB DATA LSB DATA MSB DI CLK LD DACOUT D0 D1 D2 D3 D4 D11 D12 D13 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D6 0 0 0 0 : 1 1 D5 0 0 1 1 : 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D4 0 1 0 1 : 0 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Address Selection Inconsequential AO1 selection AO2 selection AO3 selection AO4 selection AO5 selection AO6 selection AO7 selection AO8 selection AO9 selection*1 AO10 selection*1 Inconsequential Inconsequential Inconsequential Inconsequential Inconsequential D13 D12 D11 0 0 0 0 0 0 0 0 0 0 0 0 : : : 1 1 1 1 1 1 2) Reverse = L setting (1) Data format D10 0 0 0 0 : 1 1 D9 0 0 0 0 : 1 1 D8 0 0 0 0 : 1 1 D7 0 0 0 0 : 1 1 D/A output (VrefH=VDD, VrefL=VSS) VrefL (VrefH-VrefL)/1024×1+VrefL (VrefH-VrefL)/1024×2+VrefL (VrefH-VrefL)/1024×3+VrefL : (VrefH-VrefL)/1024×1022+VrefL (VrefH-VrefL)/1024×1023+VrefL For D/A converter output setting For address selection (2) Data timing diagram ADDRESS LSB ADDRESS MSB DATA MSB DATA LSB DI CLK LD DACOUT D0 D1 D2 D3 D13 D6 D5 D4 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D11 0 0 0 0 : 1 1 D12 0 0 0 0 : 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D13 0 0 0 0 : 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Address selection Inconsequential AO1 selection AO2 selection AO3 selection AO4 selection AO5 selection AO6 selection AO7 selection AO8 selection AO9 selection*1 AO10 selection*1 Inconsequential Inconsequential Inconsequential Inconsequential Inconsequential D4 0 1 0 1 : 0 1 D5 0 0 1 1 : 1 1 D6 0 0 0 0 : 1 1 D7 0 0 0 0 : 1 1 D8 0 0 0 0 : 1 1 D9 0 0 0 0 : 1 1 D10 0 0 0 0 : 1 1 D/A output (VrefH=VDD, VrefL=VSS) VrefL (VrefH-VrefL)/1024×1+VrefL (VrefH-VrefL)/1024×2+VrefL (VrefH-VrefL)/1024×3+VrefL : (VrefH-VrefL)/1024×1022+VrefL (VrefH-VrefL)/1024×1023+VrefL *1 In the BU2506FV, this channel is for testing, therefore, do not designate. www.rohm.com © 2011ROHM Co., Ltd. All rights reserved. 6/10 2011.04 - Rev.B BU2506FV,BU2505FV ●Electrical Characteristics Curves 6 Technical Note 6 6 5 5 5 4 4 4 VOUT [V] 3 VOUT [V] VOUT [V] 3 3 2 2 2 1 1 1 0 0 200 400 600 800 1000 1200 0 0 200 400 600 800 1000 1200 0 0 200 400 600 800 1000 1200 Input Code [decimal] Input Code [decimal] Input Code [decimal] Fig.1 Output voltage linearity (-30℃) Fig.2 Output voltage linearity (25℃) Fig.3 Output voltage linearity (85℃) 1.5 40 1.5 1 35 1 0.5 DNL [LSB] 30 0.5 0 DNL [LSB] Rup [kΩ] 25 0 -0.5 20 -0.5 -1 15 -1 - 1.5 0 200 400 600 800 1000 1200 10 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 6 -1.5 0 200 400 600 800 1000 1200 Input Code [decimal] Vin [V] Input Code [decimal] Fig.4 Differential linearity error (-30℃) 1.5 Fig.5 Differential linearity error (25℃) 1.5 Fig.6 Differential linearity error (85℃) 1.5 1 1 1 0.5 0.5 0.5 INL [LSB] INL [LSB] 0 0 INL [LSB] 0 200 400 600 800 1000 1200 0 -0.5 -0.5 -0.5 -1 -1 -1 -1.5 0 200 400 600 800 1000 1200 -1.5 -1.5 0 200 400 600 800 1000 1200 Input Code [decimal] Input Code [decimal] Input Code [decimal] Fig.7 Integral linearity error (-30℃) 6 5 code=1FFh Fig.8 Integral linearity error (25℃) 2.52 Fig.9 Integral linearity error (85℃) 40 35 2.51 VOUT [V] ICC [mA] Rup [kΩ] 4 3 2 1 0 -40 code=000h Ta=-30℃ Ta=25℃ Ta=85℃ 30 2.5 25 Ta=25℃ Ta=85℃ 20 2.49 15 Ta=-30℃ code=3FFh 2 .48 -2.5 -1.5 -0.5 0.5 1.5 2.5 10 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 6 10 Temp. [ ℃ ] 60 IOUT [mA] Vin [V] Fig.10 Circuit current temperature characteristic Fig.11 Output load fluctuation characteristic (input code: 1FFh) Fig.12 Pull-up built in resistance characteristic www.rohm.com © 2011ROHM Co., Ltd. All rights reserved. 7/10 2011.04 - Rev.B BU2506FV,BU2505FV ●Equivalent Circuits *1 Technical Note 1 to inside 2 to inside 3 from inside 4 ・ 5 ・ 6 5 4 6 *1 25kΩ at Vcc = 5.0V (changes according to voltage supplied) ●Standard Example Application Circuit VrefH VCC AO1 CH1 VrefL AO2 CH2 AO3 Reverse Reset CH3 Controller LD CLK DI AO10 GND CH10 www.rohm.com © 2011ROHM Co., Ltd. All rights reserved. 8/10 2011.04 - Rev.B BU2506FV,BU2505FV ●Operation Notes Technical Note (1) The electrical characteristic and data on graphs for this datasheet, are typically evaluated value, and not guaranteed. (2) We suppose that application circuits are recommendable, but please make sufficient check for characteristics with the actual application. In case that value of external component for this LSI is changed, please check characteristic, not only static but also transient. (3) About absolute maximum ratings If operation condition is over the absolute maximum ratings, supply voltage or other operation range, LSI will be broken. Please don't apply any voltage or temperature over the absolute maximum ratings. If application have possibilities of become over the absolute maximum ratings, please take safety measures by using fuse and so on. Not to over absolute maximum ratings of LSI. (4) GND voltage Please keep GND voltage lowest of any other terminal of this LSI. Please confirm that other terminal voltages are not lower than GND. (5) Thermal design Please making a thermal design that allows for a sufficient margin in light of the power dissipation in actual operating condition. (6) About terminals short and wrong mounting Please pay full attention to the LSI direction and displacement when mounting LSI on PCB. If you assemble them by mistake and electrify it, LSI might be destroyed. And it is happen to short among LSI terminals or terminals and power supply, by foreign substance. (7) About operation in strong electromagnetic field If you use it in strong electromagnetic field, please evaluate fully as there is a possibility of malfunction. (8) Place a bypass capacitor as close as possible between each power supply terminal and ground in order to prevent deterioration of the D/A conversion accuracy due to ripple and noise signals from power supply or GND. (9) A capacitor should be placed between the analog output and ground in order to eliminate noise. A capacitance up to 100pF is recommended (including the capacitance of the wire). (10) This IC is selectable to decode the 10bit DI data pattern using either LSB first or MSB first, depending on the conditions of the REVERSE terminal. Therefore the reverse terminal should be open or VDD voltage (LSB first) or GND voltage (MSB first) www.rohm.com © 2011ROHM Co., Ltd. All rights reserved. 9/10 2011.04 - Rev.B BU2506FV,BU2505FV ●Ordering part number Technical Note B U 2 Part No. 2506 2505 5 0 6 F V - E 2 Part No. Package FV: SSOP-B20 Packaging and forming specification E2: Embossed tape and reel SSOP-B20 6.5 ± 0.2 20 11 Tape Quantity 0.3Min. Embossed carrier tape 2500pcs E2 The direction is the 1pin of product is at the upper left when you hold 6.4 ± 0.3 4.4 ± 0.2 Direction of feed ( reel on the left hand and you pull out the tape on the right hand ) 1 10 0.15 ± 0.1 1.15 ± 0.1 0.1± 0.1 0.1 0.65 0.22 ± 0.1 1pin (Unit : mm) Direction of feed Reel ∗ Order quantity needs to be multiple of the minimum quantity. www.rohm.com © 2011ROHM Co., Ltd. All rights reserved. 10/10 2011.04 - Rev.B Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. 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