BU38803

Video ICs System control servo BU38603 / BU38703 / BU38803 The BU38603, BU38703 and BU38803 are servo controller ICs for VCRs. They contain a high-speed, 8-bit CPU and perform the processing required for the drum, capstan, FV and PV completely in software, allowing a large reduction in the number of external components required. They also contain high-performance linear amplifiers, eliminating the need for interface ICs. Specialized hardware is included for items that require high-speed processing, to allow efficient utilization of the CPU. •Applications camcorders VHS VCRs and •Features 1) CPU 499 commands (69 types) Memory-mapped I / O Minimum command execution time: 250ns (8MHz) 2)ROM capacity BU38603: 16384 × 8 bit BU38703: 24576 × 8 bit BU38803: 32768 × 8 bit 3) RAM capacity: 512 × 8bit 4) Interrupt Pattern generator: 1 Watch-dog timer: 1 External interrupts: 1 FG interrupts: 5 Internal interrupts: 7 Two timers, serial transmission, interrupt, VHSW, CTL interval timer (fixed) / VISS ∗ Multi-layer interrupts possible. 5) Free-running counter: 19 bit 6) PWM output: 12 bit × 2 7) Pattern generator 17 bits from FRC MSB used. Output Internal: 3 bit External (PO): 5 bit External (PIO): 6 bit 8) Programmable pre-scaler CFG: 7 bit CTL: 6 bit 9) Head amplifier / chroma rotary Generated from pattern generator output. 10) Built-in AGC. Five-bits used to switch the gain control registers for the CTL amplifier. 11) CTL counter: 1 / 30 or 1 / 25 12) Data shift PLL calculation: 24 bit 13) Timer: 8 bit × 2 14) Synchronous serial input/output: 8 bit × 1 15) VH PULSE V separeted from composite synchronous snal. Pseudo V generated from pattern generator output. Superimposed pseudo H synchronized with the composite synchronous signal. 16) VISS / VASS VASS 0 / 1 discrimination VISS discrimination threshold: 3 Aspect discrimination. D / A CTL switching. 17) Standard I / O Parallel I / O (PIO): 32 bit Parallel output (PO): 6 bit 18) A / D converter: 8 bits × 8 channels Can be masked-programmed to be parallel inputs. 19) Watch-dog timer Setting period: 4 20) Linear circuits DFG: amplifier / comparator CFG: amplifier / comparator CTL: differential amplifier / comparator DPG: comparator 1 Video ICs BU38603 / BU38703 / BU38803 •Absolute maximum ratings (Ta = 25°C) Parameter Applied voltage Pin applied voltage Power dissipation Storage temperature range Symbol VDD, VDDA, VDAD VIN Pd Tstg Limits 0.3 ~ 7.0∗2 VSS – 0.3 ~ VDD + 0.3 500∗1 – 55 ~ + 125 Unit V V mW °C ∗1 Reduced by 5mW for each increase in Ta of 1°C over 25°C. ∗2 Use with VSS = VSSA = VSAD, and VDD = VDDA = VDAD. •Recommended operating conditions Parameter Power supply voltage Clock frequency Operating temperature Symbol VDD, VDDA, VDDB FCK Topr Limits 4.5 ~ 5.5 8 – 25 ~ + 75 Unit V MHz °C •Block diagram CPU ROM / RAM PO0-PO5 P1-P31 P0 PI / O PTG Timer SI SO SCK (P0) SI / O Interrupts Watchdog ADC0-ADC7 A / D converter Servo mode register Data bus PWM PWM0 PWM1 VHSW AHSW HAMPSW CHROT ENVIN FV CSYNC Head amp, chroma VH PULSE FRC Data shift COUNTP PBCTL Linear time counter CFG, CTL division Gain control VISSVASS Vref Linear CTL + CTL – CTLAMPOUT CTLAMP – DFGIN DFGOUT DPGIN CFGIN CFGOUT RESETB 2 Video ICs BU38603 / BU38703 / BU38803 •Pin descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin name VSAD ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 VDAD DFGOUT DFGIN DPGIN CFGIN CFGOUT VSSA Vref CTLAMP – CTLAMPOUT CTL – CTL + VDDA RESETB TEST PO5 PO4 P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 PO3 VHSW AHSW HAMPSW Parallel output and pattern generator output Pattern generator VHSW output Pattern generator AHSW output Head amplifier switch output Parallel I / O and pattern generator output Parallel I / O Parallel output A / D convertor circuit power supply. Drum FG amplifier output Drum FG amplifier input Drum PG comparator input Capstan FG amplifier input Capstan FG amplifier output Linear circuit GND Internal BIAS and power-on reset pin CTL amplifier – input CTL amplifier output CTL coil – connection CTL coil + connection Linear circuit power supply Power supply reset Test mode input (normally GND) Can be optionally mask – programmed to be either A / D or parallel inputs. Function A / D convertor circuit GND. Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Pin name CHROT FV VDD PWM0 PWM1 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 PO2 PO1 PO0 CLOCKO CLOCKI VSS P8 P7 P6 P5 P4 P3 P2 P1 P0 SI SO SCK ENVIN CSYNC COUNTP PBCTL Parallel I / O and external interrupt Serial I / O data input Serial I / O data I / O Serial I / O clock I / O Envelope detector logic input Composite signal logic input CTL counter pulse output CTL logic output Parallel I / O For connection of oscillator Logic circuit GND Parallel output Parallel I / O PWM output Function Chroma rotary switch output Pseudo Vsync output Logic circuit power supply 3 Video ICs BU38603 / BU38703 / BU38803 DD •Electrical characteristics (unless otherwise noted, Ta = 25°C, V Parameter Symbol Min. Typ. Max. = 5V and fOSC = 8MHz) Conditions Measurement circuit Unit [Logic block] (Logic: pins 24 to 80) Operating supply current 〈Logic I / O〉 Output high level voltage Output low level voltage Max. output low level current Input high level voltage Input low level voltage Input high level current Input low level current 〈Serial I / O〉 Input data hold Input data setup Output data delay TSH TSS TD 0.16 0.16 — — — — — — 0.3 µs µs µs Between CLOCK and DATA IDD — 12 19 mA No load, when reset Fig.1 VH VL ILL VIH VIL IH IL 4.0 — 10.0 4.0 — — – 1.0 4.5 0.5 16.0 — — 0 0 — 1.0 — — 1.0 1.0 — V V mA V V µA µA I = 2mA: except pins 66 to 73 I = 1mA: 66 to 73pin Fig.2 Fig.2 Fig.2 Fig.2 Fig.2 I = 2mA 66 to 73pin VIN = VDD VIN = 0 Fig.2 Fig.2 — — — [Linear block] (Linear: pins 11 to 23) Operating supply current [A / D block] (A / D: pins 1 to 10) Operating supply current Linearity error Input high level voltage Input low level voltage Input high level current Input low level current IAD EL VADPH VADPL IADPH IADPL — –3 4.0 — — – 1.0 0.6 0 — — 0 0 2.0 3 — 1.0 1.0 — mA LSB V V µA µA When P input selected When P input selected When P input selected, VIN = VDD When P input selected, VIN = 0 ILI — 10 26 mA No load Fig.1 Fig.1 Fig.3 Fig.3 Fig.3 Fig.3 Fig.3 4 Video ICs BU38603 / BU38703 / BU38803 •Measurement circuits 1k 10 22 43 11 12 1k 14 IclkI A 15 I1in A 63 SW1 TEST pin SW4 C A B V4 A V1 B C xtal A B Iclko C A V2 Itest A V3 B SW3 SW2 24 A 1 10 64 62 V V1out I4 Fig.1 Idad A 1k 10 11 12 14 15 SW1 A 18 B A 22 Idda A 43 Idd 1k A 63 SW2 SW3 62 SW4 2-9, 24, 27-36, 46-58 65-75, 77, 78 SW5 1 10 64 B xtal A B Fig.2 5 Video ICs BU38603 / BU38703 / BU38803 10 22 43 Iadin A V1 B A SW1 TEST pin (2-9) C D/A 23 1 10 64 Fig.3 •Application example Capstan control Control 8MHz Drum control Serial bus Interrupt PI / O ROM / RAM Data shift Watchdog Servo mode PWM Head amplifier · chroma Pattern generator ENVIN Head amplifier SW Chroma rotary SW AHSW VHSW SI / O Timer CPU FRC CSYNC Pseudo VSYNC Count pulse VHPULSE Linear time counter VISSVASS Amplifier gain control CFG. CTL divider RESET A/D DFGAMP DPG CFGAMP REF CTLAMP voltage CTL coil DFG DPG CFG Fig.4 6 Video ICs BU38603 / BU38703 / BU38803 •Electrical characteristic curves 20 LOGIC CIRCUIT CURRENT: IDD (mA) 18 “H” OUTPUT VOLTAGE: VH (V) 16 14 12 10 8 6 4 2 0 – 30 – 10 10 30 50 70 5 4.9 4.8 4.7 4.6 4.5 4.4 4.3 4.2 4.1 4 – 30 – 10 10 30 50 70 “L” OUTPUT VOLTAGE: VL (V) 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 – 30 – 10 10 30 50 70 TEMPERATURE: Ta (°C) TEMPERATURE: Ta (°C) TEMPERATURE: Ta (°C) Fig. 5 Logic circuit current. Fig. 6 Logic “H” output voltage. Fig. 7 Logic “L” output voltage. 26 LINEAR CIRCUIT CURRENT: ILI (mA) A / D CIRCUIT CURRENT: IAD (mA) 24 22 20 18 16 14 12 10 8 6 4 – 30 – 10 10 30 50 70 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 – 30 – 10 10 30 50 70 TEMPERATURE: Ta (°C) TEMPERATURE: Ta (°C) Fig. 8 Linear circuit current. Fig. 9 A / D circuit current. •External dimensions (Units: mm) 24.0 ± 0.3 20.0 ± 0.2 64 65 18.0 ± 0.3 14.0 ± 0.2 41 40 80 1 2.7 ± 0.1 24 25 0.05 0.8 0.35 ± 0.1 0.15 QFP80 1.2 0.15 ± 0.1 7