BU64240GWZ

1/5 STRUCTURE PRODUCT SERIES TYPE FEATURES Silicon Monolithic Integrated Circuit Motor Driver for electronic camera module BU64240GWZ ・Linear current sink driver ・10bit resolution current control 2 ・I C serial Interface ・Integrated current sense resistor ・Intelligent Slew Rate Control(ISRC) for mechanical ringing compensation P P Absolute maximum ratings Parameter Symbol Limit Unit Power supply voltage VCC -0.5 to +5.5 V Power save input voltage VPS -0.5 to 5.5 V Control input voltage※1 VIN -0.5 to 5.5 V Power dissipation Pd 220※2 mW Operating temperature range Topr -25 to +85 °C Junction temperature Tjmax 125 °C Storage temperature range Tstg -55 to +125 °C Output current Iout +200※3 mA ※1 VIN is I2C BUS input pin (SCL, SDA). ※2 Reduced by 2.2 mW/°C over 25°C, when mounted on a glass epoxy board (50mm  58mm  1.75mm; 8 layers) ※3 Must not exceed Pd, ASO, or Tjmax of 125°C. P P Operating Conditions (Ta= -25°C to +85°C) Parameter Symbol Power supply voltage VCC Power save input voltage VPS Control input voltage VIN 2 I C Bus Frequency fCLK Output current Iout ※4 Must not exceed Pd, ASO. P P Min. 2.3 0 0 - Typ. 3.0 - Max. 4.8 4.8 4.8 400 130※4 P Unit V V V kHz mA REV. A 2/5  Electrical Characteristics (Unless otherwise specified Ta=25°C, VCC=3.0V ) Limit Parameter Symbol Unit Min. Typ. Max. Overall Circuit current during standby operation Conditions ICCST ICC - 0 0.6 10 126 130 1 150 - 5 1.0 VCC 0.5 10 10 VCC 0.5 0.4 10 10 2.2 1 4 143 5 200 VCC μA mA V V μA μA V V V μA μA V Bits LSB LSB μA mA mA mV V PS=0V PS=3V, SCL=400kHz Circuit current Power save input High level input voltage Low level input voltage VPSH 1.26 VPSL 0 Low level input current IPSL -10 High level input current IPSH -10 Control input (VIN=SCL, SDA) High level input voltage VINH 1.26 Low level input voltage VINL 0 Low level output voltage VINOL High level input current IINH -10 Low level input current IINL -10 UVLO UVLO voltage VUVLO 1.6 10bit D/A converter(for setting limit voltage) Resolution DRES Differential Nonlinearity DDNL -1 Integral Nonlinearity DINL -4 Constant-Current Driver block Output current resolution IORES Output maximum current IOMAX 117 Zero code offset current IOOFS 0 Output Voltage VOUT Maximum applied voltage VOMAX - VPS=0V VPS=3V IIN=+3.0mA (SDA) Input voltage=0.9×VIN Input voltage=0.1×VIN DACcode = 3’h3FF DACcode = 3’h000 Io = 100mA This specification is supposed to be revised for improvement etc. REV. A 3/5 Package Outline Pin Arrangement (Top View) 1 2 3 Top View A PS SCL SDA B OUT GND VCC Fig.2 BU64240GWZ Pin Arrangement (Top View) Side View Block Diagram 0.1～10uF VCC VCC PS VCC Power Save TSD & UVLO BandGap ISINK SDA Bottom View SCL I2C bus Interface & slew rate control 10 OSC 10bit DAC OUT Pre Driver V/I convertor RNF =0.5Ω Fig.1 UCSP30L1 Package (Unit: mm) I2C BUS Format (Fast mode: SCL=400kHz ) W rite m ode（R /W = 0) S 0 0 0 1 1 0 O utput from M aster 0 R /W BandGap VREF GND Fig.3 BU64240GWZ Block Diagram O utput from Slave U pdate A P S EN W 2 W 1 W 0 M D 9 D 8 A D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 A R ead m ode S 0 0 0 1 1 00 W rite 0 0 0 A P S EN W 2 W 1 W 0 M ※ ※ A U pdate W (register address) 1 A P S EN W 2 W 1 W 0 M CD9 CD8 S 0 0 0 1 1 A CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0 A R ead S : start signal A : acknow ledge P : stop signal nA : non acknow ledge ※ : D on`t care Register name PS EN M Setting item Serial power save OUT pin status Mode select signal Description '0' = Standby mode, '1' = Operating mode '0' = Hi-impedance, '1' = Constant current sink. '0' = ISRC Mode Disabled, '1' = ISRC Mode Enabled ‘000’ = Limit Voltage setting, '001' = Operating parameter setting1 W2W1W0 Register address ‘010’ = Operating parameter setting2, ‘011’ = Operating parameter setting 3 ‘100’ = Operating parameter setting4 Limit Voltage Operating parameter1 D9～D0 Operating parameter2 Operating parameter3 Operating parameter4 Target position DAC code[D9:D0] Resonance frequency setting[D7:D3], Slew rate speed setting[D1:D0] VCM un-control current setting1[D9:D0] VCM un-control current setting2[D9:D0] Step resolution[D7:D5] ( Minimum step resolution = 1LSB@10bit_DAC) Step time setting[D4:D0] ( Minimum step time resolution = 50us ) REV. A 4/5 Characteristics of the SDA and SCL bus lines for 2-wire serial interface. (Unless otherwise specified, Ta=-25～+85°C, VCC=2.3～4.8V ) Parameter LOW level input voltage High level input voltage Hysteresis of Schmitt trigger inputs LOW level output voltage at 3mA sink current Pulse width of spikes which must be suppressed by the input filter Input current each I/O pin with an input voltage between 0.1V and 0.9VINmax SCL clock frequency Hold time (repeated) START condition. After this period, the first clock pulse is generated LOW period of the SCL clock High period of the SCL clock Set-up time for repeated START condition Data hold time Data set-up time Set-up time for STOP condition Bus free time between a STOP and START condition ※6 Symbol VIL VIH Vhys VOL tSP Ii fSCL tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tSU;STO tBUF STANDARD-MODE※6 Min. Max. -0.5 0.5 1.26 4.8 0 0.4 0 -10 4.0 4.7 4.0 4.7 0 250 4.0 4.7 50 10 100 3.45 - FAST-MODE※6 Min. Max. -0.5 0.5 1.26 4.8 0.15 0 0.4 0 -10 0.6 1.3 0.6 0.6 0 100 0.6 1.3 50 10 400 0.9 - Unit V V V V ns uA kHz us us us us us ns us us STANDARD-MODE and FAST-MODE 2-wire serial interface devices must be able to transmit or receive at that speed. The maximum bit transfer rates of 100 kbit/s for STANDARD-MODE devices and 400 kbit/s for FAST-MODE devices This transfer rates is provided the maximum transfer rates, for example it is able to drive 100 kbit/s of clocks with FAST-MODE. Definition of timing on the 2-wire serial interface tHIGH SCL SCL tHD : STA SDA tBUF tSU : DAT tLOW tHD : DAT tSU : STA SDA tHD : STA tSU : STO START BIT STOP BIT Fig.4 Definition of timing for serial data Fig.5 Definition of timing for START and STOP bit REV. A 5/5 Operation Notes (1) Absolute maximum ratings Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range (Topr) may result in IC damage. Assumptions should not be made regarding the state of the IC (short mode or open mode) when such damage is suffered. The implementation of a physical safety measure such as a fuse should be considered when use of the IC in a special mode where the absolute maximum ratings may be exceeded is anticipated. (2) Power supply lines Regenerated current may flow as a result of the motor's back electromotive force. Insert capacitors between the power supply and ground pins to serve as a route for regenerated current. Determine the capacitance in full consideration of all the characteristics of the electrolytic capacitor, because the electrolytic capacitor may loose some capacitance at low temperatures. If the connected power supply does not have sufficient current absorption capacity, regenerative current will cause the voltage on the power supply line to rise, which combined with the product and its peripheral circuitry may exceed the absolute maximum ratings. It is recommended to implement a physical safety measure such as the insertion of a voltage clamp diode between the power supply and GND pins. (3) Ground potential Ensure a minimum GND pin potential in all operating conditions. (4) Setting of heat Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. (5) Actions in strong magnetic field Use caution when using the IC in the presence of a strong magnetic field as doing so may cause the IC to malfunction. (6) ASO When using the IC, set the output transistor for the motor so that it does not exceed absolute maximum ratings or ASO. (7) Thermal shutdown circuit This IC incorporates a TSD (thermal shutdown) circuit (TSD circuit). If the temperature of the chip reaches the following temperature, the motor coil output will be opened. The thermal shutdown circuit (TSD circuit) is designed only to shut the IC off to prevent runaway thermal operation. It is not designed to protect the IC or guarantee its operation. Do not continue to use the IC after operating this circuit or use the IC in an environment where the operation of this circuit is assumed. TSD ON temperature [°C] Hysteresis temperature [°C] (Typ.) (Typ.) 150 20 (8) Ground Wiring Pattern When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing a single ground point at the application's reference point so that the pattern wiring resistance and voltage variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring pattern of any external components, either. (9) Power Save (PS) terminal PS holds the reset function on logic concurrently. Please release PS after the start-up of VCC. Reset is not normally done when VCC is short-circuited to PS and it uses it, and there is a possibility of malfunctions. This specification is supposed to be revised for improvement etc REV. A Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. 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