BU6568GVW-E2

For Home Electronics and Security Devices Camera Image Processor Series Camera Image Processors Compatible with JPEG Image BU6566GVW, BU6568GV No.09061JET02 ●Description BU6566GVW/BU6568GV is a camera image processor compatible with standard JPEG. Pin-to-Pin compatibility enable support for both standard and high-resolution cameras. ●Features 1) Built-in Camera Module Interface VGA size (640×480)/BU6566GVW, SXGA size (1280×1024)/BU6568GV for input of image data up to 15 fps (zooming function is available). Input data format for YUV=4:2:2, RGB=4:4:4. Filter processing (image processing) to input images (2 gradations / gray scale / sepia / emboss / edge enhancement/ negative). Multi-step size reduction down to 1/8 (BU6566GVW), 1/16 (BU6568GV) in X- and Y-direction possible. Cutting out into an arbitrary size after resizing. D range enlargement processing of Y (brightness) available in YUV color space to cut images. Cut images to be stored into an arbitrary position in frame memory in YUV=4:2:2 format. 2-line serial interface built in for camera module control. 2) Built-in frame memory / JPEG code memory Image frame memory built in (80KB for storing 1 frame of 176x232 @16 bits/pixel). Display area settable to an arbitrary LCD size. Data to be stored into image frame memory in YUV=4:2:2 format. Mask data to be stored into mask frame memory in 1bit/2pixels in YUV=4:2:2 format. An arbitrary position of frame memory to be updated to camera image according to mask memory. Image frame memory accessible from HOST CPU (access available both in RGB and YUV). Rectangular writing function and rectangular reading function for transparent color to image frame memory. Frame memory usable as JPEG code memory (80KB) to store JPEG compressed images. Frame memory usable as a ring buffer for JPEG code of 80KB or more. 3) Built-in LCD controller interface Built-in input/output interface to LCD controller For display colors of 262144 colors / 65536 colors / 4096 colors. Up to 2 LCD module controllers controllable. Arbitrary rectangular selection in frame memory to be transferred to LCD controller. 4) Built-in JPEG CODEC ISO/IEC10918 conforming base line method. ･Compression For YUV=4:2:2 only. Quantization table selectable from 20 built-in tables. ･Decompression For YUV=4:4:4, 4:2:2(horizontal sub-sampling:BU6566GVW), 4:2:0, 4:1:1(horizontal sub-sampling:BU6566GVW), and gray scale. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 1/16 2009.04 - Rev.B BU6566GVW, BU6568GV 5) Built-in HOST CPU interface For 8-bit/16-bit bus interface in parallel interface. Read/ write access to frame memory. Read/ write access to internal registers (Indirect access with a index register as the address). Technical Note Read/ write access to the LCD controller: Parallel/Serial (Direct access available via the LCD interface). 6) Extended overlay function Supporting overlay of icon-data/font-data of up to two points during LCD data transfer. Both icon-data and font-data corresponding to 65536 display colors. Possible to setting transparent colors. 7) LED interface, GIO function Built-in PWM output of 4 systems for 3 color LED controls and white LED control. 7 GIO's in total available for the GIO function. 8) Clock generation, power management function Oscillation circuit configuration by XIN and XOUT terminals, or clock input from XIN terminal available. Built-in PLL in BU6568GV. Clock control of IC inside in unit of block (suspend mode available). 9) Key interfaces built in 3 systems of key interfaces built in. Interruption to be generated at key input. Useable for removing software chattering. ＊Data is prepared separately about each register setup. Please refer to the Development Scheme on page 14. System 1 (VDDIO1) P3-P4(D15-14),P6-P11(D13-8), P14-P18(D7-0),P23(A2), P28-P31(A1,CSB,WRB,RDB), P97-P98(XOUT,XIN),P33(INT*1) System 2 (VDDIO2) P34-P44(CAMVS, CAMHS, CAMD0-3, GIO2, CAMD4-7), P46(CAMCKI), P48(CAMCKO), P53-P65(SDA, SDC, LEDCNT, PWM1-3, VD, LCDCS1B, LCDCS2B, KEY0, LCDWRB, LCDRDB, LCDA0) P67-P69(LCDD0-2), P71-P72(LCDD3-4) P78-P87(LCDD5-7, TEST, X16_8, LCDD8-12), P89-P94(KEY1, LCDD13-15, RESETB, PWM0) *1； P33 (INT) terminal is the power source system of VDDIO2 in BU6568GV. ●Application Security camera, Intercom with camera, Drive recorder, and Web camera etc. ●Lineup Power source Parameter voltage IO1:HOSTI/F IO2:Camera, LCD Supported up to BU6566GVW 1.45-1.55V(VDDCore) 1.70-3.15V(VDDIO1) BU6568GV 2.70-3.15V(VDDIO2) 0.3M pixels. (640×480) Supported up to 1.3M pixels. (1280×1024) 8bit/16bit bus 80 systems CPU Interface Supported up to QCIF+(232×176) 0.3M pixels JPEG Codec Motion-JPEG 1.3M pixels JPEG Codec Motion-JPEG SBGA099T070 SBGA099W070 Camera interface Host CPU interface LCD interface Codec [Image] Multimedia interface Package ＊Although QCIF+ is 220x176 pixels, it is supported to 232x176 pixels by effective use of memory in ROHM products. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 2/16 2009.04 - Rev.B BU6566GVW, BU6568GV Technical Note ●Absolute maximum ratings Parameter Applied power source voltage 1 Applied power source voltage 2 Applied power source voltage 3 Other terminals Storage temperature range Power dissipation Symbol VDDIO1 VDDIO2 VDD Tstg PD (Ta=25℃) Rating -0.3～+4.2 -0.3～+4.2 -0.3～+2.1 -0.3～ VDDIO+0.3 -40～+150 410 Unit V V V V ℃ ｍＷ ●Recommended operating range Parameter Applied power source voltage 1 Applied power source voltage 2 Applied power source voltage 3 Input voltage range Operating temperature range Symbol VDDIO1 VDDIO2 VDD VIN Topr Rating 1.70～3.15(Typ:1.80V) 2.70～3.15(Typ:2.85V) 1.45～1.55(Typ:1.50V) 0～VDDIO -30～+85 Unit V V V V ℃ ＊Please supply power source in order of VDD→VDDIO1→VDDIO2. ＊In the case exceeding 25ºC, 4.1mW should be reduced at the rating 1ºC. ●Electric characteristics (Unless otherwise specified, Ta=25℃,VDD=1.50V,VDDIO=2.85V, fin=30.0MHz,fSYS=30.0MHz/BU6566GVW fin=13.0MHz ,fSYS=52.0MHz (using PLL)/BU6568GV) Limits Parameter Symbol Unit Condition MIN. TYP. MAX. BU6566GVW XIN 30.0 Input frequency ｆIN MHz /30.0 BU6568GV XIN (Duty 50±5%), at PLL OFF BU6566GVW Internal 30.0 ｆSYS MHz Internal SCLK frequency operating frequency /52.0 BU6568GV BU6566GVW At camera ON, LCD display ON Operating 6.4 IDD mA consumption current /15 BU6568GV At viewer operating BU6566GVW Static consumption 50 IDDst μA At suspend mode setting current /100 BU6568GV Input "H" current 1 Input "H" current 2 Input "H" current 3 Input "L" current 1 Input "L" current 2 Input "L" current 3 Input "H" voltage1 Input "L" voltage 1 Input "H" voltage 2 Input "L" voltage 2 Hysteresis width voltage IIH1 IIH2 IIH3 IIL1 IIL2 IIL3 VIH1 VIL1 VIH2 VIL2 Vhys VOH1 VOL1 -10 25 -10 -10 -10 -160 VDDIO ×0.8 -0.3 VDDIO ×0.85 -0.3 VDDIO -0.4 0.0 50 -80 0.9 /0.6 - 10 100 10 10 10 -25 VDDIO +0.3 VDDIO ×0.2 VDDIO +0.3 VDDIO ×0.15 VDDIO 0.4 μA μA μA μA μA μA V V V V V V V BU6566GVW BU6568GV VIH=VDDIO Pull-Down terminal, VIH=VDDIO Pull-Up terminal, VIH=VDDIO VIL=GND Pull-Down terminal, VIL=GND Pull-Up terminal, VIL=GND Normal input (including input mode of I/O terminal) Normal input (including input mode of I/O terminal) Hysteresis input Hysteresis input Hysteresis input IOH1=-1.0mA(DC) (Including output mode of I/O terminal) IOL1=1.0mA(DC) (Including output mode of I/O terminal) Output "H" voltage 1 Output "L" voltage 1 www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 3/16 2009.04 - Rev.B BU6566GVW, BU6568GV ●Block Diagram HOST CPU interface HOST CPU I/F Register Array LCD Controller I/F LCD Control display data Technical Note YUV=4:2:2 RGB=5:6:5 Camera interface RGB⇔YUV Color space conversion YUV=4:2:2 Image processing (filtering) Multi-step zooming YUV=4:4:4 MEMORY I/F JPEG Codec For LCD display data For JPEG compression data 80KB Cutting size Brightness Component Changing D-range YUV=4:2:2 Camera control 2-line type serial Frame buffer camera image storage status interruption Interruption to HOST CPU : INT 2-line serial control Clock control Power down control XIN,XOUT RESETB General purpose input / output PWM control GIO PWM control KEY input control ●Recommended Application Circuit CAMCKO CAMVS CAMCKI Camera module CAMHS CAMD[7:0] SDC SDA A2 A1 Host CPU OE WE RESETB CS D[15:0] A2 A1 D[15:0] BU6566GVW RDB WRB CSB /BU6568GV LCDA0 LCDD[15:0] LCDWRB LCDCS1B LCDCS2B VD RESETB MAIN LCD SUB PWM0 PWM1 PWM2 PWM3 LCD LED driver ＊Data is prepared separately about each register setup. Please refer to the Development Scheme on page 14. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 4/16 2009.04 - Rev.B BU6566GVW, BU6568GV ●Terminal functions PIN No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Land No. A1 B2 B1 C2 C1 D3 D2 D1 E1 E2 E3 E4 F5 F4 F3 F2 F1 G1 G2 G3 PIN Name In /Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In In In In In In In In Out In In In In In In In/Out In In In In In Out Active Level PWR DATA DATA DATA DATA DATA DATA DATA DATA DATA GND PWR DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA GND PWR DATA DATA Low Low Low Low Low -*2 Low Out/Lo w Low Camera clock output Interruption signal Camera vertical timing signal (pull down at CAMOFF) Camera horizontal timing signal (pull down at CAMOFF) Technical Note Init Function explanation Function division HOST IF HOST IF I/O type BU6566GV W I/O type BU6568G V N.C. VDDIO1 D15/HOST_MODE D15/EXGIO7 D14/EXGIO6 N.C. D13/EXGIO5 D12/EXGIO4 D11/EXGIO3 D10/EXGIO2 D9/EXGIO1 D8/EXGIO0 GND VDD D7 D6 D5 D4 D3 D2 D1/SIF_RD D1 IN *1 IN *1 IN *1 IN *1 IN *1 IN *1 IN *1 IN *1 IN *1 IN *1 IN *1 IN *1 IN *1 IN *1 IN *1 IN *1 IN *1 IN *1 IN *1 - *2 Host data bus bit 2 Common ground Host data bus bit 13 Host data bus bit 12 Host data bus bit 11 Host data bus bit 10 Host data bus bit 9 Host data bus bit 8 Common ground Digital I/O power source (system 1) Switch parallel / Serial of HOST I/F (BU6566GVW F*3 F F F F F F F E E E E E E E - H H H H H H H H G G G G G G G G A A K K K D B B B B B B H B B B B B D Host data bus bit 15 Host data bus bit 14 - HOST IF HOST IF HOST IF HOST IF HOST IF HOST IF HOST IF HOST IF HOST IF HOST IF HOST IF HOST IF HOST IF Digital core power source Host data bus bit 7 Host data bus bit 6 Host data bus bit 5 Host data bus bit 4 Host data bus bit 3 Host data bus bit 2 Host data bus bit 1 Serial data from BU6566GVW to HOST Host data bus bit 1 Host data bus bit 0 Serial data from HOST to BU6566GVW Host data bus bit 0 - 21 22 23 24 25 26 27 28 H1 H2 J1 G4 H3 K1 J2 K2 D0/SIF/WD D0 N.C. A2 GND N.C. N.C. VDDIO1 A1/SIF_CD A1 HOST IF HOST IF E A A - Digital I/O power source (system 1) Host address bus bit 1 signal Command / data identification in HOST serial I/F(BU6566GVW HOST IF Host address bus bit 1 Chip select signal Chip select signal in HOST serial I/F(BU6566GVW only) 29 J3 CSB/SIF_CS1 CSB HOST IF A - Chip select signal Write enable signal Serial clock in HOST serial I/F(BU6566GVW only) Write enable signal Read enable signal HOST IF HOST IF CAMERA CAMERA CAMERA CAMERA CAMERA CAMERA SYSTEM CAMERA CAMERA CAMERA CAMERA CAMERA CAMERA HOST IF 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 K3 H4 J4 K4 K5 J5 H5 G5 F6 G6 H6 J6 K6 K7 J7 H7 K8 J8 K9 WRB/SIF_SCK WRB RDB N.C. INT CAMVS CAMHS CAMD0 CAMD1 CAMD2 CAMD3 GIO2 / KEY2 CAMD4 CAMD5 CAMD6 CAMD7 VDDIO2 CAMCKI N.C. CAMCKO C C D B B B B B B H B B B B B D ＊ ＊ ＊ DATA DATA DATA DATA DATA DATA DATA DATA DATA PWR CLK CLK Camera data input bit0 (pull down at CAMOFF) Camera data input bit1 (pull down at CAMOFF) Camera data input bit2 (pull down at CAMOFF) Camera data input bit3 (pull down at CAMOFF) General purpose I/O2 / Key input2 (pull down for register control) Camera data input bit4 (pull down at CAMOFF) Camera data input bit5 (pull down at CAMOFF) Camera data input bit6 (pull down at CAMOFF) Camera data input bit7 (pull down at CAMOFF) Digital I/O power source (system 2) Camera clock input (pull down at CAMOFF) - www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 5/16 2009.04 - Rev.B BU6566GVW, BU6568GV Technical Note PIN No. 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Land No. G7 K10 J9 J10 H9 H10 G8 G9 G10 F10 F9 F8 F7 E6 E7 E8 E9 E10 D10 D9 D8 C10 C9 B10 D7 C8 A10 B9 A9 B8 A8 C7 B7 A7 A6 B6 C6 D6 E5 D5 C5 B5 A5 A4 B4 C4 A3 B3 A2 D4 C3 PIN Name GND N.C. N.C. VDD SDA SDC LEDCNT/GIO1 PWM1/GIO3 PWM2/GIO4 PWM3/GIO5 VD/GIO6 LCDCS1B LCDCS2B KEY0 LCDWRB LCDRDB LCDA0 VDDIO2 LCDD0 LCDD1 LCDD2 N.C. LCDD3 LCDD4 N.C. GND N.C. N.C. VDD LCDD5 LCDD6 / SCL LCDD7 / SI TEST X16_8 LCDD8 LCDD9 LCDD10 LCDD11 LCDD12 N.C. KEY1 LCDD13 LCDD14 LCDD15 RESETB PWM0/GIO0 VDDIO1 N.C. XOUT XIN GND N.C. In /Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out Out Out In Out Out Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In In In/Out In/Out In/Out In/Out In/Out In In/Out In/Out In/Out In In/Out Out In - Active Level GND PWR DATA CLK Init Out/Lo Out/Lo In *5 In *5 In *5 In *5 In *5 High Out/Lo Out/Lo Out/Lo Out/Lo Out/Lo Out/Lo Out/Lo Out/Lo Out/Lo Out/Lo Out/Lo Out/Lo Out/Lo Out/Lo Out/Lo Out/Lo Out/Lo Out/Lo In *5 High Key input Function explanation Common ground Digital core power source Serial control input / output Serial clock output LED PWM control signal / General purpose input1 LED PWM control signal1/ General purpose input3 LED PWM control signal2/ General purpose input4 LED PWM control signal3/ General purpose input5 LCD controller vertical synchronization signal/ general purpose Function division CAMERA CAMERA SYSTEM SYSTEM SYSTEM SYSTEM LCD IF LCD IF LCD IF SYSTEM LCD IF LCD IF LCD IF LCD IF LCD IF LCD IF LCD IF LCD IF LCD IF LCD IF LCD IF SYSTEM SYSTEM LCD IF LCD IF LCD IF LCD IF LCD IF SYSTEM LCD IF LCD IF LCD IF SYSTEM SYSTEM SYSTEM SYSTEM - I/O type BU6566GV I/O BU6568G J J H H H H H D D H*6 G*4 G*4 G*4 H H H H H H H H H H B A H H H H H H*6 H H H C H I C,I - J J H H H H H D D H*6 G*4 G*4 G*4 H H H H H H H H H H B A H H H H H H*6 H H H K H I K,I - ＊ - ＊ Low Low LCD controller chip select 1 LCD controller chip select 2 KEY input LCD controller write enable signal LCD controller read enable signal LCD controller command parameter identification signal ＊ Low Low ＊ PWR DATA DATA DATA DATA DATA GND PWR DATA DATA DATA DATA DATA Low DATA DATA DATA DATA DATA DATA DATA DATA Low DATA PWR CLK CLK GND - Digital IO power source (system 2) LCD controller data bus bit 0 LCD controller data bus bit 1 LCD controller data bus bit 2 LCD controller data bus bit 3 LCD controller data bus bit 4 Common ground Digital core power source LCD controller data bus bit 5 LCD controller data bus bit 6 LCD clock of serial transmission (BU6566GVW LCD controller data bus bit 7 LCD data of serial transmission (BU6566GVW only) Test mode terminal (Connect with GND) Host data bus 16-bit / 8-bit selection LCD controller data bus bit 8 LCD controller data bus bit 9 LCD controller data bus bit 10 LCD controller data bus bit 11 LCD controller data bus bit 12 LCD controller data bus bit 13 LCD controller data bus bit 14 LCD controller data bus bit 15 System reset signal LED PWM control signal0/ General purpose input / Digital IO power source (system 1) Clock output (always HIGH output at setting of external input) Clock input *7 Common ground - - ＊"＊" in Active Level column means active level can be changed by setting of register. Moreover, Init is a pin state at the time of reset release. *1: Under the condition of RESETB="L" or CSB= "H". *2: Please connect A2 and RDB to GND when to use Host serial I/F. *3: Pull down only except for a test mode. *4: Input only except for a test mode. *5: Pull down while RESETB=’L’(initial state). *6: Output only except for a test mode. *7: The crystal oscillation circuit does not include a return resistance, so it is needed to examine an external circuit including return resistance. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 6/16 2009.04 - Rev.B BU6566GVW, BU6568GV ●Equivalent Circuit Structures of input / output pins. Type Equivalent circuit structure VDDIO VDDIO Technical Note Type Equivalent circuit structure VDDIO VDDIO Internal signal A To internal B To internal GND GND GND GND GND Input terminal VDDIO PULL-DOWN Input terminal VDDIO VDDIO C GND To internal D Internal signal Internal signal Hysteresis input terminal with SUSPEND VDDIO Internal signal GND Output terminal GND VDDIO Internal signal To internal VDDIO VDDIO To internal VDDIO VDDIO E Internal signal F GND Internal signal Internal signal GND GND GND Internal signal GND Internal signal GND GND Internal signal Internal signal I/O terminal with SUSPEND VDDIO VDDIO VDDIO To internal PULL-DOWN I/O terminal with SUSPEND VDDIO VDDIO VDDIO To internal Internal signal Internal signal G GND Internal signal H GND GND Internal signal Internal signal GND Internal signal GND GND GND Internal signal I/O terminal Internal signal VDDIO XIN PULL-DOWN I/O terminal VDDIO Internal signal VDDIO Internal signal VDDIO VDDIO VDDIO To Internal VDDIO GND Internal signal I VDDIO XOUT GND J GND To internal Internal signal GND GND Internal signal GND Clock input terminaD PULL-UP I/O terminal GND Internal signal www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 7/16 2009.04 - Rev.B BU6566GVW, BU6568GV Type Equivalent circuit structure VDDIO Technical Note Type Equivalent circuit structure VDDIO Internal signal K To internal L GND GND To internal GND Hysterisisinput terminal (only for BU6568GV) PULL-DOWN Hysterisisinput terminal (only for BU6568GV) VDDIO VDDIO Internal signal Internal signal GND GND M Internal signal Pull-up 3-state output terminal (only for BU6568GV) ●Terminal Layout K 26 NC 28 A1 30 WRB 33 INT 34 CAMVS 42 CAMD5 43 CAMD6 46 CAMCKI 48 CAMCKO 51 NC J 23 A2 27 VDDIO1 29 CSB 32 NC 35 CAMHS 41 CAMD4 44 CAMD7 47 NC 52 VDD 53 SDA H 21 D0 22 NC 25 NC 31 RDB 36 CAMD0 40 GIO2 45 VDDIO2 50 NC 54 SDC 55 LEDCNT G 18 D3 19 D2 20 D1 24 GND 37 CAMD1 39 CAMD3 49 GND 56 PWM1 57 PWM2 58 PWM3 F 17 D4 16 D5 15 D6 14 D7 13 VDD 38 CAMD2 62 KEY0 61 LCDCS2B 60 LCDCS1B 59 VD E 9 D10 10 D9 11 D8 12 GND 88 NC 63 LCDWRB 64 LCDRDB 65 LCDA0 66 VDDIO2 67 LCDD0 D 8 D11 7 D12 6 D13 99 GND 89 KEY1 87 LCDD12 74 GND 70 NC 69 LCDD2 68 LCDD1 C 4 D14 100 NC 95 VDDIO1 90 LCDD13 86 LCDD11 81 TEST 75 NC 72 LCDD4 71 LCDD3 B 3 D15 2 VDDIO1 97 XOUT 94 PWM0 91 LCDD14 85 LCDD10 82 X16_8 79 LCDD6 77 VDD 73 NC A 1 NC 98 XIN 96 NC 93 RESETB 92 LCDD15 84 LCDD9 83 LCDD8 80 LCDD7 78 LCDD5 76 NC 1pin marker (Top View) corner. 1 2 3 4 5 6 7 8 9 10 （Bottom View） www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 8/16 2009.04 - Rev.B BU6566GVW, BU6568GV ●Timing Chart 1. HOST interface timing 1.1 System timing Table 1.1-1 Symbol tXIN DutyXIN tSCLK DutySCLK tCAMCKO DutyCAMCKO tCAMCKI DutyCAMCKI tRESETB Clock duty System clock cycle System clock duty Camera clock output cycle Camera clock output duty Camera clock input cycle Camera clock input duty RESETB "L" pulse width Details Clock input cycle Technical Note BU6566GVW timing conditions (system) MIN. 33.0 45.0 33.0 33.3 33.0 33.3 66.0 40.0 1.0 TYP. 50.0 50.0 50.0 50.0 MAX. 55.0 66.7 66.7 60.0 Unit ns % ns % ns % ns % us "H" width / cycle “"H" width / cycle "H" width / cycle "H" width / cycle Conditions ＊Regulation all at threshold of VDDIO×1/2 Table 1.1-2 Symbol tXIN DutyXIN tSCLK DutySCLK tCAMCKO DutyCAMCKO tCAMCKI DutyCAMCKI tRESETB Clock duty System clock cycle System clock duty Details Clock input cycle BU6568GV timing conditions (system) MIN. 33.0 45.0 19.2 33.3 19.2 45.0 19.2 45.0 1.0 TYP. 50.0 50.0 50.0 50.0 MAX. 55.0 66.7 55.0 55.0 Unit ns % ns % ns % ns % us "H" width / cycle "H" width / cycle "H" width / cycle "H" width / cycle Conditions Camera clock output cycle Camera clock output duty Camera clock input cycle Camera clock input duty RESETB "L" pulse width ＊Regulation all at threshold of VDDIO×1/2 1.2 Register (including RAM via register) write timing. tWC tAS tAH Address Input tCS tCH A2,A1 CSB（WRB） WRB（CSB） RDB tWW tWAIT tDS tDH Data D[15:0] Write Table 1.2-1 Symbol tWC tAS tAH tCS tCH tWW tWAIT tDS tDH Write cycle time BU6566GVW timing conditions（RAM, register write cycle） Details MIN. 70 -5 -1 0 0 40 30 35 -1 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns Address setup time before WRB(CSB) falling Address hold time after WRB(CSB) rising CSB(WRB) input setup time before WRB(CSB) falling CSB(WRB) input hold time after WRB(CSB) rising WRB(CSB) active time width Wait time from WRB(CSB) rising to the next WRB(CSB) or to RDB falling Data setup time before WRB(CSB) rising Data hold time after WRB(CSB) rising ＊Regulation all at threshold of VDDIO1×1/2 (VDD=1.50V,VDDIO=2.85V,GND=0.0V,Ta=25ºC) ＊It is possible to use it with either CSB or WRB active. However, either of them must do LOW pulse operation. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 9/16 2009.04 - Rev.B BU6566GVW, BU6568GV Table 1.2-2 Symbol tWC tAS tAH tCS tCH tWW tWAIT tDS tDH Write cycle time Address setup time before WRB(CSB) falling Address hold time after WRB(CSB) rising CSB(WRB) input setup time before WRB(CSB) falling CSB(WRB) input hold time after WRB(CSB) rising WRB(CSB) active time width Wait time from WRB(CSB) rising to the next WRB(CSB) or to RDB falling Data setup time before WRB(CSB) rising Data hold time after WRB(CSB) rising Technical Note BU6568GV timing conditions（RAM, register write cycle） Details MIN. 55 -4 0 0 0 40 15 30 0 TYP. MAX Unit ns ns ns ns ns ns ns ns ns ＊Regulation all at threshold of VDDIO1×1/2 (VDD=1.50V,VDDIO=2.85V,GND=0.0V,Ta=25ºC) ＊It is possible to use it with either CSB or WRB active. However, either of them must do LOW pulse operation. 1.3 Register (including RAM via register) read timing. tRC A2,A1 CSB（RDB） tAS Address Input tCS tRD tAH WRB RDB（CSB） tCH tWAIT D[15:0] tROE Read Data tROD Table 1.3-1 Symbol tRC tAS tAH tCS tCH tRD tWAIT tROE,tROD Read cycle time BU6566GVW timing conditions (RAM, register read cycle) Details MIN. 100 -5 -1 0 0 30 TYP. MAX. 70 15 Unit ns ns ns ns ns ns ns ns Address setup time before RDB(CSB) falling Address hold time after RDB(CSB) rising CSB(RDB) input setup time before RDB(CSB) falling CSB(RDB) input hold time after RDB(CSB) rising Access time after RDB(CSB) falling Wait time from RDB(CSB) rising to the next RDB(CSB) falling or to WRB falling Data output enable time after RDB(CSB) falling, Data output disable time after RDB(CSB) rising ＊Regulation all at threshold of VDDIO1×1/2 (VDD=1.50V,VDDIO=2.85V,GND=0.0V,Ta=25ºC) ＊It is possible to use it with either CSB or RDB active. However, either of them must do LOW pulse operation. Table 1.3-2 Symbol tRC tAS tAH tCS tCH tRD tWAIT tROE,tROD Read cycle time BU6568GV timing conditions (RAM, register read cycle) Details MIN. 74.5 -4 0 0 0 30 8 TYP. MAX. 70 Unit ns ns ns ns ns ns ns ns Address setup time before RDB(CSB) falling Address hold time after RDB(CSB) rising CSB(RDB) input setup time before RDB(CSB) falling CSB(RDB) input hold time after RDB(CSB) rising Access time after RDB(CSB) falling Wait time from RDB(CSB) rising to the next RDB(CSB) falling or to WRB falling Data output enable time after RDB(CSB) falling, Data output disable time after RDB(CSB) rising ＊Regulation all at threshold of VDDIO1×1/2 (VDD=1.50V,VDDIO=2.85V,GND=0.0V,Ta=25ºC) ＊It is possible to use it with either CSB or RDB active. However, either of them must do LOW pulse operation. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 10/16 2009.04 - Rev.B BU6566GVW, BU6568GV 2. Camera Module Interface Timing 2.1. System clock and camera clock Technical Note External input clock (XIN) may be divided set and supplied as CAMCKO clock to camera module. The relation of data synchronization clock CAMCKI clock from camera and system clock SCLK must be set so as to meet the following formula. fSCLK  2 × fCAMCKI ……(2.1-1) fSCLK System clock frequency fCAMCKI Camera clock frequency input to CAMCKI terminal Moreover, [Camera timing 1] or [Camera timing 2] shown below must be satisfied. [Camera timing１] (In the case when CAMCKI signal is as asynchronous as CAMCKO) tCAMCKIH > tSCLK + 1ns and tCAMCKIL > tSCLK + 1ns ……(2.1-2) tCAMCKIH CAMCKI High interval tCAMCKIL CAMCKI Low interval [Camera timing 2] (In the case when CAMCKI signal is as synchronous as CAMCKO) total delay + margin ( 10ns) < tSCLK ……(2.1-3) total delay delay from CAMCKO change point to CAMCKI change point The clock relation in fSCLK = fCAMCKO = 2 × fCAMCKI is shown in Figure.2.1-1. [fSCLK=fCAMCKO=2 × fCAMCKI] internal SCLK CAMCKO CAMCKI detect total delay detect CAMCKI = "H" CAMCKO BU6566GVW /BU6568GV CAMCKI total delay CAMERA Module CAMCKI = "L" Figure .2.1-1 Relation between system clock and camera clock 2.2. Camera module interface timing The timing of the camera image signal in camera I/F is shown in Table 2.2-1. CAMVS CAMHS CAMD0 －CAMD7 CAMCKI (CKPL=“0”) CAMCKI (CKPOL=“1”) tCMS tCMH Table Symbol tCMS tCMH 2.2-1 BU6566GVW/BU6568GV timing (camera data) MIN. TYP. MAX. Details Unit ns ns Remarks BU6566GVW/BU6568GV BU6566GVW/BU6568GV CAMCKI rising/falling camera set up time CAMCKI rising/falling camera hold time 1/5 1/5 - - www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 11/16 2009.04 - Rev.B BU6566GVW, BU6568GV 3. LCD direct access Technical Note When to set up with A2="L", direct access to LCD module is set up, and HOST CPU signal penetrated to LCD signal. CSB LCDCSB tCSf1 tCSr1 WRB LCDWRB tWRf1 tWRr1 tRDr1 tRDf1 tAD1 tAD2 tDTr1 tDTw1 RDB LCDRDB A1 LCDA0 D0～D15 LCDD0～LCDD15 Table 3-1 Symbol tCSf1 tCSr1 tWRf1 tWRr1 tRDf1 tRDr1 tAD1 tDTw1 tDTr1 BU6566GVW timing conditions（LCD direct access） Details MIN. TYP. MAX. Unit Delay from CSB to LCDCSB falling Delay from CSB to LCDCSB rising Delay from WRB to LCDWRB falling Delay from WRB to LCDWRB rising Delay from RDB to LCDRDB falling Delay from RDB to LCDRDB rising Delay from A1 to LCDA0 Delay from D0～D15 to LCDD0～LCDD15 Delay from LCDD0～LCDD15 to D0～D15 3.5 2.1 3.0 2.0 3.0 2.0 1.8 7.4 3.0 - 12.0 9.3 11.2 9.2 11.8 9.1 9.6 22.3 13.35 ns ns ns ns ns ns ns ns ns Table 3-2 Symbol tCSf1 tCSr1 tWRf1 tWRr1 tRDf1 tRDr1 tAD1 tAD2 tDTw1 tDTr1 BU6568GV timing conditions（LCD direct access） Details MIN. TYP. MAX. Unit Delay from CSB to LCDCSB falling Delay from CSB to LCDCSB rising Delay from WRB to LCDWRB falling Delay from WRB to LCDWRB rising Delay from RDB to LCDRDB falling Delay from RDB to LCDRDB rising Delay from A1 to LCDA0 Delay from A1 to LCDA0 Delay from D0～D15 to LCDD0～LCDD15 Delay from LCDD0～LCDD15 to D0～D15 3.0 2.5 3.0 2.5 3.0 2.5 2.5 6.0 4.0 4.0 - 12.0 10.0 12.0 10.0 12.0 10.0 10.0 24.0 16.0 16.0 ns ns ns ns ns ns ns ns ns ns www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 12/16 2009.04 - Rev.B BU6566GVW, BU6568GV 4. LCD transfer timing Transfer timing to LCD is shown below. RESO Nwrb Npix Tseq Th_rest 0 2 1 (WL+WH+2)×2 0 1 2 1 (WL+WH+2)×2 0 2 3 2 (WL+WH+max(WL,WH)+3)×2 abs(WL-WH) 3 1 1 (WL+WH+2) 0 4 2 1 (WL+WH+2)×2 0 5 3 1 (WL+WH+2)×3 0 6 3 1 (WL+WH+2)×3 0 7 2 1 (WL+WH+2)×2 0 ＊RESO(IDX:42h bit [2:0]) shows a color resolution setting of LCD. ＊Nwrb, Npix, Tseq, and Th_rest are the parameters determined by RESO. ＊WL, WH are the value of LCDWL, LCDWH of Register MLCDWAV (IDX:49h), respectively. ＊max (WL, WH) shows the maximum of WL and WH. ＊abs(WL-WH) shows the absolute value of (WL-WH). Technical Note TRN_CMD=1 Waveform at command transfer (TSCLK for all unit) EXCMD=0 LCDCSB EXCMD=1～7 LCDCSB 2 LCDWRB 4 Command WH+2 WL+1 WH+3 LCDA0 LCDD0-15 1 1 2 2 WH+3 WH+2 1 TRN_CMD=0 Waveform at data transfer (TSCLK for all unit) Nwrb=1 Tseq LCDWRB WL+1 WH+1+Th_rest LCDWRB WL+1 Tseq WH+1 LCDWRB WL+1 WL+1 WL+1 WH+1 WH+1+Th_rest WL+1 Nwrb=2 Tseq WH+1 WH+1+Th_rest Nwrb=3 EXCMD=0 LCDCSB (Tseq/Npix)+5 LCDWRB LCDA0 1 (Tseq/Npix)+5 LCDD0-15 1 (Tseq/Npix)+5 WL+1 Data WH+1 WH+2+Th_rest WH+2+Th_rest WH+1+Th_rest 1 Data EXCMD=1-7 Command LCDCSB LCDWRB LCDA0 1 LCDD0-15 1 2 (Tseq/Npix)+WH+5 2 2 WH+1 WH+2 (Tseq/Npix)+WH+5 1 (Tseq/Npix)+WH+4 WL+1 WH+2+Th_rest WH+1+Th_rest 1 WH+1 WH+2+Th_rest （Note1）In LCD_DELAY[1:0]( IDX:49h bit [9:8]) ="00", LCDA0 and LCDD change in LCDWRB falling, and are held to the next LCDWRB falling. （Note2）Change of LCDWRB is late for LCDA0 and LCDD 15-0 according to a setup of LCD_DELAY [1:0] (at the time of output no-load). Typ. delays 10ns in LCD_DELAY[1:0] ="01." 1tSCLK in LCD_DELAY[1:0] ="10”. 1tSCLK＋Typ.10ns in LCD_DELAY[1:0] ="11”. Figure 4-1 MAIN LCD data transfer waveform（Unit：tSCLK） www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 13/16 2009.04 - Rev.B BU6566GVW, BU6568GV Technical Note ● Development Scheme This technical note is aimed at trying the connectivity in the hardware between customer’s system and our camera image processor series. We prepare various data and tools for every development STEP as follows other than this technical note, please contact the sales staff in your duty also including the support system. （1） Demonstration STEP (You can try the standard image processing functions by the standard Demonstration kit at once.) You can confirm the standard functions such as camera image preview, memory data display to LCD, camera image composition JPEG compression/ expansion, frame composition, divided display, and LED lighting, and so forth on the Demonstration board. ・Standard Demonstration board kit ◎Demonstration board （LCD module provided by ROHM, Camera module provided by ROHM, Check board equipped with the camera image processor, ARM-equipped controller board） ◎Demonstration board operation manual ◎Demonstration software If the software for the trial board is installed in your Windows PC(Windows 2000/XP/ME/98), more detailed setting is possible. (Execution tools for the macro command, sample macro command file) ◎USB cable （2） Confirmation STEP (We will respond to customer’s camera module, LCD module, HOST CPU.) ・Specifications We will provide specifications for camera image processor according to customer’s requirements. ・Function explanation We will deliver you the function explanation describing detailed functions, register settings, external interfaces, timing, and so forth of camera image processor according to your requests. ・Application note We will deliver you the detailed explanation data on application development of camera image processor according to your requests. （3） System check STEP (You can check the application operation as a system by the kit of system check tools and your module(camera/LCD).) ROHM creates the system check board using your camera/LCD module. You can check the interface with your module and the application operation on the system check board using the tools for user’s only. ・System check tools kit ・System check software (For Windows PC) ◎Reference C source code summarizing ARM –compatible application program interface(API) ◎The application software (API) as a reference C source code ◎The execution tools for the macro command (BU65XX_USB) for the check by your PC. ◎The macro command file for the check by your PC. ・System check document ◎System check board manual ◎BU65XX Demo_Board Application using API ◎Board circuit diagram *You can check the detailed functions of the application operation by your PC using the macro command file. （4） Integrated check STEP with user’s system (You can check the application operation as a system on your system check board using the integrated check software.) You can check the application operation on the sample LSI-equipped system check board by your camera / LCD module using the integrated check software. ・On line Support；We will answer your questions about the software development. How to use the macro command file, API file, and APL file. Setting flow of the camera function (camera JPEG, preview, etc.) Interface setting of the camera module, LCD module and the camera image processor. Header analysis method oh JPEG decode, etc. ・On site Support；We will help you clarify the questions about the software development on site together on spot. Check of the operation of each function and the basic operation at each register setting, etc. based on the specification. Explanation about the specific usage of the macro command file, API file and APL file and relative questions. How to develop the overlay or special functions, etc. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 14/16 2009.04 - Rev.B BU6566GVW, BU6568GV ●Cautions on use (1)Absolute Maximum Ratings Technical Note An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down devices, thus making impossible to identify breaking mode such as a short circuit or an open circuit. If any special mode exceeding the absolute maximum ratings is assumed, consideration should be given to take physical safety measures including the use of fuses, etc. (2)Operating conditions These conditions represent a range within which characteristics can be provided approximately as expected. The electrical characteristics are guaranteed under the conditions of each parameter. (3)Reverse connection of power supply connector The reverse connection of power supply connector can break down ICs. Take protective measures against the breakdown due to the reverse connection, such as mounting an external diode between the power supply and the IC’s power supply terminal. (4)Power supply line Design PCB pattern to provide low impedance for the wiring between the power supply and the GND lines. In this regard, for the digital block power supply and the analog block power supply, even though these power supplies has the same level of potential, separate the power supply pattern for the digital block from that for the analog block, thus suppressing the diffraction of digital noises to the analog block power supply resulting from impedance common to the wiring patterns. For the GND line, give consideration to design the patterns in a similar manner. Furthermore, for all power supply terminals to ICs, mount a capacitor between the power supply and the GND terminal. At the same time, in order to use an electrolytic capacitor, thoroughly check to be sure the characteristics of the capacitor to be used present no problem including the occurrence of capacity dropout at a low temperature, thus determining the constant. (5)GND voltage Make setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state. Furthermore, check to be sure no terminals are at a potential lower than the GND voltage including an actual electric transient. (6)Short circuit between terminals and erroneous mounting In order to mount ICs on a set PCB, pay thorough attention to the direction and offset of the ICs. Erroneous mounting can break down the ICs. Furthermore, if a short circuit occurs due to foreign matters entering between terminals or between the terminal and the power supply or the GND terminal, the ICs can break down. (7)Operation in strong electromagnetic field Be noted that using ICs in the strong electromagnetic field can malfunction them. (8)Inspection with set PCB On the inspection with the set PCB, if a capacitor is connected to a low-impedance IC terminal, the IC can suffer stress. Therefore, be sure to discharge from the set PCB by each process. Furthermore, in order to mount or dismount the set PCB to/from the jig for the inspection process, be sure to turn OFF the power supply and then mount the set PCB to the jig. After the completion of the inspection, be sure to turn OFF the power supply and then dismount it from the jig. In addition, for protection against static electricity, establish a ground for the assembly process and pay thorough attention to the transportation and the storage of the set PCB. (9)Input terminals In terms of the construction of IC, parasitic elements are inevitably formed in relation to potential. The operation of the parasitic element can cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the input terminal. Therefore, pay thorough attention not to handle the input terminals, such as to apply to the input terminals a voltage lower than the GND respectively, so that any parasitic element will operate. Furthermore, do not apply a voltage to the input terminals when no power supply voltage is applied to the IC. In addition, even if the power supply voltage is applied, apply to the input terminals a voltage lower than the power supply voltage or within the guaranteed value of electrical characteristics. (10)Ground wiring pattern If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well. (11)External capacitor In order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a degradation in the nominal capacitance due to DC bias and changes in the capacitance due to temperature, etc. ●Order Model Name Selection B U 6 5 6 8 GV Package type GVW:SBGA099W070 GV:SBGA099T070 E 2 Taping model name E2: Embossed reel tape ROHM model name Product number www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 15/16 2009.04 - Rev.B BU6566GVW, BU6568GV ● Tape and Reel information Technical Note SBGA099W070 1PIN MARK 7.0± 0.1 7.0 ± 0.1 Tape Quantity 0.08 0.9MAX Embossed carrier tape (with dry pack) 1500pcs E2 The direction is the 1pin of product is at the upper left when you hold S Direction of feed ( reel on the left hand and you pull out the tape on the right hand ) 0.1 S 99- φ 0.33± 0.05 φ 0.08 M S AB P=0.65× 9 0.65 A 0.575± 0.1 K J H G F E D C B A B 0.65 1 2 3 4 5 6 7 8 910 0.575± 0.1 P=0.65× 9 1pin Direction of feed (Unit : mm) Reel ∗ Order quantity needs to be multiple of the minimum quantity. SBGA099T070 1PIN MARK 7.0± 0.1 7.0 ± 0.1 Tape Quantity 0.23 1.2MAX Embossed carrier tape (with dry pack) 1500pcs E2 The direction is the 1pin of product is at the upper left when you hold S Direction of feed ( reel on the left hand and you pull out the tape on the right hand ) 0.1 S 99- φ 0.33± 0.05 φ 0.08 M S AB P=0.65× 9 0.65 A 0.575± 0.1 K J H G F E D C B A B 0.65 1 2 3 4 5 6 7 8 910 0.575± 0.1 P=0.65× 9 1pin Direction of feed (Unit : mm) Reel ∗ Order quantity needs to be multiple of the minimum quantity. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 16/16 2009.04 - Rev.B Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law. Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact us. ROHM Customer Support System http://www.rohm.com/contact/ www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. R0039A