BU7843AGU_10

1/4 Structure Product Name Silicon Monolithic Integrated Circuit Audio Interface for Cellular Phone Product No. BU7843AGU Audio Interface 6x6 keyscan circuit Features o ○Absolute Maximum Ratings(Ta=25 C） Parameter Analog supply voltage Digital supply voltage Power supply voltage Analog input voltage Digital input voltage Input current Allowable dissipation Operating temperature range Storage temperature range o Symbol AVDD DVDD PVDD VAIN VDIN IIN Pd TOPR TSTG o Rating -0.3～4.5 -0.3～4.5 -0.3～4.5 AVSS-0.3～AVDD+0.3 DVSS-0.3～DVDD+0.3 -10～+10 310(*1) -30～+85 -55～+125 Unit V V V V V mA mW o o Remarks C C (*1) When Ta is above 25 C, reduce 3.1mW per 1 C. o ○Recommended operating conditions（Ta=25 C） Parameter Analog operation voltage Digital operation voltage Power operation voltage Symbol AVDD DVDD PVDD Min. 2.7 1.65 2.7 Rating Typ. 2.8 1.8 2.8 Max. 3.1 3.1 3.1 Unit V V V (*2) Remarks (*2) AVDD and PVDD are internally connected in the IC and use the same potential. This chip is not designed to protect itself against radioactive rays. REV. B 2/4 ○Electrical Characteristics (Unless otherwise noted, Ta = 25oC AVSS=DVSS=PVSS=0.0V Parameter Digital DC characteristics Digital high level input voltage 1 Digital high level input voltage 2 Digital low level input voltage 1 Digital low level input voltage 2 Digital high level input current Digital low level input current Digital high level output voltage Digital low level output voltage Digital AC characteristics SCL clock frequency Bus free time (Iterative) start condition setup time (Iterative) start condition hold time SCL low time SCL high time Data setup time Data hold time Stop condition setup time VIH1 VIH2 VIL1 VIL2 IIH IIL VOH VOL fSCL tBUF tSU;STA tHD;STA tLOW tHIGH tSU;DAT tHD;DAT tSU;STO 0.8 DVDD DVDD -0.4 DVDD -0.5 0.5 V IOL=1mA ATT is set at 0) Max. 0.2 DVDD 0.4 1 1 Unit V V V V μA μA V Condition Symbol Min. Rating Typ. - DVDD=3.0V DVDD=1.8V DVDD=3.0V DVDD=1.8V VIH=DVDD VIL=DVSS IOH=-1mA 1.3 0.6 0.6 1.3 0.6 100 0 0.6 - 400 - kHz μs μs μs μs μs ns ns μs After a reset MIC1_IN→MIX6→TX_OUT RX_IN→MIX2→HF_OUT RX_IN→MIX2→BT_OUT RX_IN→MIX2→RCVP_OUT､ RCVN_OUT DACL_IN→MIX2→HPL_OUT DACR_IN→MIX3→HPR_OUT DACL_IN→MIX4→SPL_OUT DACR_IN→MIX5→SPR_OUT All paths are ON BIAS_ON＝！ Current consumption AVDD=DVDD=PVDD=2.8V Standby current IST TX_OUT path current HF_OUT path current BT_OUT path current Reciever path current Headphone path current Speaker path current Full operation current Microphone bias current IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 IDD9 IDD8 - input signal = no signal. 3 μA 1.3 1.4 1.3 2.5 3.5 1.9 8.5 250 2.2 2.4 2.2 4.2 5.9 3.2 13.5 430 mA mA mA mA mA mA mA μA REV. B 3/4 ○External measure and View ○Pin layout diagram Pin NO. Pin name N.C. MIC1_IN MIC2_IN MIC3_IN AUX1_IN DACR_IN AUX2_IN DACL_IN RX_IN SDA SDL KBR0 KBR1 N.C. N.C. N.C. N.C. KBR2 KBR3 KBR4 KBR5 Pin NO. F4 H4 G5 F5 H5 E5 H6 G6 H7 G7 H8 G8 F6 F7 F8 E6 E8 D7 D6 D8 D5 Pin name KB0 DVDD DVSS KB1 KB2 KB3 KB4 KB5 N.C. N.C. N.C. N.C. IRQ RSTB HPR_OUT HPL_OUT CHPL PVSS PVDD RCVN_OUT CSTEP Pin NO. C8 C7 B8 B7 A8 A7 C6 B6 B5 A6 C5 A5 B4 C4 A4 D4 A3 B3 A2 B3 Pin name RCVP_OUT CPOP N.C. N.C. N.C. N.C. SPL_OUT SPR_OUT HF_OUT BT_OUT TX_OUT COMOUT COMIN AVDD AVSS CBIAS MIC1_OUT MICB N.C. N.C. BU78 43AGU A1 C3 C2 D2 C1 LOT No D3 D1 E2 E3 E1 E4 F1 VBGA063T050 （Unit: mm） F2 G1 G2 H1 H2 F3 G3 G4 ○Block diagram MIC1_OUT COMOUT COMIN CBIAS AVDD AVSS MICB N.C. N.C. H3 SPR_OUT SPL_OUT HF_OUT TX_OUT BT_OUT N.C. 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 D4 C4 C5 C6 B2 A2 B3 A3 A4 B4 A5 A6 B5 B6 A7 49 1 600OSingle A8 N.C. N.C. A1 MIC_BIAS AVDD / AVSS VREF B7 48 N.C. + MIX6 B8 ANTI-POP MUTE 47 N.C. 3 MIC1_IN C3 + SW C7 46 -26~ +12dB/2dB -26~ +4dB/2dB -26~ +4dB/2dB -26~ +4dB/2dB -26~ +12dB/2dB CPOP MIC AMP 4 TX_V SPR_V MIC2_IN MIC_V -20~ +30dB/2dB BT_V C2 SPL_V HF_V SW C8 45 RCVP_OUT 5 MIC3_IN D2 SW 32OBTL CSTEP D5 44 6 AUX1_IN C1 AUX1_V -11~ +3dB/1dB D8 RCVN_OUT + 43 MIX1 7 DACR_IN -11~ +3dB/1dB 8 AVDD / AVSS D3 DACR_V D6 42 PVDD AUX2_IN D1 AUX2_V -11~ +3dB/1dB + MIX2 D7 41 PVSS 9 CHPL DACL_V -11~ +3dB/1dB RCV_V -26~ +4dB/2dB DACL_IN E2 E8 40 10 RX_IN E3 RX_V -11~ +3dB/1dB + MIX3 HPL_V -26~ +4dB/2dB 16OSingle E6 39 HPL_OUT 11 SDA I2C BUS I/F E1 HPR_V + MIX5 -26~ +4dB/2dB 16OSingle F8 38 HPR_OUT 12 SCL E4 DVDD 13 30k DVDD 14 30k AVDD/PVDD is connected at internal, and they are connected analog portion. E7 37 CHPR KBR0 F1 + MIX4 F7 36 RSTB KEYSCAN KEYSCAN KBR1 F2 6 6 F6 35 IRQ 15 N.C. G1 6 16 DVDD 30k DVDD 30k DVDD 30k DVDD 30k DVDD / DVSS G8 34 N.C. N.C. H8 N.C. G2 BU7843AGU G3 G4 G5 G6 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 KB0 KB1 KB2 KB3 KB4 KBR2 KBR3 KBR4 KBR5 DVDD N.C. N.C. KB5 N.C. REV. B DVSS N.C. G7 H1 H2 H3 H4 H5 H6 H7 E5 F3 F4 F5 4/4 ○Cautions on use (1) Absolute Maximum Ratings An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down devices, thus making impossible to identify breaking mode such as a short circuit or an open circuit. If any special mode exceeding the absolute maximum ratings is assumed, consideration should be given to take physical safety measures including the use of fuses, etc. (2) Operating conditions These conditions represent a range within which characteristics can be provided approximately as expected. The electrical characteristics are guaranteed under the conditions of each parameter. (3) Reverse connection of power supply connector The reverse connection of power supply connector can break down ICs. Take protective measures against the breakdown due to the reverse connection, such as mounting an external diode between the power supply and the IC’s power supply terminal. (4) Power supply line Design PCB pattern to provide low impedance for the wiring between the power supply and the GND lines.In this regard, for the digital block power supply and the analog block power supply, even though these power supplies has the same level of potential, separate the power supply pattern for the digital block from that for the analog block, thus suppressing the diffraction of digital noises to the analog block power supply resulting from impedance common to the wiring patterns. For the GND line, give consideration to design the patterns in a similar manner. Furthermore, for all power supply terminals to ICs, mount a capacitor between the power supply and the GND terminal. At the same time, in order to use an electrolytic capacitor, thoroughly check to be sure the characteristics of the capacitor to be used present no problem including the occurrence of capacity dropout at a low temperature, thus determining the constant. (5) GND voltage Make setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state. Furthermore, check to be sure no terminals are at a potential lower than the GND voltage including an actual electric transient. (6) Short circuit between terminals and erroneous mounting In order to mount ICs on a set PCB, pay thorough attention to the direction and offset of the ICs. Erroneous mounting can break down the ICs. Furthermore, if a short circuit occurs due to foreign matters entering between terminals or between the terminal and the power supply or the GND terminal, the ICs can break down. (7) Operation in strong electromagnetic field Be noted that using ICs in the strong electromagnetic field can malfunction them. (8) Inspection with set PCB On the inspection with the set PCB, if a capacitor is connected to a low-impedance IC terminal, the IC can suffer stress. Therefore, be sure to discharge from the set PCB by each process. Furthermore, in order to mount or dismount the set PCB to/from the jig for the inspection process, be sure to turn OFF the power supply and then mount the set PCB to the jig. After the completion of the inspection, be sure to turn OFF the power supply and then dismount it from the jig. In addition, for protection against static electricity, establish a ground for the assembly process and pay thorough attention to the transportation and the storage of the set PCB. (9) Input terminals In terms of the construction of IC, parasitic elements are inevitably formed in relation to potential. The operation of the parasitic element can cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the input terminal. Therefore, pay thorough attention not to handle the input terminals, such as to apply to the input terminals a voltage lower than the GND respectively, so that any parasitic element will operate. Furthermore, do not apply a voltage to the input terminals when no power supply voltage is applied to the IC. In addition, even if the power supply voltage is applied, apply to the input terminals a voltage lower than the power supply voltage or within the guaranteed value of electrical characteristics. (10) Ground wiring pattern If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well. (11) External capacitor In order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a degradation in the nominal capacitance due to DC bias and changes in the capacitance due to temperature, etc. (12) Others In case of use this LSI, please peruse some other detail documents, we called ,Technical note, Functinal description, Application note. REV. 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