BU7964GUW

MSDL (Mobile Shrink Data Link) Transceivers for Mobile Phones Data rate 1350Mbps RGB Interface BU7964GUW No.10058EAT04 ●Description BU7964GUW is a differential serial interface connecting mobile phone LCD modules to the host CPU. Unique technology is utilized for lower power consumption and EMI. MSDL minimizes the number of wires required - an important consideration in hinge phones - resulting in greater reliability and design flexibility. ●Features 1) MSDL3 high-speed differential interface with a maximum transfer rate of 1350 Mbps. 2) Compatible with24-bit RGB video mode for LCD controller-to-LCD interface. 3) Pixel clock frequency range from 4 to 45MHz. 4) Depending on the data transfer rate, either, two or three differential data channels can be selected. ●Applications Serial Interface for LCD Display Interface of Mobile Devices Application. ●Absolute Maximum Ratings Parameter Power Supply Voltage Input Voltage Output Voltage Input Current Output Current Preservation Temperature Symbol DVDD MSVDD VIN VOUT IIN IOUT Tstg Ratings -0.3 ~ +2.5 -0.3 ~ +2.5 -0.3 ~ MSVDD+0.3 -0.3 ~ DVDD+0.3 -0.3 ~ MSVDD+0.3 -0.3 ~ DVDD+0.3 -10 ~ +10 -70 ~ +70 -55 ~ +125 Unit V V V V V V mA mA ℃ Remarks I/O terminals of MSVDD line I/O terminals of DVDD line I/O terminals of MSVDD line I/O terminals of DVDD line - ●Operating Conditions Parameter Supply Voltage for DVDD Supply Voltage for MSVDD Data Transmission Rate Operating Temperature Range Symbol VDVDD VMSVDD DR Topr Ratings Min 1.65 1.65 120 -30 Typ 1.80 1.80 25 Max 1.95 1.95 450 85 Unit V V Mbps/ch ℃ Conditions VDVDD = VMSVDD - www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 1/18 2010.04 - Rev.A BU7964GUW ●Package View Technical Note 1PIN MARK LOT NO. 5.0±0.1 0.9 MAX 5.0±0.1 S 0.10 B P = 0.5×7 0.75±0.1 BU7964 0.08 S A 0.75±0.1 63-φ0.295±0.05 0.05 M S AB H G F E D C B A 1 234 56 7 8 P = 0.5×7 0.5 (UNIT:mm) Fig.1. Package View (VBGA063W50) www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 2/18 2010.04 - Rev.A BU7964GUW ●Block Diagram MSVDD DVDD Technical Note High Speed I/F D0 D0+ Serial to Parallel PD Error Detection I/F Logic CPO D1 D1+ D2 D2+ CLKCLK+ PLL Timing Generator PCLK Control PCLK Link Monitor Reset Generator XSD LS DRVR Reference Control Logic F_XS PLLBW TEST MSGND DGND Fig.2. Block Diagram www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 3/18 2010.04 - Rev.A BU7964GUW ●Pin Layout 1 2 3 4 5 6 7 Technical Note 8 A TEST0 PD19 PD17 PD16 PD14 PD13 PD10 CPO B PCLK PD18 PD15 PD12 PD11 PD9 PD8 C PD22 PD20 PLL_BW0 DVDD N.C. F_XS PD7 PD6 D PD23 PD21 N.C. DGND DGND DVDD PD4 PD5 E PD25 PD24 DVDD DGND MSGND N.C. PD1 PD3 F PD26 LS0 MSVDD MSGND MSVDD N.C. XSD PD2 G LS1 PLL_BW1 D2- D1- CLK- D0- N.C. PD0 H N.C. N.C. D2+ D1+ CLK+ D0+ DRVR TEST1 Fig.3. Pin Layout (Top View) www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 4/18 2010.04 - Rev.A BU7964GUW ●Pin Functions Table 1. Power Supply and Ground Power Supply / Ground: 10-pin Name DVDD MSVDD DGND MSGND Width 3 2 3 2 Logic core, CMOS I/O power supply. Analog core power supply. CMOS I/O and logic core ground. Analog core ground. Table 2. MSDL3 High-Speed Serial Interface: 8-pin Name CLK+ CLKD0+ D0D1+ D1D2+ D2Width 1 1 1 1 1 1 1 1 Level Analog Analog Analog Analog Analog Analog Analog Analog I/O I I I I I I I I CLK+pin. CLK-pin. D0+pin. D0-pin. D1+pin. D1-pin. D2+pin. D2-pin. Table 3. Analog Analog: 1-pin Name DRVR Width 1 Level Analog I/O Functions 10kΩ ± 5% register should be connected between DRVR and MSGND. Table 4. Parallel Data Interface Parallel Data Interface: 29-pin Name PCLK PD[26:0] CPO Width 1 27 1 Level CMOS CMOS CMOS I/O O O O PCLK interface. Parallel data interface. Parity error toggled output, normally ‘L,’ output is toggled during one PCLK period when a parity error is detected Functions Functions Functions Technical Note Shutdown Pull Down Pull Down Pull Down Pull Down Pull Down Pull Down Pull Down Pull Down Equivalent Schematic D D D D D D D D Shutdown - Equivalent Schematic D Shutdown ‘L’ ‘L’ ‘L’ Equivalent Schematic C C C www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 5/18 2010.04 - Rev.A BU7964GUW Table 5. Control Control: 8-pin Name XSD Width 1 Level CMOS I/O I Functions Shutdown pin. ‘L’: shutdown. ‘H’: normal operation. Selection of the number of data channel and the data format. Refer to section 0. * Set the same number of data channel bet wean the TX device and the RX device. Selection of CMOS output rising and falling slope ‘L’: slow ‘H’: fast Technical Note Shutdown Input Equivalent Schematic A LS0 1 CMOS I Input A LS1 1 F_XS 1 CMOS I Input A PLL_BW0 1 CMOS I Selection of PLL bandwidth. Input A PLL_BW1 1 TEST0 1 Pull down I TEST1 1 Test mode pins. ‘L’: normal mode. ‘H’: test mode. Must be open or ‘L.’ B Input B DVDD DVDD DVDD MSVDD A B C D Fig.4. Equivalent Schematics www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 6/18 2010.04 - Rev.A BU7964GUW Technical Note ●Operation Control MSDL3 Channel Count Selection Pins LS0 and LS1 are used to control the high-speed data channel count and data format. High-speed data channel count, data format should be the same between the transmitting and receiving devices (the BU7963GUW and BU7964GUW, respectively). Table 6 shows and Receipt Data rate ranges for the LS pin settings. Table 6. The Range of The Receipt Data rate LS1 ‘L’ ‘L’ ‘H’ LS0 ‘L’ ‘H’ ‘L’ The Number of Data Channel 1-channel (27-bit format). 2-channel (27-bit format). 3-channel (27-bit format). The Range of PCLK Input Frequency [MHz] 4.0-15.0 8.0-30.0 12.0-45.0 The Range of The Data Receipt Rate [Mbits/sec] 120-450 240-900 360-1350 CMOS Output Drivability Selection F_XS determines output drivability of the parallel data interface. Table 7 shows output drivability. Table 7. Output Drivability F_XS ‘L’ ‘H’ 1mA Type 3mA Type Output Drivability PLL Bandwidth Selection BU7964GUW controls the range of the CLK+ / CLK− input frequency (= PCLK output frequency) by the setting of the data format (LS1, and LS0) of the high-speed data channel and the bandwidth setting of PLL_BW0 and PLL_BW1. Table 8. PLL Bandwidth Selection LS1 ‘L’ ‘L’ ‘L’ ‘L’ ‘L’ ‘L’ ‘H’ ‘H’ ‘H’ LS0 ‘L’ ‘L’ ‘L’ ‘H’ ‘H’ ‘H’ ‘L’ ‘L’ ‘L’ PLL_BW1 ‘L’ ‘L’ ‘H’ ‘L’ ‘L’ ‘H’ ‘L’ ‘L’ ‘H’ PLL_BW0 ‘L’ ‘H’ ‘L’ ‘L’ ‘H’ ‘L’ ‘L’ ‘H’ ‘L’ CLK+/CLK- Frequency Range [MHz] (PCLK Input Frequency) Min 4 6 10 8 12 20 12 18 30 Max 7 11 15 14 22 30 21 33 45 www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 7/18 2010.04 - Rev.A BU7964GUW ●Power Modes BU7964UW has three power modes. 1) Shutdown Mode BU7964GUW goes to Shutdown Mode when XSD = ‘L.’ AII logic circuits are initialized in the Shutdown Mode. All high-speed signaling are pulled down to MSGND. All parallel data interface output ‘L’. Technical Note 2) Standby Mode BU7964GUW goes to a Standby Mode when XSD = ‘H’ and CLK+ / CLK− is Hi-Z. All high-speed signaling inputs sink DC current in order to pull the pins down to MSGND. BU7964GUW is monitoring VCM of CLK+ / CLK−. When TX device starts driving high-speed signaling outputs, BU7964GUW detects its VCM and switches to Active Mode. In Standby Mode, All parallel data interface output ‘L’. 3) Active Mode BU7964UW goes to Active Mode when XSD = ‘H’ and VCM is running. Table 9. Power Modes Input Power Mode XSD ‘L’ Vcm of CLK+/CLKMSGND Functions Initialized Operation MSDL3 Terminals Disabled(Pull-down) MSDL3 Vcm detection (Pull-down) MSDL3 VCM monitor. Enabled. Parallel output Initial value Shutdown Standby ‘H’ MSGND Clock input is active MSDL3 Vcm detection MSDL3 VCM monitor. Normal operation. (S2P conv) Initial value Active ‘H’ Normal operation 4) Power Modes Transition Fig.5.shows the Transition of power modes. XSD = ”L” Shutdown XSD = ”H” Standby PCLK input disabled (Hi-z) PCLK input detected Active Fig.5. Power Modes Transition www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 8/18 2010.04 - Rev.A BU7964GUW Technical Note ●Link Error Detection Detection of Parity Error BU7964GUW counts the number of ‘H’ bits in PD[26:0] and CP in every pixel information received and detects parity error as follows: ・There is no parity error occurred if the number of ‘H’ bits in PD[26:0] and CP is odd. ・There is parity error occurred if the number of ‘H’ bits in PD[26:0] and CP is even. If parity error is detected, BU7964GUW outputs the previous error-free pixel information and discards the invalid pixel information. At the same time, BU7964GUW toggles CPO during one PCLK period. BU7964GUW outputs initial value, if the parity error is detected when there is no previous pixel information. Otherwise, BU7964GUW outputs the received pixel information from the high-speed data channel(s) and CPO keeps ‘L.’ Error correction is not supported in BU7964GUW. ●High-Speed Data Channel Protocols Fig.6 Fig.7 and Fig.8 show high-speed data channel protocols. D0channel CLK channel CP PD26 PD25 PD24 PD23 PD22 PD21 PD20 PD19 PD18 PD17 PD16 PD15 PD14 PD13 PD12 Frame start / end PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 res res CP PD26 PD25 PD11 Fig.6. MSDL3 Protocol for 1-channel Data (27-bit) D0channel CP D1channel res CLK channel Frame start / end PD26 PD14 PD25 PD24 PD23 PD22 PD21 PD20 PD9 PD8 PD19 PD18 PD17 PD7 PD6 PD5 PD16 PD15 PD4 PD3 PD2 PD1 res PD0 CP res PD26 PD14 PD13 PD12 PD11 PD10 Fig.7. MSDL3 Protocol for 2-channel Data (27-bit) D0channel CP D1channel res D2channel res CLK channel Frame start / end PD26 PD18 PD10 PD25 PD24 PD17 PD16 PD9 PD8 PD23 PD15 PD7 PD22 PD21 PD20 PD14 PD13 PD12 PD6 PD5 PD4 PD19 PD11 PD3 PD2 PD1 PD0 CP res res PD26 PD18 PD10 Fig.8. MSDL3 Protocol for 3-channel Data (27-bit) “res” is reserved bit for the future use, the default state of those is ‘0.’ CP is the parity bit of data payload. BU7964GUW adds an odd parity on CP of the high-speed channel data. ・When the number of ‘H’ bits in parallel data is even, CP bit is ‘H.’ ・When the number of ‘H’ bits in parallel data is odd, CP bit is ‘L.’ www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 9/18 2010.04 - Rev.A BU7964GUW ●Electrical Characteristics 1) DC Characteristics Table 10. Digital Input / Output DC Characteristics Ta=25°C, DVDD=MSVDD=1.80V and DGND=MSGND=0.00V, unless otherwise noted. Technical Note Parameter ‘L’ Input Voltage 1 ‘H’ Input Voltage 1 Output ‘L’ Voltage1 Output ‘H’ Voltage1 Output ‘L’ Voltage2 Output ‘H’ Voltage2 Output ‘L’ Voltage3 Output ‘H’ Voltage3 Symbol VIL1 VIH1 VOL1 VOH1 VOL2 VOH2 VOL3 VOH3 Limits Min DGND 0.7 x DVDD DGND 0.7 x DVDD DGND 0.7 x DVDD DGND 0.85 x DVDD Typ Max 0.3 x DVDD DVDD 0.3 x DVDD DVDD 0.3 x DVDD DVDD 0.15 x DVDD DVDD Unit V V V V V V V V Conditions XSD, F_XS PLL_BW[1:0], LS[1:0]Pin XSD, F_XS PLL_BW[1:0], LS[1:0]Pin F_XS=‘L’, IO = 1mA, PCLK, CPO, PD[26:0]Pin F_XS=‘L’, IO = -1mA, PCLK, CPO, PD[26:0]Pin F_XS=‘H’, IO = 3mA, PCLK, CPO, PD[26:0]Pin F_XS=‘H’, IO = -3mA, PCLK, CPO, PD[26:0]Pin IO = 100µA, PCLK, CPO, PD[26:0]Pin IO = -100µA, PCLK, CPO, PD[26:0]Pin Table 11. Current Consumption Ta=25°C, DVDD=MSVDD=1.80V and DGND=MSGND=0.00V, unless otherwise noted. Parameter Symbol Limits Min Typ 0.2 Max 10 Unit Conditions XSD = ‘L’, IDVDD + IMSVDD Shutdown Current Iop_sht_rx µA Standby Current Iop_stb_rx - 41.8 90 µA XSD = ‘H’, IDVDD + IMSVDD LS[1:0] = “LL”, PLL_BW[1:0] = “HL”, DVDD = MSVDD, PCLK = 15MHz, XSD = ‘H’, CL = 10pF, Total operating current (IDVDD + IMSVDD) with PD[26:0] outputs toggling 0x2AAAAAA and 0x5555555 LS[1:0] = “LH”, PLL_BW[1:0] = “HL” , DVDD = MSVDD, PCLK = 30MHz, XSD = ‘H’, CL = 10pF, Total operating current (IDVDD + IMSVDD) with PD[26:0] outputs toggling 0x2AAAAAA and 0x5555555 LS[1:0] = “HL”, PLL_BW[1:0] = “HL” , DVDD = MSVDD, PCLK = 45MHz, XSD = ‘H’, CL = 10pF, Total operating current (IDVDD + IMSVDD) with PD[26:0] outputs toggling 0x2AAAAAA and 0x5555555 Active Current 1-channel / 27-bit Format Iop_act_rx1 - 17.6 24.0 mA Active Current 2-channel / 27-bit Format Iop_act_rx2 - 28.0 36.8 mA Active Current 3-channel / 27- bit Format Iop_act_rx3 - 36.0 48.6 mA www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 10/18 2010.04 - Rev.A BU7964GUW 2) AC Characteristics Parallel Data Output Timing tR tR _D _R, _ F Technical Note tR D _ tR 0 .7×DVDD P [2 : 0] 0.5 ×DVDD 0 .3×DVDD PCL 0 .5 ×DVDD tR tR _PCLK DUTY _ Fig.9. Parallel Data Output Timing Table 12. Parallel Data Output AC Timing Ta=25°C, DVDD=MSVDD=1.80V and DGND=MSGND=0.00V, unless otherwise noted. Parameter PCLK Output Duty Cycle Output Data Setup Time Output Data Hold Time Output Data Rise Time/Fall time Symbol tRX_DUTY tRX_DS tRX_DH tRX_R tRX_F Limits Min 45 0.41X Typ 50 9 3 Max 55 - Unit % ns ns ns ns Conditions CL=10pF CL=10pF CL=10pF F_XS=0, CL=10pF F_XS=1, CL=10pF tRx_PCLK 0.41X tRx_PCLK - www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 11/18 2010.04 - Rev.A BU7964GUW 3) Power-On / Off Sequence Power-On Sequence Fig.10 shows power-on sequence of BU7964GUW. Technical Note DVDD ,MSVDD of Tx XSD of Tx PCLK of Tx tTX_VDD_XSD t TX_IN_VAL Stopped Provided tTX_OUT_VAL Tx MSDL 3 Output HiZ Valid DVDD ,MSVDD of Rx XSD of Rx Rx Power mode tRX_VDD_XSD t RX_IN_VAL Shutdown Standby / Active t RX_OUT_VAL Rx All Outputs Initial Value Valid Outputs Tx : BU 7963 GUW Rx: BU 7964 GUW Fig.10. Power-On Sequence Table 13. Power-On Sequence Timing Ta=25°C, DVDD=MSVDD=1.80V and DGND=MSGND=0.00V, unless otherwise noted. Parameter Reset Valid After Power Supplied PCLK Valid After XSD Released Parallel Data Valid After TX HighSpeed Signals Valid Symbol tRX_VDD_XSD tRX_IN_VAL tRX_OUT_VAL Limits Min 10 Typ Max 10 2 Unit Conditions µs µs ms www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 12/18 2010.04 - Rev.A BU7964GUW Power-Off Sequence Fig.11 shows the power-off sequence of BU7964GUW. Technical Note PCLK of Tx Provided Stopped t TX_OUT_INV Tx MSDL 3 Output Valid HiZ t RX_OUT_INV Rx All Outputs Valid Outputs Initial Value XSD of Tx DVDD ,MSVDD of Tx XSD of Rx DVDD ,MSVDD of Rx t TX_XSD_VDD t RX_XSD_VDD Tx : BU 7963 GUW Rx: BU 7964 GUW Fig.11. Power-Off Sequence Timing Table 14. Power-Off Sequence Timing Ta=25°C, DVDD=MSVDD=1.80V, DGND=MSGND=0.00V, unless otherwise noted. Parameter Parallel output delay time XSD hold time Symbol tRX_OUT_INV tRX_XSD_VDD Limits Min 10 Typ Max 100 - Unit µs µs Conditions www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 13/18 2010.04 - Rev.A BU7964GUW ●Frequency Change Sequence Fig.12 shows the frequency change sequence of BU7964GUW. Technical Note DVDD , MSVDD of Tx and Rx XSD of Tx PCLK of Tx t TX_XSD_OUT Frequency 1 tTX_IN_XSD Frequency 2 t TX_XSD_CTL PLL _BW[ 1 :0 ] of Tx State 1 t TX_CTL_XSD State 2 XSD of Rx tRX_XSD_CTL PLL _BW[ 1 :0 ] of Rx State 1 t RX_CTL_XSD State 2 Tx : BU 7963 GUW Rx: BU 7964 GUW Fig.12. Frequency Change Sequence Table 15. Frequency Change Sequence Timing Ta=25°C, DVDD=MSVDD=1.80V and DGND=MSGND=0.00V, unless otherwise noted. Parameter Control Signal Hold Time Control Signal Setup Time Symbol tRX_XSD_CTL tRX_CTL_XSD Limits Min 2.0 2.0 Typ Max - Unit µs µs Conditions www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 14/18 2010.04 - Rev.A BU7964GUW ●High-Speed Channel Characteristic Table 16. High-speed channel characteristic Ta=25°C, DVDD=MSVDD=1.80V and DGND=MSGND=0.00V, unless otherwise noted. Technical Note Parameter Differential Voltage Range LOW-level threshold voltage HIGH-level threshold voltage Common Mode Voltage Range Internal termination resistance Operating Frequency RX sink current Link detection threshold voltage Symbol Vdiff_rx Vthl Vthh Vcm_rx R_rx fopr_rx IPULL_RX VLINK_RX Limits Min 70 -40 0.6 75 12 0.2 Typ 100 0.9 100 30 0.3 Max 200 40 1.2 125 225 90 0.4 Unit mVpp mV mV V Ω MHz µA V Conditions fopr_rx Single-end InP(D0+,D1+,D2+) Vcm_rx InN(D0-,D1-,D2-) Vdiff_rx Differential (InP-InN) 0 Differential (InP-InN) 0 Vthh Vthl Fig.13. High-Speed Channel Characteristic Fig.14 shows high-speed channel equivalent schematic. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 15/18 2010.04 - Rev.A BU7964GUW Technical Note MSDL 3 TX MSVDD Transmission line MSDL 3 RX VO + ILEA _ T ILEA _ R MSVDD RT / 2 RR / 2 VI+ VIMSGND VO ILEA _ T Logical output from MSDL 3 RX Logical input to MSDL 3 TX RT / 2 RR / 2 ILEA MSVDD _ R IPUL MSGND MSGND _ R VC _R V LIN Link detection comparator output MSGND Fig.14. High-Speed Channel Equivalent Schematic. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 16/18 2010.04 - Rev.A BU7964GUW ●Application Circuit Example 1.8V 1.8V 0.1μ×2 0.1μ×3 100p×3 100p×2 1.8V 1.8V 0.1μ×3 0.1μ×2 100p×2 100p×3 Technical Note DGND MSGND MSVDD MSGND MPU 1.8V GND 1.8V GND MSVDD DVDD DGND DVDD Video Mode LCD Controller Pixel clock PCLK 27 PD[26:0] CKD DVDD CLK+ CLKD0+ D0D1+ D1D2+ D2- CLK+ CLKD0+ D0D1+ D1D2+ D2- PCLK BU7964GUW （Rx device） 27 PD[26:0] CPO PLLBW1 PLLBW0 LS1 LS0 F_XS TEST[1:0] XSD Pixel clock R[7:0],G[7:0],B[7:0], HS,VS,DE BU7963GUW （Tx device） R[7:0],G[7:0],B[7:0], HS,VS,DE DVDD 10KΩ±5% 10KΩ±5% RVS TEST[1:0] XSD DGND MSGND MSGND DGND Fig.15. Application Circuit www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. Reset PLLBW POL_PCLK LS1 LS0 Reset WVGA LCD panel DRVR DRVR 17/18 2010.04 - Rev.A BU7964GUW ●Ordering Part Number Technical Note B U 7 Part No. 9 6 4 G U W - E 2 Part No. Package GUW: VBGA063W050 Packaging and forming specification E2: Embossed tape and reel VBGA063W050 1PIN MARK 5.0± 0.1 5.0 ± 0.1 Tape Quantity 0.1 0.9MAX Embossed carrier tape (with dry pack) 2500pcs E2 The direction is the 1pin of product is at the upper left when you hold S Direction of feed ( reel on the left hand and you pull out the tape on the right hand ) 0.08 S 63- φ 0.295± 0.05 φ 0.05 M S AB H G F E D C B A P=0.5× 7 0.5 A 0.75± 0.1 B 0.5 12345678 0.75± 0.1 P=0.5× 7 1pin Direction of feed (Unit : mm) Reel ∗ Order quantity needs to be multiple of the minimum quantity. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 18/18 2010.04 - Rev.A Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuelcontroller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law. Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact us. ROHM Customer Support System http://www.rohm.com/contact/ www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. R1010A