BU8254KVT

LVDS Interface ICs 35bit LVDS Transmitter 35:5 Serializer BU8254KVT ●Description LVDS Interface IC of ROHM "Serializer" "Deserializer" operate from 8MHz to 150MHz wide clock range, and number of bits range is from 35 to 70. Data is transmitted seven times (7X) stream and reduce cable number by 3(1/3) or less. The ROHM's LVDS has low swing mode to be able to expect further low EMI. ●Features ■35bits data of parallel LVCMOS level inputs are converted to five channels of LVDS data stream. ■30bits of RGB data and 5bits of timing and control data(HSYNC,VSYNC,DE,CNTL1,CNTL2) are transmitted up to 784Mbps effective rate per LVDS channel. ■Support clock frequency from 8MHz up to 112MHz. ■Support consumer video format including 480i, 480P, 720P and 1080i as well. ■Clock edge selectable ■Power down mode ■Support spread spectrum clock generator. ■Support reduced swing LVDS for low EMI. ■30bit LVDS receiver is recommended to use BU8255KVT. ●Applications Flat Panel Display ●Precaution ■This chip is not designed to protect from radioactivity. ■The chip is made strictly for the specific application or equipment. Then it is necessary that the unit is measured as need. ■This document may be used as strategic technical data which subjects to COCOM regulations. Status of this document The Japanese version of this document is the official specification. Please use the translation version of this document as a reference to expedite understanding of the official version. If there is any uncertainty in translation version of this document, official version takes priority. Jun.2008 ●Block Diagram LVCMOS Input CLKIN (8～112MHz) LVDS Output PLL ＋ － TCLK P/N (8～112MHz) 7 TA6-TA0 Parallel to Serial ＋ － TA P/N 7 TB6-TB0 Parallel to Serial ＋ － TB P/N 7 TC6-TC0 Parallel to Serial ＋ － TC P/N 7 TD6-TD0 Parallel to Serial ＋ － TD P/N 7 TE6-TE0 Parallel to Serial ＋ － TE P/N RS RF XRST Figure-1 Block Diagram 2 / 20 ●TQFP64V Package Outline and Specification Product No. BU8254KVT Lot No. 1PIN MARK Figure–2 TQFP64V Package Outline and Specification 3 / 20 ●Pin configuration GND GND TB2 TB5 TB4 TB0 TA6 TB3 TB1 TA5 TA4 TA3 TA2 TA1 34 47 48 46 45 44 43 42 41 40 39 38 37 36 35 TB6 TC0 VDD TC1 TC2 TC3 TC4 GND TC5 TC6 TDO RF TD1 TD2 TD3 TD4 33 32 31 30 29 28 27 LVDS GND TAN TAP TBN TBP LVDS VDD LVDS GND TCN TCP TCLKN TCLKP TDN TDP TEN TEP LVDS GND 26 25 24 23 22 21 20 19 18 17 TE6 16 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 10 11 12 13 14 15 PLL VDD 1 2 3 4 5 6 7 8 9 64-Pin TQFP (Top View) CLK IN XRST GND GND VDD TD5 TD6 TE0 TE1 TE2 TE3 TE4 TE5 Figure-3 Pin Diagram (Top View) 4 / 20 PLL GND TA0 RS ●Pin Description Table 1 : Pin Description Pin Name Pin No. TAP, TAN TBP, TBN TCP, TCN TDP, TDN TEP, TEN TCLKP, TCLKN TA0～TA6 TB0～TB6 TC0～TC6 TD0～TD6 TE0～TE6 XRST 30,31 28,29 24,25 20,21 18,19 22,23 33,34,35,36,37,38,40 41,42,44,45,46,48,49 50,52,53,54,55,57,58 59,61,62,63,64,1,3 4,5,6,8,9,11,16 13 Type LVDS OUT LVDS OUT LVDS OUT LVDS OUT LVDS OUT LVDS OUT IN IN IN IN IN IN H : Normal operation, L : Power down (all outputs are Hi-Z) LVDS swing mode, VREF *1select. RS RS 43 IN VDD 0.6～1.4V GND LVDS Swing 350mV 350mV 200mV Small Swing Input Support N/A RS-VREF N/A Pixel data inputs. Descriptions LVDS data out. LVDS clock out. *1 VREF is Input Reference Voltage. RF VDD CLKIN GND LVDS VDD LVDS GND PLLVDD PLLGND 60 51,7 12 2,10,39,47,56 27 17,26,32 15 14 IN Power IN Ground Power Ground Power Ground Input clock triggering edge select. H : Rising edge, L : Falling edge. Power supply pins for LVCMOS inputs and digital core. Clock input. Ground pins for LVCMOS inputs and digital core. Power supply pins for LVDS outputs. Ground pins for LVDS outputs. Power supply pin for PLL core. Ground pins for PLL core. 5 / 20 ●Electrical characteristics ■Rating Table 2 : Absolute Maximum Rating Parameter Supply Voltage Input Voltage Output Voltage Storage Temperature Range Symbol VDD VIN VOUT Tstg Rating Min -0.3 -0.3 -0.3 -55 Max 4.0 VDD+0.3 VDD+0.3 125 Units V V V ℃ Table 3 : Package Power PACKAGE T QFP64V Power Dissipation (mW) 700 1000*2 De-rating (mW/℃) *1 7.0 10.0*2 *1:At temperature Ta >25℃ *2:Package power when mounting on the PCB board. The size of PCB board :70×70×1.6（mm3） The material of PCB board :The FR4 glass epoxy board.(3% or less copper foil area) (It is recommended to apply the above package power requirement to PCB board when the small swing input mode is used) Table 4 : Recommended Operating Conditions Parameter Supply Voltage Operating Temperature Range Symbol M in VDD Topr 3.0 -20 0 Rating Typ 3.3 Max 3.6 85 70 V ℃ ℃ VDD,LVDSVDD,PLLVDD Clock frequency from 8MHz up to 90MHz Cock frequency from 90MHz up to 112MHz Units Conditions 6 / 20 ■DC characteristics Table 5 : LVCMOS DC Specifications（VDD=3.0V～3.6V, Ta=-20℃～85℃） Rating Symbol Parameter Units Min Typ Max VIH VIL VIHRS VILRS VDDQ*1 VREF VSH*2 VSL*2 IINC High Level Input Voltage Low Level Input Voltage High Level Input Voltage Low Level Input Voltage Small Swing Voltage Input Reference Voltage Small Swing High Level Input Voltage Small Swing Low Level Input Voltage Input Current VDD×0.8 GND VDD×0.8 GND 1.2 Conditions exclude RS pin VDDQ/2 VDD VDD×0.2 VDD 0.2 2.8 V V RS pin V VDDQ/2 +200mV VDDQ/2 -200mV ±10 V V μA Small Swing(RS=VDDQ/2) VREF=VDDQ/2 VREF=VDDQ/2 0V≤VIN≤VDD - - *1: VDDQ voltage defines max voltage of small swing input. It is not an actual input voltage. *2: Small swing signal is applied to TA[6:0], TB[6:0], TC[6:0], TD[6:0] TE[6:0], CLKIN. Table 6 : LVDS Transmitter DC Specifications（VDD=3.0V～3.6V, Ta=-20℃～85℃） Rating Symbol Parameter Units Conditions Min Typ Max VOD ΔVOD VOC ΔVOC IOS IOZ Differential Output Voltage Change in VOD between complementary output states Common Mode Voltage Change in VOC between complementary output states Output Short Circuit Current Output TRI-STATE Current 250 100 350 200 450 300 35 1.375 35 -24 ±10 mV mV mV V mV mA μA VOUT=0V, RL=100Ω XRST=0V, VOUT=0V to VDD RL=100Ω RL=100Ω Normal swing RS=VDD Reduced swing RS=GND 1.125 1.25 - - 7 / 20 ■Supply Current Table 7 : Supply Current Symbol Parameter Rating Typ 57 Max - Units mA Conditions RL=100Ω,CL=5pF VDD=3.3V,RS=VDD Gray Scale Pattern RL=100Ω,CL=5pF VDD=3.3V,RS=GND Gray Scale Pattern RL=100Ω,CL=5pF VDD=3.3V,RS=VDD Worst Case pattern RL=100Ω,CL=5pF VDD=3.3V,RS=GND Worst Case pattern XRST=L f=85MHz ITCCG Transmitter Supply Current 42 mA f=85MHz 62 ITCCW Transmitter Supply Current 45 ITCCS Transmitter Power Down Supply Current - mA f=85MHz 10 mA μA f=85MHz - 8 / 20 Gray Scale Pattern CLKOUT Rx0 Rx1 Rx2 Rx3 Rx4 Rx5 Rx6 X=A,B,C,D,E Figure-4 Gray scale pattern Worst Case Pattern (Maximum Power condition) CLKOUT Rx0 Rx1 Rx2 Rx3 Rx4 Rx5 Rx6 X=A,B,C,D,E Figure-5 Worst Case Pattern 9 / 20 ■AC characteristics Table 8 : Switching Characteristics Parameter Symbol tTCIT tTCP tTCH tTCL tTCD tTS tTH tLVT tTOP1 tTOP0 tTOP6 tTOP5 tTOP4 tTOP3 tTOP2 tTPLL CLK IN Transition time CLK IN Period CLK IN High Time CLK IN Low Time CLK IN to TCLK+/-Delay LVSMOS Data Set up to CLK IN LVCMOS Data Hold from CLK IN LVDS Transition Time Output Data Position 0 Output Data Position 1 Output Data Position 2 Output Data Position 3 Output Data Position 4 Output Data Position 5 Output Data Position 6 Phase Locked Loop Set Time Min 8.93 0.35tTCP 0.35tTCP 2.5 0 -0.2 Typ 0.5tTCP 0.5tTCP tTCP 0.6 0.0 Max 5.0 125.0 0.65tTCP 0.65tTCP 1.5 +0.2 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms tTCP -0.2 7 tTCP -0.2 2 7 tTCP -0.2 3 7 tTCP -0.2 4 7 tTCP -0.2 5 7 tTCP 6 -0.2 7 - tTCP 7 tTCP 2 7 tTCP 3 7 tTCP 4 7 tTCP 5 7 tTCP 6 7 - tTCP +0.2 7 tTCP 2 +0.2 7 tTCP 3 +0.2 7 tTCP 4 +0.2 7 tTCP 5 +0.2 7 tTCP 6 +0.2 7 10.0 10 / 20 ●AC Timing ■AC Timing Diagrams LVCMOS Input CLK IN 10% tTCIT tTCIT 10% 90% 90% LVDS Output Vdiff=(TAP)-(TAN) TAP CL TAN LVDS Output Load RL 80% Vdiff 20% 80% 20% tLVT tLVT LVCMOS Input tTCH CLKIN VDD/2 VDD/2 tTCP RF=L VDD/2 tTCL tTS Tx0-Tx6 VDD/2 RF=H tTH VDD/2 tTCD TCLKP VOC TCLKN Figure-6 AC Timing Diagrams 11 / 20 ■Small Swing Inputs tTCP tTCH RF=L CLKIN VDDQ/2 VDDQ/2 VDDQ/2 VREF RF=H tTCL tTS Tx0-Tx6 VDDQ/2 tTH VDDQ VDDQ/2 VREF GND tTCD TCLKP VOC TCLKN Figure-7 Small Swing Inputs 12 / 20 ■AC Timing Diagrams LVDS Output TCLK OUT (Differential) TAP/N TBP/N TCP/N TDP/N TEP/N TA6 TA5 TA4 TA3 TA2 TA1 TA0 TB6 TB5 TB4 TB3 TB2 TB1 TB0 TC6 TC5 TC4 TC3 TC2 TC1 TC0 TD6 TD5 TD4 TD3 TD2 TD1 TD0 TE6 TE5 TE4 TE3 TE2 TE1 TE0 Previous Cycle tTOP1 tTOP0 tTOP6 tTOP5 tTOP4 tTOP3 tTOP2 Next Cycle Figure-8 AC Timing Diagrams ■Phase Locked Loop Set Time 2.0V XRST 3.0V VDD tTPLL 3.6V CLKIN Vdiff=0V TCLKP/N Figure-9 Phase Locked Loop Set Time 13 / 20 ●About the Power On Reset Power On Reset is not mandatory for this device. （The PD pin should be set to high level when Power On Reset procedure is not used.） VDD XRST BU8254KVT Figure–10 Terminal connection when Power On Reset is not used However, Power On Reset procedure is strongly recommend for internal logic initialization by following two methods. ① The method of using CR circuit. ② The method of using external specific IC. It is recommend to do enough examination for target application. V DD schottky barrier diode V DD 10KΩ VDD XRST VT + 220Ω Be careful of temperature of the capacitor especially over and again. B characteristic ceramics and polymer aluminum are recommended. 2.2μF XRST Internal Reset td td is approximately equal to 20ms when the left RC coleus are applied. Figure–11 Power On Reset by external a CR circuit V DD VDD power on IC (open drain output) VOUT V DD 220KΩ XRST XRST 0.1μF Internal Reset td Detection voltage VDD VT + GND B Characteristic ceramics. Figure–12 Power On Reset by specific IC 14 / 20 ●10bit LVCMOS Level Input Example: BU7986KUT ： Falling edge Normal swing Dual-in / Dual-out mode VDD 0.1uF 0.01uF VDD LVDS VDD 0.1uF 0.01uF GND R1[9:0] G1[9:0] B1[9:0] R2[9:0] G2[9:0] B2[9:0] HSYNC VSYNC DE CLK_IN CONT11 CONT12 CONT21 CONT22 R1[9:0] G1[9:0] B1[9:0] R2[9:0] G2[9:0] B2[9:0] HSYNC VSYNC DE CLK_IN CONT11 CONT12 CONT21 CONT22 LVDS GND TA1N TA1P TB1N TB1P TC1N BU7986KUT TC1P TCLKN TCLKP TD1N TD1P TEST[3:0] TE1N TE1P MODE0 TA2N TA2P TB2N MODE1 TB2P TC2N XRST VDD XRST TC2P TCLKN TCLKP RS *1 TD2N TD2P R/F TE2N TE2P 100Otwist pair Cable or PCB trace PCB(Transmitter) *1 : If RS pin is tied to VDD, LVDS swing is 350m V. If RS pin is tied to GND, LVDS swing is 200m V. 15 / 20 ●10bit LVCMOS Level Input Example: BU7986KUT ： Falling edge Normal swing Dual-in / Single-out mode VDD 0.1uF 0.01uF VDD LVDS VDD 0.1uF 0.01uF GND R1[9:0] G1[9:0] B1[9:0] R2[9:0] G2[9:0] B2[9:0] HSYNC VSYNC DE CLK_IN CONT11 CONT12 CONT21 CONT22 R1[9:0] G1[9:0] B1[9:0] R2[9:0] G2[9:0] B2[9:0] HSYNC VSYNC DE CLK_IN CONT11 CONT12 CONT21 CONT22 LVDS GND TA1N TA1P TB1N TB1P TC1N BU7986KUT TC1P TCLKN TCLKP TD1N TD1P TEST[3:0] VDD MODE0 TE1N TE1P TA2N TA2P TB2N MODE1 TB2P TC2N XRST VDD XRST TC2P TCLKN TCLKP OPEN RS *1 TD2N TD2P R/F TE2N TE2P 100Otwist pair Cable or PCB trace PCB(Transmitter) *1 : If RS pin is tied to VDD, LVDS swing is 350m V. If RS pin is tied to GND, LVDS swing is 200m V. 16 / 20 ●10bit LVCMOS Level Input Example: BU7986KUT ： Falling edge Normal swing Single-in / Dual-out mode VDD 0.1uF 0.01uF VDD LVDS VDD 0.1uF 0.01uF LVDS GND GND R1[9:0] G1[9:0] B1[9:0] R1[9:0] G1[9:0] B1[9:0] R2[9:0] G2[9:0] B2[9:0] HSYNC VSYNC DE CLK_IN CONT11 CONT12 HSYNC VSYNC DE CLK_IN CONT11 CONT12 CONT21 CONT22 TEST[3:0] TA1N TA1P TB1N TB1P TC1N BU7986KUT TC1P TCLKN TCLKP TD1N TD1P TE1N TE1P TA2N MODE0 VDD MODE1 TA2P TB2N TB2P TC2N TC2P XRST VDD XRST TCLKN TCLKP RS *1 TD2N TD2P TE2N R/F TE2P 100Otwist pair Cable or PCB trace PCB(Transmitter) *1 : If RS pin is tied to VDD, LVDS swing is 350m V. If RS pin is tied to GND, LVDS swing is 200m V. 17 / 20 ●10bit LVCMOS Level Input Example: BU7986KUT ： Falling edge Normal swing Single-in / Single -out mode VDD 0.1uF 0.01uF VDD LVDS VDD 0.1uF 0.01uF LVDS GND GND R1[9:0] G1[9:0] B1[9:0] R1[9:0] G1[9:0] B1[9:0] R2[9:0] G2[9:0] B2[9:0] HSYNC VSYNC DE CLK_IN CONT11 CONT12 HSYNC VSYNC DE CLK_IN CONT11 CONT12 CONT21 CONT22 TEST[3:0] VDD MODE0 VDD MODE1 TA1N TA1P TB1N TB1P TC1N BU7986KUT TC1P TCLKN TCLKP TD1N TD1P TE1N TE1P TA2N TA2P TB2N TB2P TC2N TC2P OPEN XRST VDD XRST TCLKN TCLKP RS *1 TD2N TD2P TE2N R/F TE2P 100Otwist pair Cable or PCB trace PCB(Transmitter) *1 : If RS pin is tied to VDD, LVDS swing is 350m V. If RS pin is tied to GND, LVDS swing is 200m V. 18 / 20 ●10bit Small Swing Input Example: BU8254KVT ： LVCMOS level input/Falling edge/Normal swing BU8255KVT ： Falling edge VDD F.Bead *3 F.Bead *3 VDD 0.1uF 0.01uF CLKIN R4 R5 R6 R7 R8 R9 G4 G5 G6 G7 G8 G9 B4 B5 B6 B7 B8 B9 HSYNC VSYNC DE R2 R3 G2 G3 B2 B3 R0 R1 G0 G1 B0 B1 VDD GND LVDS VDD 0.1uF 0.01uF LVDS GND PLL VDD PLL GND 0.1uF 0.01uF 0.1uF 0.01uF 100Ω 0.1uF 0.01uF LVDD VDD GND 0.1uF 0.01uF CLKOUT R4 R5 R6 R7 R8 R9 G4 G5 G6 G7 G8 G9 B4 B5 B6 B7 B8 B9 HSYNC VSYNC DE R2 R3 G2 G3 B2 B3 OPEN R0 R1 G0 G1 B0 B1 OPEN PD OE CLKIN TA0 TA1 TA2 TA3 TA4 TA5 TA6 TB0 TB1 TB2 TB3 TB4 TB5 TB6 TC0 TC1 TC2 TC3 TC4 TC5 TC6 TD0 TD1 TD2 TD3 TD4 TD5 TD6 TE0 TE1 TE2 TE3 TE4 TE5 TE6 XRST *4 RS *4 R/F LGND PVDD PGND TAN TAP TBN TBP TCN TCP RARA+ RBRB+ RCRC+ RCLKRCLK+ RDRD+ RERE+ 100Ω 100Ω BU8254KVT TCLKN TCLKP TDN TDP TEN TEP 100Ω 100Ω 100Ω CLKOUT RA0 RA1 RA2 RA3 RA4 RA5 RA6 RB0 RB1 RB2 RB3 RB4 RB5 RB6 RC0 RC1 RC2 RC3 RC4 RC5 RC6 RD0 BU8255KVT RD1 RD2 RD3 RD4 RD5 RD6 RE0 RE1 RE2 RE3 RE4 RE5 RE6 PD OE DK R/F XRST 100Ω twist pair Cable or PCB trace PCB(Transmitter) PCB(Receiver) *3 : Recommended Parts: F.Bead : BLM18A-Series (Murata Manufacturing) *4 : RS pin acts as VREF input pin when input voltage is set to half of high level signal input. We recommend to locate by-pass condenser near the RS pin. VDD R1 15k RS pin. R2 5.6k C1=0.1uF Example for LVCMOS(1.8V input):(R1,R2)=(15kΩ,5.6kΩ) 19 / 20 TQFP64V 12.0 ± 0.3 10.0 ± 0.2 48 33 32 Container Quantity Direction of feed 0.5 Tray(with dry pack) 1000pcs Direction of product is fixed in a tray. 12.0 ± 0.3 10.0 ± 0.2 49 64 1 16 17 0.125 ± 0.1 1.0 ± 0.1 0.1 ± 0.1 0.5 0.2 ± 0.1 0.1 （Unit:mm) 1pin ※When you order , please order in times the amount of package quantity. Catalog No.08T240A '08.6 ROHM ©