BU8255KVT-E2

LVDS Interface ICs 35bit LVDS Receiver 5:35 DeSerializer BU8255KVT ●Description LVDS Interface IC of ROHM "Serializer" "Deserializer" operate from 8MHz to 150MHz wide clock range, and number of bits range is from 35 to 70. Data is transmitted seven times (7X) stream and reduce cable number by 3(1/3) or less. The ROHM's LVDS has low swing mode to be able to expect further low EMI. ●Features ■Five channels of LVDS data stream are converted to 35bits data of parallel LVCMOS level outputs. ■30bits of RGB output data, 5bits of timing and control output data(HSYNC, VSYNC, DE, CTL1 and CTL2) are transmitted available. ■Support clock frequency from 8MHz up to 112MHz. ■Support consumer video format including 480i, 480P, 720P and 1080i as well. ■Support many kinds of PC video formats such as VGA, SVGA, XGA and SXGA. ■Provide 784Mbps per 1ch or 3.92Gbps per device throughput rate using 112MHz clock rate. ■User programmable LVCMOS data output triggering timing by using either rising or falling edge of clock. ■30bit LVDS transmitter is recommended to use BU8254KVT. ●Applications Flat Panel Display ◇Precaution ･This chip is not designed to protect from radioactivity. ･The chip is made strictly for the specific application or equipment. Then it is necessary that the unit is measured as need. ･This document may be used as strategic technical data which subjects to COCOM regulations. Status of this document The Japanese version of this document is the formal specification. A customer may use this translation version only for a reference to help reading the formal version. If there are any differences in translation version of this document, formal version takes priority. Jun.2008 ●Block Diagram LVDS Differential Input RCLK ＋/－ (8～112MHz) LVCMOS Output ＋ － PLL 7 CLKOUT Sampling Clocks 7 RA ＋/－ ＋ － Serial to Parallel RB ＋/－ ＋ － Serial to Parallel RC ＋/－ ＋ － RD ＋/－ ＋ － RE ＋/－ ＋ － RA6-RA0 7 RB6-RB0 7 Serial to Parallel RC6-RC0 7 Serial to Parallel RD6-RD0 7 Serial to Parallel LVCMOS Input RESERVE PD OE R/F Figure-1 Block Diagram 2 / 17 RE6-RE0 ●TQFP64V Package Specification Product No. BU8255KVT 1PIN MARK Lot No. Figure–2 TQFP64V Package 3 / 17 RA1 RA2 GND RA3 RA4 RA5 RA6 RB0 RB1 VDD RB2 RB3 RB4 46 45 44 43 42 41 40 39 38 37 36 35 34 RB5 RA0 47 33 VDD 48 ●Pin Diagram 49 32 RB6 RA+ 50 31 CLKOUT RB_ 51 30 GND RB+ 52 29 RC0 LVDD 53 28 RC1 RC_ 54 27 RC2 RC+ 55 26 RC3 RCLK_ 56 25 RC4 RCLK+ 57 24 RC5 LGND 58 23 VDD RD_ 59 22 RC6 RD+ 60 21 RD0 RE_ 61 20 RD1 RE+ 62 19 RD2 PGND 63 18 RD3 PVDD 64 17 RD4 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESERVE PD OE R/F RE6 RE5 RE4 VDD RE3 RE2 RE1 RE0 RD6 RD5 Figure-3 Pin diagram (Top view) 4 / 17 GND 1 GND 64-Pin TQFP (Top View) 16 RA_ ●Pin Description Table .1: Pin description Pin Name Pin No. I/O RA+, RA- 50,49 LVDS Input RB+, RB- 52,51 LVDS Input RC+, RC- 55,54 LVDS Input RD+, RD- 60,59 LVDS Input RE+, RE- 62,61 LVDS Input RCLK+, RCLK- 57,56 LVDS Input RA6～RA0 RB6～RB0 RC6～RC0 RD6～RD0 RE6～RE0 40,41,42,43, 45,46,47 32,33,34,35, 36,38,39 22,24,25,26, 27,28,29 14,15,17,18, 19,20,21 6,7,8,10,11,1 2,13 Description LVDS data input + : Positive input of LVDS data differential pair. - : Negative input of LVDS data differential pair. LVDS clock input Output Output Output LVCMOS data outputs. Output Output RESERVE 2 Input Reserved input, must be “Low” for normal operation. PD 3 Input OE 4 Input R/F 5 Input VDD 9,23,37,48 Power 3.3V output driver and digital core power supply pin. CLKOUT 31 Output LVCMOS level clock output. GND 1,16,30,44 Ground GND pin for both data output driver cells and the digital cores. LVDD 53 Power Power supply pin for LVDS inputs. LGND 58 Ground Ground pin for LVDS inputs. PVDD 64 Power Power supply pin for PLL core. PGND 63 Ground Ground pin for PLL core. Power down input for the internal system. H: Normal operation. L: Power down (All output are “Low”). Power down input for the data output driver. H: Output enable (Normal operation). L: Output disable(All outputs are “Hi-Z”). Select input pin for data output clock triggering edge. H: Output data is latched on rising edge. L: Output data is latched on falling edge. 5 / 17 ●Function Description Table .2: Function explanation list PD R/F OE Data output (Rxn) *1 Clock output 0 0 0 Hi-Z Hi-Z 0 0 1 All fixed low Fixed Low 0 1 0 Hi-Z Hi-Z 0 1 1 All fixed low Fixed Low 1 0 0 Hi-Z Hi-Z 1 0 1 Data output Output data is latched by falling edge of clock. 1 1 0 Hi-Z Hi-Z 1 1 1 Data output Output data is latched by rising edge of clock *1：Rxn x = A,B,C,D,E n = 0,1,2,3,4,5,6 6 / 17 ●Electrical Characteristics ■Rating Table .3: Absolute maximum rating Item Symbol Supply voltage Input voltage Output voltage Storage temperature range VDD VIN VOUT Tstg Value Unit Min. Max. -0.3 -0.3 -0.3 -55 4.0 VDD+0.3 VDD+0.3 125 V V V ℃ Table .4: Package power Package TQFP64V PD(mW) DERATING(mW/℃) 700 7.0 1000*2 10.0*2 *1 *1 At temperature Ta > 25℃ *2 Package power when mounting on the PCB board. The size of PCB board :70×70×1.6（mm3） The material of PCB board :The FR4 glass epoxy board.(3% or less copper foil area) Table .5: Recommended operating conditions Min. Value Typ. Max. VDD 3.0 3.3 Supply Noise Voltage VNOZ - Operating temperature range Topr Item Symbol Supply voltage Unit Condition 3.6 V VDD, LVDD, PVDD - 0.1 V -20 - 85 ℃ Clock frequency from 8MHz up to 90MHz 0 - 70 ℃ Clock frequency from 90MHz up to 112MHz 7 / 17 ■DC Characteristics Table .6: LVCMOS DC character （VDD=3.0V～3.6V, Ta=-20℃～85℃） Value Symbol Item Unit Min. Typ. Max. Condition VIH High Input voltage VDD×0.8 - VDD V VIL Low Input voltage 0.0 - VDD×0.2 V VOH High Output voltage VDD-0.5 - VDD V IOH=-4mA (data) IOH=-8mA (clock) VOL Low Output voltage 0.0 - 0.4 V IOL=4mA (data) IOL=8mA (clock) IINC Input current - - ±10 μA Table .7: LVDS Receiver DC character （VDD=3.0V～3.6V, Ta=-20℃～85℃） Value Symbol Item Unit Min. Typ. Max. 0V≤VIN≤VDD Condition VTH Differential input High threshold - - 100 mV VOC*1=1.2V VTL Differential input Low threshold -100 - - mV VOC*1=1.2V IINL Input current - - ±25 μA VIN=2.4V / 0V VDD=3.6V *1Common Mode Voltage 8 / 17 ■Supply Current Table .8: Supply current Symbol IRCCG IRCCW IRCCS Value Item Receiver supply current (Gray Scale Pattern) Receiver supply current (Worst Case Pattern) Receiver power down supply current Unit Condition Min. Max. 52 - mA fCLKOUT=90MHz CL=8pF, VDD=3.3V 95 - mA fCLKOUT=90MHz CL=8pF, VDD=3.3V - 10 μA PD=L, OE=L Gray Scale Pattern CLKOUT Rx0 Rx1 Rx2 Rx3 Rx4 Rx5 Rx6 x=A,B,C,D,E Figure-4 Gray Scale Pattern Worst Case Pattern (Maximum power condition) CLKOUT Rx0 Rx１ Rx2 Rx3 Rx4 Rx5 Rx6 x=A,B,C,D,E Figure-5 Worst Case Pattern 9 / 17 ■AC Characteristics Table .9 : Switching characteristics Symbol Item Min. Value Typ. Max. 8.93 - 125 ns Unit tRCP CLKOUT period tRCH CLKOUT "H" time - 0.5tRCP-1.0 - ns tRCL CLKOUT "L" time - 0.5tRCP-1.0 - ns tRS LVCMOS data setup to CLKOUT 0.5tRCP-1.4 - - ns tRH LVCMOS data hold from CLKOUT 0.23tRCP-1.0 - - ns tTLH LVCMOS data rise time - 1.0 2.0 ns tTHL LVCMOS data fall time - 1.0 2.0 ns tRIP1 Input data position0 -0.25 0.0 +0.25 ns tRIP0 Input data position1 tRIP6 Input data position2 tRIP5 Input data position3 tRIP4 Input data position4 tRIP3 Input data position5 tRIP2 Input data position6 Phase Locked Loop set time tRCIP 7 tRCIP 2 7 tRCIP 3 7 tRCIP 4 7 tRCIP 5 7 tRCIP 6 7 - tRCIP +0.25 7 tRCIP 2 +0.25 7 tRCIP 3 +0.25 7 tRCIP 4 +0.25 7 tRCIP 5 +0.25 7 tRCIP 6 +0.25 7 tRPLL tRCIP -0.25 7 tRCIP -0.25 2 7 tRCIP -0.25 3 7 tRCIP -0.25 4 7 tRCIP -0.25 5 7 tRCIP -0.25 6 7 - 10.0 ms tRCIP Clock input period 8.93 - 125 ns 10 / 17 ns ns ns ns ns ns ●AC Timing Diagrams ■LVCMOS LVCMOS output 80% 80% 20% CL=8pF 20% LVCMOS output load tTLH tRCH CLKOUT tRCL VDD/2 VDD/2 tTHL R/F=L VDD/2 VDD/2 R/F=H tRCP tRS Rxn tRH VDD/2 x=A,B,C,D,E n=0,1,2,3,4,5,6 VDD/2 Figure–6 LVCMOS output timing ■Phase-Locked Loop set time 3.0V VDD RCLK +/- VDD/2 PD tRPLL VDD/2 CLKOUT Figure–7 Phase-Locked Loop set time 11 / 17 ●LVDS Data, Clock Input Timing Current cycle Previous cycle Next cycle tRCIP RCLK + (Differential) Vdiff=0V Vdiff=0V RA+/- RA3 RA2 RA1 RA0 RA6 RA5 RB+/- RB3 RB2 RB1 RB0 RB6 RB5 RC+/- RC3 RC2 RC1 RC0 RC6 RD+/- RD3 RD2 RD1 RD0 RE2 RE1 RE0 RE+/- RE3 RA3 RA2 RA1 RA0 RA6 RB4 RB3 RB2 RB1 RB0 RB6 RC5 RC4 RC3 RC2 RC1 RC0 RC6 RD6 RD5 RD4 RD3 RD2 RD1 RD0 RD6 RE6 RE5 RE4 RE3 RE2 RE1 RE0 RE6 RA4 tRIP1 tRIP0 tRIP6 tRIP5 tRIP4 tRIP3 tRIP2 Figure-8 LVDS data and clock input timing 12 / 17 ●LVDS Data, Clock Input and LVSMOS Output Timing LVDS Input RA+/- RA6 RA5 RA4 RA3 RA2 RA1 RA0 RB+/- RB6 RB5 RB4 RB3 RB2 RB1 RB0 RC+/- RC6 RC5 RC4 RC3 RC2 RC1 RC0 RD+/- RD6 RD5 RD4 RD3 RD2 RD1 RD0 RE+/- RE6 RE5 RE4 RE3 RE2 RE1 RE0 RCLK+/- LVCMOS Output CLKOUT (R/F=L) CLKOUT (R/F=H) RA0～6 VALID VALID RB0～6 VALID VALID RC0～6 VALID VALID RD0～6 VALID VALID RE0～6 VALID VALID Figure-9 LVDS Data, Clock Input and LVCMOS Output Timing 13 / 17 ●About the Power On Reset Power on reset is not mandatory for this device. （The PD pin should be set to high level when power on reset procedure is not used.） VDD PD BU8255KVT Figure-10 Terminal connection when power on reset is not used. However, Power on reset procedure is strongly recommend for internal logic initialization by following two methods. ① The method of using CR circuit. ② The method of using external specific IC. It is recommend to do enough examination for target application. VDD schottky barrier diode VDD VDD 10KΩ V T+ PD 220Ω PD 2.2μF Be careful of temperature of the capacitor especially over and again. B characteristic ceramics and function polymer aluminum electrolysis are recommended. VDD VDD Power on IC (Open drain output) Internal Reset ｔｄ td is approximately equal to 20ms when the left RC coleus are applied. Figure-11 Power on reset by external a CR circuit VDD 220KΩ PD Detection voltage VDD PD V T+ VOUT GND 0.1μF B Characteristic ceramics. Internal Reset ｔｄ Figure–12 Power on reset by specific IC 14 / 17 ●10 LVDS Level Input & Output Example: BU8254KVT ： LVCMOS level input/Falling edge/LVDS normal(350mV) swing output BU8255KVT ： LVCMOS level output/Falling edge VDD F.Bead *1 VDD GND 0.1uF 0.01uF CLKIN TA0 TA1 TA2 TA3 TA4 TA5 TA6 TB0 TB1 TB2 TB3 TB4 TB5 TB6 TC0 TC1 TC2 TC3 TC4 TC5 TC6 TD0 TD1 TD2 TD3 TD4 TD5 TD6 TE0 TE1 TE2 TE3 TE4 TE5 TE6 CLKIN R4 R5 R6 R7 R8 R9 G4 G5 G6 G7 G8 G9 B4 B5 B6 B7 B8 B9 HSYNC VSYNC DE R2 R3 G2 G3 B2 B3 R0 R1 G0 G1 B0 B1 XRST LVDD LVDS VDD 0.1uF 0.01uF LGND PLL VDD PLL GND PVDD 0.1uF 0.01uF 0.1uF 0.01uF TAN 100Ω TAP TBN 100Ω TBP TCN 100Ω TCP TCLKN 100Ω TCLKP TDN 100Ω TDP TEN 100Ω TEP XRST RS *2 RARA+ RBRB+ RCRC+ RCLKRCLK+ RDRD+ RERE+ CLKOUT RA0 RA1 RA2 RA3 RA4 RA5 RA6 RB0 RB1 RB2 RB3 RB4 RB5 RB6 RC0 RC1 RC2 RC3 RC4 RC5 RC6 RD0 BU8255KVT RD1 RD2 RD3 RD4 RD5 RD6 RE0 RE1 RE2 RE3 RE4 RE5 RE6 DK R/F R/F PCB(Transmitter) PGND VDD GND PD OE 100Ωtwist pair Cable or PCB trace VDD 0.1uF 0.1uF 0.01uF LVDS GND BU8254KVT VDD F.Bead *1 PCB(Receiver) ＊1 Recommended Parts： F.Bead ： BLM18A-Series （Murata Manufacturing Co.） ＊2 :If RS pin is tied to VDD,LVDS swing is 350m V. If RS pin is tied to GND,LVDS swing is 200m V. 15 / 17 0.1uF 0.01uF CLKOUT R4 R5 R6 R7 R8 R9 G4 G5 G6 G7 G8 G9 B4 B5 B6 B7 B8 B9 HSYNC VSYNC DE R2 R3 G2 G3 B2 B3 OPEN R0 R1 G0 G1 B0 B1 OPEN PD OE ●10bit Small Swing Input & LVCMOS Level Output Example: BU8254KVT ： LVCMOS level input/Falling edge/LVDS normal(350mV) swing output BU8255KVT ： LVCMOS level output/Falling edge VDD F.Bead *3 VDD GND 0.1uF 0.01uF CLKIN TA0 TA1 TA2 TA3 TA4 TA5 TA6 TB0 TB1 TB2 TB3 TB4 TB5 TB6 TC0 TC1 TC2 TC3 TC4 TC5 TC6 TD0 TD1 TD2 TD3 TD4 TD5 TD6 TE0 TE1 TE2 TE3 TE4 TE5 TE6 CLKIN R4 R5 R6 R7 R8 R9 G4 G5 G6 G7 G8 G9 B4 B5 B6 B7 B8 B9 HSYNC VSYNC DE R2 R3 G2 G3 B2 B3 R0 R1 G0 G1 B0 B1 XRST LVDS VDD LVDD 0.1uF 0.01uF 0.1uF 0.01uF LVDS GND LGND PLL VDD PLL GND PVDD 0.1uF 0.01uF 0.1uF 0.01uF TAN 100Ω TAP TBN 100Ω TBP TCN 100Ω TCP BU8254KVT VDD F.Bead *3 TCLKN 100Ω TCLKP TDN 100Ω TDP TEN 100Ω TEP XRST RS *4 RA+ RBRB+ RCRC+ RCLKRCLK+ RDRD+ RERE+ 0.1uF 0.01uF CLKOUT R4 R5 R6 R7 R8 R9 G4 G5 G6 G7 G8 G9 B4 B5 B6 B7 B8 B9 HSYNC VSYNC DE R2 R3 G2 G3 B2 B3 OPEN R0 R1 G0 G1 B0 B1 OPEN PD OE DK R/F R/F PCB(Transmitter) RA- CLKOUT RA0 RA1 RA2 RA3 RA4 RA5 RA6 RB0 RB1 RB2 RB3 RB4 RB5 RB6 RC0 RC1 RC2 RC3 RC4 RC5 RC6 RD0 BU8255KVT RD1 RD2 RD3 RD4 RD5 RD6 RE0 RE1 RE2 RE3 RE4 RE5 RE6 PD OE 100Ωtwist pair Cable or PCB trace *4 PGND VDD GND PCB(Receiver) ＊3 Recommended Parts： F.Bead ： BLM18A-Series （Murata Manufacturing Co.） ＊4 :RS pin acts as VREF input pin when input voltage is set to half of high level signal input. We recommend to locate by-pass condenser near the RS pin. VDD R1 15k RS pin. R2 5.6k C1=0.1uF Example for LVTTL(1.8V input):(R1,R2)=(15kΩ,5.6kΩ) 16 / 17 TQFP64V 12.0 ± 0.3 10.0 ± 0.2 0.2 ± 0.1 1pin 17 16 0.125 ± 0.1 0.5 1000pcs Direction of product is fixed in a tray. 0.5 32 64 Tray(with dry pack) Quantity Direction of feed 33 49 1 1.0 ± 0.1 0.1 ± 0.1 12.0 ± 0.3 10.0 ± 0.2 48 Container 0.1 （Unit:mm) ※When you order , please order in times the amount of package quantity. Catalog No.08T238A '08.6 ROHM ©