BU8732AKV-E2

BU8732AKV Communication ICs CODEC IC for digital mobile phone BU8732AKV BU8732AKV is a PCM codec IC for digital cellular phones. This includes plenty of analog input / output functions such as a 14bit precision linear. µ / A-LAW codec, a microphone amplifier with two systems, amplifiers for speaker and earphone and a switch transistor for driving a ringer. This IC is the most suitable for both PDC system and CDMA system cellular phones. zApplication Digital cellular phones with CDMA system, Digital cellular phones with PDC system. zFeatures 1) +3V single power supply. (VDD=2.7 to 3.3V) 2) 14bit precision linear ‚ µ / A-LAW codec. 3) Transmission filter of the codec block is in conformity to the ITU-T recommendation G. 714. 4) Built-in PLL circuit for system clock generation. 5) Built-in DSP I/F which is in conformity with PDC and N-CDMA. 6) Arbitrary setting of the clock frequency of PCM data transmission is allowed : µ / A-LAW 64kHz to 2048kHz Linear 128kHz to 2048kHz 7) Plenty of input / output analog functions : • Two systems of built-in microphone amplifier (differential input type, single input type) • Built-in speaker amplifier for receiver (32Ω BTL type) • Built-in speaker amplifier for earphone (32Ω single type) • Built-in speaker amplifier for REXT of call receiving system (600Ω) • Built-in electronic volumes for gain adjustment. (Call-receiving system, call sending system, TONE system) • Built-in input / output circuit for data signal which allows external connection. • Pop noise of REXT earphone and receiver outputs at the time of switching on and off the power supply is reduced by means of soft mute. 8) A built-in function to generate DTMF signals and musical scale tones is provided in the tone signal generating block. 9) Built-in switch transistor for driving a ringer. 10) VQFP 48 pin package. 1/10 BU8732AKV Communication ICs zAbsolute maximum rating (Ta=25°C unless specified particularly) Parameter Symbol Digital power supply voltage Analog power supply voltage Limits Unit DVDD −0.3 to +4.5 V RXVDD −0.3 to +4.5 V TXVDD −0.3 to +4.5 V Digital pin apply voltage VTD DVSS−0.3 to DVDD+0.3 V Analog pin apply voltage VTA RXVSS−0.3 to RXVDD+0.3 V TXVSS−0.3 to TXVDD+0.3 V Input current IIN Power dissipation Pd Storage temperature range Operation temperature range −10 to +10 mA 400 ∗1 mW Tstg −50 to +125 °C Ta −30 to +85 °C ∗1 Drops by 4.0mW per 1°C when used at more than Ta=25°C. zRecommendable operation condition (Ta=25°C unless specified particularly) Parameter Digital power supply voltege Analog power supply voltege Symbol Min. Typ. Max. Unit DVDD 2.7 − 3.3 V RXVDD 2.7 − 3.3 V TXVDD 2.7 − 3.3 V Radiation resistance is not included design. 2/10 BU8732AKV Communication ICs zBlock diagram TEXT 27 + MIC2IN 28 MIC20 29 TAUDO TXVDD 30 R7 TEXTADD 31 + 0.01µ 32 TEXTDI 33 C10 R8 TEXTDO 34 PLLLPF 35 FSYNC STB SRL SDA 36 C11 frame syne signal 8kHz for CPU 26 25 SW8 MIC10 24 PLL XPRSTB + MIC Amp2 38 SW0 + MIC1IP 1 − DTMF / TONE 2 DVDD 3 MIC Amp1 40 22 TXVSS 21 EV3 DSP I / F 41 BPF A/D TXREF + EV0 AAF 20 1µ PCMIN D/A 19 EV1 Vref / COMMON PWM 2.2µ CODECREF + 18 RG0 1µ CPUSEL 45 SW4 5 6 3 7 2 R9 ERP0 SPP0 RGPULSE 17 − ERMT 1µ SMUTE + 16 JAmp RINGER1 R10 46 0.22µ RXVDD − + EV6 − Amp3 EV5 EARO EAmp1 + 47 15 14 RAmp RINGER3 Amp4 − + 8 R2 9 SPPO 7 SPPN 6 ERPO 5 13 10 11 SPCON + ERPN 4 AUDVR + AUDO 3 RIN 2 EXTO REXTDO REXTDI PVSS 1 RXVSS C5 R1 Power on by VCPON C1 C2 12 R4 REXT Power on by REFPON EAR (32Ω) C7 EAmp2 SPCOP − + EV2 SW9B + Amp5 SW9A 48 − + + SPMT + EXTSEL RINGER2 (20Ω) RXREF + SOFTMUTE + 1 44 + 43 + LPF DCLK + REFC EV7 EV4 42 RINGER + PCMOUT DSP C8 R5 − Amp1 39 C9 23 + DVSS R6 MIC1IN + CPU I / F + SW12 37 − reset R3 C3 C6 C4 SPC (32Ω) Power on by TGPON Power on by VCPON or TGPON Power on by SPCON Power on by RXPON Power on by EARON 3/10 BU8732AKV Communication ICs zPin descriptions Minimum load resistance[Ω] Maximum load capacitance[F] Input of the data signal of receive − − Output of the data signal of receive − − 600 − − − Direct output of receive signal 50k 50p External output of receive signal 50k 50p − − 50k 50p − − 50k 50p 30(BTL) − Pin name I/O 1 REXTDI I/O 2 REXTDO I/O 3 EXTO O Amplifier output for the gain adjustment of receive signal 4 RIN I Direct input of the voice of receive 5 AUDO O 6 AUDVR O 7 ERPN I Inverted amplifier input for the earphone gain adjustment 8 ERPO O Amplifier output for the earphone gain adjustment 9 SPPN I Inverted amplifier input for the speaker gain adjustment 10 SPPO O Amplifier output for the speaker gain adjustment 11 SPCOP O Non-ineverted speaker amplifier output for the receiver 12 SPCON O Inverted speaker amplifier output for the receiver 30(BTL) − 13 RXVSS − Analog grounding for the receive − − 14 EARO O Speaker amplifier output for the earphone 30 − 15 RXVDD − Analog power source for the receive − − 16 SMUTE I Time constant terminal for the soft mute setting − 0.22µ∗1 17 RXREF O Analog reference voltage output for the receive − 1µ∗1 18 CODCREF O Analog reference voltage output for codec − 1µ∗1 19 REFC O Analog reference voltage output − 2.2µ∗1 20 TXREF O Analog reference voltage output for the transmit − 1µ∗1 21 TXVSS − Analog grounding for the transmit − − 22 MIC1IP I Non-inverted input of the microphone amplifier 1 − − 23 MIC1IN I Inverted input of the microphone amplifier 1 − − 24 MIC1O O Output of microphone amplifier 1 50k 50p 25 MIC2IN I Inverted input of the microphone amplifier 2 − − 26 MIC2O O Output of microphone amplifier 2 output 50k 50p 27 TAUDO O External output of transmit signal 50k 50p 28 TXVDD − Analog power source for the transmit − − 29 TEXTADD I Additive input of the transmit signal − − 30 TEXTDI I/O Input of the data signal of transmit − − 31 TEXTDO I/O Output of the data signal of transmit − − 32 PLLLPF I/O Filter connection input/output for PLL − 0.01µ∗1 33 FSYNC I PLL reference clock input − − 34 STB I Strobe input for CPU I/F − − 35 SCL I/O Shift clock input for CPU I/F − − 36 SDA I/O Address data input for CPU I/F − − 37 XPRSTB I System reset input (L: reset) − − 38 DVSS − Grounding for digital − − 39 DVDD − Power supply for digital − − 40 PCMOUT O Output of PCM signal − − 41 PCMIN I Input of PCM signal − − DCLK 42 ∗1 Standard value I Shift clock input for PCM signal − − Pin No. Terminal function 4/10 BU8732AKV Communication ICs Pin No. Pin name I/O Terminal function Minimum load resistance[Ω] Maximum load capacitance[F] 43 CPUSEL I Fixed to GND, Fixed "L" − − 44 RGPULSE O Pulse output for the ringer − − 45 RINGER1 O Open drain output of the ringer driving transistor 100(at 3V) − 46 RINGER2 O Open drain output of the ringer driving transistor 60(at 3V) − 47 RINGER3 O Open drain output of the ringer driving transistor 20(at 3V) − 48 PVSS − Grounding for ringer − − ∗1 Standard value zElectrical characteristics (Ta=25°C, DVDD=RXVDD=TXVDD=3.0V, FSYNC=8kHz, gain 0dB unless specified particularly) Parameter Symbol Min. Typ. Max. IDD1 − 8.0 11.5 IDD2 − 7.0 10.2 Reference / Voice / SPC ON (Note2) IDD3 − 6.0 8.6 Reference / Voice / EAR ON (Note2) IDD4 − 5.4 7.8 IDD5 − 5.1 7.3 Reference / Voice ON (Note2) IDD6 − 3.7 5.3 Reference / Tone ON (Note2) IDD7 − 3.3 4.8 IDD8 − 0.1 20 µA Digital "H" level input voltage VIH 0.8DVDD − − V Digital "L" level input voltage VIL − − 0.2DVDD V Digital "H" level input current IIH − − 10 µA VIH=DVDD Current consumption(Note 1) Digital "L" level input current Digital "H" level output voltage Digital "L" level output voltage Unit Conditions Full operation (Note2) mA Reference / Voice / RAMP ON (Note2) Reference ON (Note2) All power down, FSYNC, Fixed DCLK terminal IIL −10 − − µA VIL=0V VOH DVDD−0.5 − − V IOH= −1mA VOL − − 0.5 V IOL=1mA ∗1) Power supply voltage (DVDD, RXVDD, TXVDD) is 3V. Digital and analog output terminals are free from load. All the digital terminals except FSYNC. CLK terminal are connected to either DVDD or DVSS. Analog terminals are connected with an appropriate resistance to TXREF or RXREF. The soft mute is in the canceled status. (SMUTE="0") ∗2) FSYNC=8kHz, DCLK=256kHz 5/10 BU8732AKV Communication ICs zElectrical characteristics (Ta=25°C, DVDD=RXVDD=TXVDD=3.0V, FSYNC=8kHz, DCLK=256kHz, gain 0dB, input signal frequency=1 kHz, 30 kHz LFP, specified particularly) < CODEC block > Parameter Symbol Transmit signal-to- Min. Typ. Max. 35 − − Unit 29 − − TEXTADD→PCMOUT 24 − − Receive signal-to- 35 − − distortion ratio 29 − − 24 − − −0.3 − 0.3 −0.6 − 0.6 −1.6 − 1.6 −0.3 − 0.3 −0.6 − 0.6 −1.6 − 1.6 VITX 0.257 0.346 0.436 Vrms VORX 0.291 0.346 0.411 Vrms 24 − − 0 − 2.5 distortion ratio SDT SDR PCMIN→AUDO Transmit Gain error TEXTADD→PCMOUT Receive Gain error PCMIN→AUDO Transmit reference signal level Receive reference signal level GTX GRX Transmit Gain relative to input signal gain at 1.02KHZ GRTX TEXTADD→PCMOUT 1.02KHZ TEXTADD→PCMOUT Receive noise level PCMIN→AUDO Noise level of speaker amplifier for receiver Noise level of speaker amplifier for earphone ∗3) 0.3 − 0.9 dB dB (LINEAR) ∗3) 1020Hz input (LINEAR) ∗3) 1020Hz, (LINEAR) ∗3) Reference level= −10dBm0 1020Hz, (LINEAR) ∗3) Reference level= −10dBm0 1020Hz, 0dBm0 EV0=0dB, (LINEAR) ∗3) 1020Hz, 0dBm0 EV1=0dB, (LINEAR) ∗3) 0 to −40dBm0 −40dBm0 −45dBm0 0 to −40dBm0 −40dBm0 −45dBm0 +3 to −40dBm0 −40 to −50dBm0 −50 to −55dBm0 +3 to −40dBm0 −40 to −50dBm0 −50 to −55dBm0 TEXTADD→ PCMOUT PCMIN→AUDO 0.2kHz 1020Hz, 0dBm0 dB Input reference EV0=0dB, (LINEAR) − − − − −0.3 − 0.3 −0.3 − 0.9 0 − − 6.5 − − VNTX − − −65 dBV VNRX − − −70 dBV VNSPC − −90 − dBV VNEAR − −93 − dBV GRRX 1020Hz input 0.06kHz 0 PCMIN→AUDO Transmit noise level − −0.3 dB 6.5 Receive Gain relative to input signal gain at −0.3 dB Conditions 0.3 to 3.0kHz 3.4kHz 3.6kHz 3.78kHz 0.3 to 3.0kHz 1020Hz, 0dBm0 dB Input reference EV1=0dB, (LINEAR) 3.4kHz 3.6kHz 3.78kHz EV0=0dB, (LINEAR) ∗3) PCMIN= "L" fixed, EV1=0dB, (LINEAR) ∗3) SPCOP-SPCON, RL=32Ω Connect SPPN-SPPO ∗3) EARO, RL=32Ω Connect ERPN-ERPO ∗3) Using C-MESSAGE filter 6/10 BU8732AKV Communication ICs < Analog element (1) > Parameter Max. Closed loop gain Min. Load impedance Max. Load capacitance Symbol Min. Typ. Max. GCMIC1 40 − − GCMIC2 40 − − GCAMP4 40 − − GCAMP5 40 − − AMP5, THD