BU8920GU

1/4 Structure Product Name Silicon monolithic integrated circuit PCM CODEC IC for cellular phone Product No. Physical dimentions Features BU8920GU Figure1 (VCSP85H2) · 16bit Linear・μ/A-Law codec · Built-in PLL circuit for system clock generation · Support for below frequency about PCM data transmission clock. μ/A-Law Linear 64kHz - 2048 kHz 128 kHz -2048 kHz · Built-in Output amplifier for line drives (600Ω) · Power down control using NRST pin ○ Absolute Maximum Ratings Parameter Digital supply voltage Analog supply voltage Input voltage for digital terminal Input voltage for analog terminal Input current Power dissipation *1 Storage temperature range ○ Symbol ＤＶＤＤ ＡＶＤＤ ＶＴＤ ＶＴＡ ＩＩＮ Ｐｄ Ｔｓｔｇ Rating －０．３～４．５ －０．３～４．５ ＤＶＳＳ－０．３～４．５ ＡＶＳＳ－０．３～ＡＶＤＤ＋０．３ －１０～＋１０ ２５０ －５５～１２５ Unit Ｖ Ｖ Ｖ Ｖ ｍＡ ｍＷ ℃ (*1) Note: Reduce to 2.5mW/℃ when Ta = 25℃ or above Recommended Operating Power Supply Voltage and temperature Range Parameter Digital supply voltage Analog supply voltage Operating temperature range Symbol ＤＶＤＤ ＡＶＤＤ Ｔopr Min １．６５ ２．７０ －３０ Rating Typ １．８０ ２．８０ Max １．９５ ３．１０ ８５ Unit Ｖ Ｖ ℃ This product is not designed to protect itself against radioactive rays. REV. B 2/4 ○ Electrical Characteristics Specified Value Typ Unless otherwise noted, Ta = 25℃、AVDD=2.8、DVDD=1.8V、FSYNC=8kHz、DCLK=256kHz. Parameter Current consumption Standby current consumption Full Operation DC Characteristics Digital H level input voltage Digital L level input voltage Digital H level input current Digital L level input current Digital H level output voltage Digital L level output voltage VIH VIL IIH IIL VOH VOL DVDDｘ0.75 NRST=DVSS and Symbol Min Max Unit Condition IDD1 IDD2 - 0.1 2.5 3.0 3.8 4.5 DVDDｘ0.25 1 -1 ＤＶＤＤ DVDDｘ0.2 uA FSYNC,DCLK=DVSS mA Ｖ Ｖ uA uA Ｖ Ｖ NRST,BST=DVDD, No input signal -0.3 DVDDｘ0.8 ０ - VIH=DVDD VIL=DVSS IOH= -1mA IOL= 1mA Unless otherwise noted, Ta=25°C,AVDD=2.7～3.1Ｖ,ＤＶＤＤ＝1.65～1.95Ｖ,FSYNC=8kHz,DCLK=256kHz,and linear mode. Parameter Transmit signal-to-distortion ratio (AUX1IN→PCMOUT) Receive signal-to-distortion ratio (PCMIN→AUDOUT) Transmit Gain Tracking (ＡＵＸ1ＩＮ→ＰＣＭＯＵＴ) Receive Gain Tracking (PCMIN→AUDOUT) Transmit reference level Receive reference level ＳＤＲ ＳＤＴ symbol Condition 0dBm0 1020Hz ＊2,＊3 -30dBm0 -40dBm0 -45dBm0 0dBm0 -30dBm0 -40dBm0 -45dBm0 +3.0～0.5dBm0 +0.5～-40dBm0 -40～-50dBm0 -50～-55dBm0 +3.0～-40dBm0 -40～-50dBm0 -50～-55dBm0 AUX1IN→PCMOUT PCMIN→AUDOUT Specified Value Min 45 35 29 24 45 35 29 24 -3.0 -0.3 -0.6 -1.6 -0.3 -0.6 -1.6 0.375 0.400 24 0 -0.3 -0.3 -0.3 0 6.5 24 0 -0.3 -0.3 -0.3 0 6.5 Typ 0.500 0.475 Max 3.0 0.3 0.6 1.6 0.3 0.6 1.6 0.667 0.564 2.5 0.5 0.3 0.9 2.5 0.3 0.5 0.9 -76 -85 Unit ｄＢ 1020Hz ＊2 1020Hz，Reference ｄＢ ＧＴＸ level=-10ｄＢｍ0 ＊2,＊3 1020Hz，Reference ｄＢ ＧＲＸ ＶＩＴＸ１ ＶＯＲＸ level=-10ｄＢｍ0, ＊2 1020Hz，0dBm0 ＊2 1020Hz，0dBm0 ＊2 ｄＢ Ｖｒｍｓ Ｖｒｍｓ 0.06kHz Transmit Gain Loss relative to Frequency (AUX1IN→PCMOUT) ＧＲＴＸ 0.2kHz 0.3～0.4kHz 1020Hz 0.4～3.0kHz 3.4kHz 3.6kHz 3.78kHz 0.06kHz 0.2kHz 0.3～2.8kHz 1020Hz 2.8～3.0kHz 3.4kHz 3.6kHz 3.78kHz AUX1IN= AGND level. ＊2 PCMIN=”L”. Using A-Weight filter. dB Receive Gain Loss relative to Frequency (PCMIN→AUDOUT) ＧＲＲＸ dB Transmit noise level Receive noise level ＊2 Using C-MESSAGE filter VNTX VNRX dBV dBV ＊3 Specified that 0dBm0 is 0.5Vrms REV. B 3/4 ○ Physical dimentions (Figure1) ○Ball assignment Ball No A1 A2 A3 A4 LOT No Ball name AVSS AUDOUT AVDD BGFLT NC AUX1IN PLLCAP AGND VREF FRM1 NC FSYNC BU8920 Ball No C5 D1 D2 D3 D4 D5 E1 E2 E3 E4 E5 Ball name PCMSEL FRM2 NRST DVDD PCMIN DCLK TEST DSEL BST DVSS PCMOUT A5 B1 B3 B4 B5 C1 C2 C4 Power down control using only NRST. NRST = L : Power down mode NRST = H : Active mode NC : This ball is not connected with internal. VCSP85H2（23Balls） （Unit: mm） ○ Block diagram (Figure2) BGFLT (A4) AVDD (A3) DVDD (D3) BIAS NRST (D2) BST (E3) AUX1IN (B1) AAF S to D ADC BPF PCM P to S PCM OUT (E5) FSYNC (C4) VREF (B5) System clock AGND (B4) PLL DCLK (D5) PLLCAP (B3) + AUDOUT (A2) + SM F D to S DAC BPF PCM S to P PCM IN (D4) TEST (E1) PCMSEL (C5) DSEL (E2) FRM 1 (C1) FRM 2 (D1) AVSS (A1) DVSS (E4) （）: Ball NO REV. B 4/4 ○ Cautions on use (1) Absolute Maximum Ratings An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down devices, thus making impossible to identify breaking mode such as a short circuit or an open circuit. If any special mode exceeding the absolute maximum ratings is assumed, consideration should be given to take physical safety measures including the use of fuses, etc. (2) Operating conditions These conditions represent a range within which characteristics can be provided approximately as expected. The electrical characteristics are guaranteed under the conditions of each parameter. (3) Reverse connection of power supply connector The reverse connection of power supply connector can break down ICs. Take protective measures against the breakdown due to the reverse connection, such as mounting an external diode between the power supply and the IC’s power supply terminal. (4) Power supply line Design PCB pattern to provide low impedance for the wiring between the power supply and the GND lines.In this regard, for the digital block power supply and the analog block power supply, even though these power supplies has the same level of potential, separate the power supply pattern for the digital block from that for the analog block, thus suppressing the diffraction of digital noises to the analog block power supply resulting from impedance common to the wiring patterns. For the GND line, give consideration to design the patterns in a similar manner. Furthermore, for all power supply terminals to ICs, mount a capacitor between the power supply and the GND terminal. At the same time, in order to use an electrolytic capacitor, thoroughly check to be sure the characteristics of the capacitor to be used present no problem including the occurrence of capacity dropout at a low temperature, thus determining the constant. (5) GND voltage Make setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state. Furthermore, check to be sure no terminals are at a potential lower than the GND voltage including an actual electric transient. (6) Short circuit between terminals and erroneous mounting In order to mount ICs on a set PCB, pay thorough attention to the direction and offset of the ICs. Erroneous mounting can break down the ICs. Furthermore, if a short circuit occurs due to foreign matters entering between terminals or between the terminal and the power supply or the GND terminal, the ICs can break down. (7) Operation in strong electromagnetic field Be noted that using ICs in the strong electromagnetic field can malfunction them. (8) Inspection with set PCB On the inspection with the set PCB, if a capacitor is connected to a low-impedance IC terminal, the IC can suffer stress. Therefore, be sure to discharge from the set PCB by each process. Furthermore, in order to mount or dismount the set PCB to/from the jig for the inspection process, be sure to turn OFF the power supply and then mount the set PCB to the jig. After the completion of the inspection, be sure to turn OFF the power supply and then dismount it from the jig. In addition, for protection against static electricity, establish a ground for the assembly process and pay thorough attention to the transportation and the storage of the set PCB. (9)Input terminals In terms of the construction of IC, parasitic elements are inevitably formed in relation to potential. The operation of the parasitic element can cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the input terminal. Therefore, pay thorough attention not to handle the input terminals, such as to apply to the input terminals a voltage lower than the GND respectively, so that any parasitic element will operate. Furthermore, do not apply a voltage to the input terminals when no power supply voltage is applied to the IC. In addition, even if the power supply voltage is applied, apply to the input terminals a voltage lower than the power supply voltage or within the guaranteed value of electrical characteristics. (10) Ground wiring pattern If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well. (11) External capacitor In order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a degradation in the nominal capacitance due to DC bias and changes in the capacitance due to temperature, etc. (12) Others In case of use this LSI, please peruse some other detail documents, we called ,Technical note, Functinal description, Application note. REV. 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