LVDS Interface ICs
35bit LVDS Receiver 5:35 DeSerializer
BU90R104
No.11057EAT09
●Description LVDS Interface IC of ROHM "Serializer" "Deserializer" operates from 8MHz to 150MHz wide clock range, and number of bits range is from 35 to 70. Data is transmitted seven times (7X) stream and reduce cable number by 3(1/3) or less. The ROHM's LVDS has low swing mode to be able to expect further low EMI. ●Features 1) Five channels of LVDS data stream are converted to 35bits data of parallel LVCMOS level outputs. 2) 30bits of RGB output data, 5bits of timing and control output data(HSYNC, VSYNC, DE, CTL1 and CTL2) are transmitted available. 3) Support clock frequency from 8MHz up to 112MHz. 4) Support consumer video format including 480i, 480P, 720P and 1080i as well. 5) Support many kinds of PC video formats such as VGA, SVGA, XGA and SXGA. 6) Provide 784Mbps per 1ch or 3.92Gbps per device throughput rate using 112MHz clock rate. 7) User programmable LVCMOS data output triggering timing by using either rising or falling edge of clock. 8) 30bit LVDS transmitter is recommended to use BU8254KVT. ●Applications Flat Panel Display ●Absolute maximum ratings Parameter Supply voltage Input voltage Output voltage Storage temperature range ●Package power Package TQFP64V
*1 *2
Symbol VDD VIN VOUT Tstg
Ratings Min. -0.3 -0.3 -0.3 -55 Max. 4.0 VDD+0.3 VDD+0.3 125
Unit V V V ℃
PD(mW) 700 1000
*2
DERATING(mW/℃) 7.0 10.0*2
*1
At temperature Ta > 25℃ Package power when mounting on the PCB board. The size of PCB board :70×70×1.6(mm3) The material of PCB board :The FR4 glass epoxy board.(3% or less copper foil area)
●Recommended operating conditions Parameter Supply voltage Supply Noise Voltage Symbol VDD VNOZ Ratings Min. 3.0 -20 Operating temperature range Topr 0 70 ℃ Typ. 3.3 Max. 3.6 0.1 85 Unit V V ℃ Clock frequency from 8MHz up to 90MHz Clock frequency from 90MHz up to 112MHz Condition VDD, LVDD, PVDD
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BU90R104
●Block Diagram
Technical Note
LVDS Differential Input
RCLK +/- (8~112MHz) + -
LVCMOS Output
PLL
7 Sampling Clocks 7 CLKOUT
RA +/-
+ -
Serial to Parallel
RA6-RA0
RB +/-
+ -
7
Serial to Parallel
RB6-RB0
RC +/-
+ -
7
Serial to Parallel
RC6-RC0
RD +/-
+ -
Serial to Parallel
7 RD6-RD0
RE +/-
+ -
7
Serial to Parallel
RE6-RE0
LVCMOS Input
RESERVE PD OE R/F
Fig.1 Block
Diagram
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BU90R104
●TQFP64V Package Specification
Technical Note
Product No.
BU90R104
Lot No.
1PIN MARK
(Unit : mm)
Fig.2 TQFP64V Package
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BU90R104
●Pin Diagram GND VDD RA5 RA6
Technical Note
VDD
RA0
RA1
RA2
RA3
RA4
RB0
RB1
RB2
RB3
RB4 34
47
46
45
44
43
42
41
40
39
38
37
36
35
33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
RA- 49 RA+ 50 RB- 51 RB+ 52 LVDD 53 RC- 54 RC+ 55 RCLK- 56 RCLK+ 57 LGND 58 RD- 59 RD+ 60 RERE+ PGND PVDD 61 62 63 64 RE2 11 RE3 10 RE1 12 RE0 13 RD6 14 RD5 15 GND 16 1 6 4 5 7 8 2 3 9
48
RB5
RB6 CLKOUT GND RC0 RC1 RC2 RC3 RC4 RC5 VDD RC6 RD0 RD1 RD2 RD3 RD4
RESERVE
RE5
RE4
R/F
GND
Fig.3 Pin diagram (Top view)
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VDD
RE6
PD
OE
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BU90R104
●Pin Description Pin Name RA+, RARB+, RBRC+, RCRD+, RDRE+, RERCLK+, RCLKRA6~RA0 RB6~RB0 RC6~RC0 RD6~RD0 RE6~RE0 RESERVE PD Pin No. 50,49 52,51 55,54 60,59 62,61 57,56 40,41,42,43, 45,46,47 32,33,34,35, 36,38,39 22,24,25,26, 27,28,29 14,15,17,18, 19,20,21 6,7,8,10, 11,12,13 2 3 I/O LVDS Input LVDS Input LVDS Input LVDS Input LVDS Input LVDS Input Output Output Output Output Output Input Input Reserved input must be “Low” for normal operation. Power down input for the internal system. H : Normal operation. L : Power down (All output are “Low”). Power down input for the data output driver. H : Output enable (Normal operation). L : Output disable (All outputs are “Hi-Z”). Select input pin for data output clock triggering edge. H : Output data is latched on rising edge. L : Output data is latched on falling edge. 3.3V output driver and digital core power supply pin. LVCMOS level clock output. LVCMOS data outputs. LVDS clock input LVDS data input + : Positive input of LVDS data differential pair. - : Negative input of LVDS data differential pair. Description
Technical Note
OE
4
Input
R/F VDD CLKOUT GND LVDD LGND PVDD PGND
5 9,23,37,48 31 1,16,30,44 53 58 64 63
Input Power Output Ground Power Ground Power Ground
GND pin for both data output driver cells and the digital cores. Power supply pin for LVDS inputs. Ground pin for LVDS inputs. Power supply pin for PLL core. Ground pin for PLL core.
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BU90R104
●Function Description PD 0 0 0 0 1 1 1 1
*1
Technical Note
R/F 0 0 1 1 0 0 1 1
OE 0 1 0 1 0 1 0 1
Data output *1 (Rxn) Hi-Z All fixed low Hi-Z All fixed low Hi-Z Data output Hi-Z Data output Hi-Z Fixed Low Hi-Z Fixed Low Hi-Z
Clock output
Output data is latched by falling edge of clock. Hi-Z Output data is latched by rising edge of clock
: Rxn x = A,B,C,D,E n = 0,1,2,3,4,5,6
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BU90R104
●Electrical Characteristics ■DC Characteristics ○LVCMOS DC character (VDD=3.0V~3.6V, Ta=-20℃~85℃) Limits Parameter Symbol Min. Typ. High Input voltage Low Input voltage High Output voltage Low Output voltage Input current VIH VIL VOH VOL IINC VDD×0.8 0.0 VDD-0.5 0.0 -
Technical Note
Max. VDD VDD×0.2 VDD 0.4 ±10
Unit V V V V µA
Conditions
IOH=-4mA (data) IOH=-8mA (clock) IOL=4mA (data) IOL=8mA (clock) 0V≦VIN≦VDD
○LVDS Receiver DC character (VDD=3.0V~3.6V, Ta=-20℃~85℃) Limits Parameter Symbol Min. Typ. Differential input High threshold Differential input Low threshold Input current
*1 Common Mode Voltage
Max. 100 ±25
Unit mV mV µA
Conditions VOC*1=1.2V VOC*1=1.2V VIN=2.4V / 0V VDD=3.6V
VTH VTL IINL
-100 -
-
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BU90R104
Technical Note
■Supply Current ○Supply current Parameter Receiver supply current (Gray Scale Pattern) Receiver supply current (Worst Case Pattern) Receiver power down supply current Symbol IRCCG IRCCW IRCCS Limits Min. 52 95 Max. 10 Unit mA mA µA Conditions fCLKOUT=90MHz fCLKOUT=90MHz PD=L, OE=L CL=8pF, VDD=3.3V CL=8pF, VDD=3.3V
Gray Scale Pattern CLKOUT Rx0 Rx1 Rx2 Rx3 Rx4 Rx5 Rx6 x=A,B,C,D,E Fig.4 Gray Scale Pattern Worst Case Pattern (Maximum power condition)
CLKOUT Rx0 Rx1 Rx2 Rx3 Rx4 Rx5 Rx6 x=A,B,C,D,E Fig.5 Worst Case Pattern
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BU90R104
Technical Note
■AC Characteristics ○Switching characteristics Parameter CLKOUT period CLKOUT "H" time CLKOUT "L" time LVCMOS data setup to CLKOUT LVCMOS data hold from CLKOUT LVCMOS data rise time LVCMOS data fall time Input data position 0 Input data position 1 Input data position 2 Symbol tRCP tRCH tRCL tRS tRH tTLH tTHL tRIP1 tRIP0 tRIP6 2 Limits Min. 8.93 0.5tRCP-1.4 0.23tRCP-1.0 -0.25
tRCIP -0.25 7
Typ. 0.5tRCP-1.0 0.5tRCP-1.0 1.0 1.0 0.0
tRCIP 7
Max. 125 2.0 2.0 +0.25
tRCIP +0.25 7
Unit ns ns ns ns ns ns ns ns ns
tRCIP -0.25 7
tRCIP -0.25 7 tRCIP -0.25 7
2 3 4 5 6
tRCIP 7
tRCIP 7 tRCIP 7
2 3 4 5 6
tRCIP +0.25 7
tRCIP +0.25 7 tRCIP +0.25 7
ns ns ns ns ns ms ns
Input data position 3 Input data position 4 Input data position 5 Input data position 6 Phase Locked Loop set time Clock input period
tRIP5 tRIP4 tRIP3 tRIP2 tRPLL tRCIP
3 4 5 6
tRCIP -0.25 7
tRCIP -0.25 7
tRCIP 7
tRCIP 7
tRCIP +0.25 7
tRCIP +0.25 7
8.93
-
10.0 125
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BU90R104
●AC Timing Diagrams ■LVCMOS
LVCMOS output CL=8pF
Technical Note
80% 20%
80% 20%
LVCMOS output load
tTLH
tTHL
tRCH
tRCL VDD/2
R/F=L VDD/2 R/F=H
CLKOUT
VDD/2
VDD/2
tRCP
tRS
tRH
Rxn
VDD/2
VDD/2
x=A,B,C,D,E n=0,1,2,3,4,5,6 Fig.6 LVCMOS output timing
■Phase-Locked Loop set time VDD 3.0V
RCLK +/-
PD
VDD/2
tRPLL
VDD/2
CLKOUT
Fig.7 Phase-Locked Loop set time
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BU90R104
●LVDS
Technical Note
Data, Clock Input Timing
Previous cycle Current cycle
Next cycle
tRCIP RCLK + (Differential) Vdiff=0V Vdiff=0V
RA+/-
RA3
RA2
RA1
RA0
RA6
RA5
RA4
RA3
RA2
RA1
RA0
RA6
RB+/-
RB3
RB2
RB1
RB0
RB6
RB5
RB4
RB3
RB2
RB1
RB0
RB6
RC+/-
RC3
RC2
RC1
RC0
RC6
RC5
RC4
RC3
RC2
RC1
RC0
RC6
RD+/-
RD3
RD2
RD1
RD0
RD6
RD5
RD4
RD3
RD2
RD1
RD0
RD6
RE+/-
RE3
RE2
RE1
RE0
RE6
RE5
RE4
RE3
RE2
RE1
RE0
RE6
Fig.8 LVDS data and clock input timing
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BU90R104
●LVDS Data, Clock Input and LVSMOS Output Timing
Technical Note
LVDS Input
RA+/RB+/RC+/RD+/RE+/RCLK+/-
RA6
RA5
RA4
RA3
RA2
RA1
RA0
RB6
RB5
RB4
RB3
RB2
RB1
RB0
RC6
RC5
RC4
RC3
RC2
RC1
RC0
RD6
RD5
RD4
RD3
RD2
RD1
RD0
RE6
RE5
RE4
RE3
RE2
RE1
RE0
LVCMOS Output
CLKOUT (R/F=L) CLKOUT (R/F=H) RA0~6 RB0~6 RC0~6 RD0~6 RE0~6 VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID
Fig.9 LVDS Data, Clock Input and LVCMOS Output Timing
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BU90R104
●About the Power On Reset
Technical Note
Power on reset is not mandatory for this device. (The PD pin should be set to high level when power on reset procedure is not used.)
VDD
PD
BU90R104
Fig.10 Terminal connection when power on reset is not used.
However, Power on reset procedure is strongly recommend for internal logic initialization by following two methods. ①The method of using CR circuit. ②The method of using external specific IC. It is recommend to do enough examination for target application.
VDD
schottky barrier diode
VDD 10KΩ
VDD PD VT+
220Ω 2.2µF
PD
Internal Reset td
Be careful of temperature ofthe capacitor especially over and again. B characteristic ceramics and function polymer aluminum electrolysis are recommended.
td is approximately equal to 20ms when the left RC coleus are applied.
Fig.11 Power on reset by external a CR circuit
VDD VDD
(Open drainoutput)
VDD 220KΩ PD VDD PD Detection voltage
Power on IC
VOUT 0.1μF GND B Characteristic ceramics. td Internal Reset
VT+
Fig.12 Power on reset by specific IC
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BU90R104
●10 LVDS Level Input & Output
Technical Note
Example: BU8254KVT : BU90R104 :
LVCMOS level input/Falling edge/LVDS normal(350mV) swing output LVCMOS level output/Falling edge
VDD
F.Bead *1
F.Bead *1
VDD
0.1uF 0.01uF CLKIN R4 R5 R6 R7 R8 R9 G4 G5 G6 G7 G8 G9 B4 B5 B6 B7 B8 B9 HSYNC VSYNC DE R2 R3 G2 G3 B2 B3 R0 R1 G0 G1 B0 B1
VDD GND
LVDS VDD 0.1uF 0.01uF 0.1uF 0.01uF
LVDD
VDD GND
0.1uF 0.01uF CLKOUT R4 R5 R6 R7 R8 R9 G4 G5 G6 G7 G8 G9 B4 B5 B6 B7 B8 B9 HSYNC VSYNC DE R2 R3 G2 G3 B2 B3 OPEN R0 R1 G0 G1 B0 B1 OPEN PD OE
CLKIN TA0 LVDS GND TA1 TA2 TA3 PLL VDD TA4 TA5 PLL GND TA6 TB0 TB1 TB2 TAN TB3 TB4 TAP TB5 TB6 TBN TC0 TC1 TBP TC2 TC3 TCN TC4 TC5 TCP TC6 TD0 TCLKN TD1 BU8254KVT TD2 TCLKP TD3 TD4 TDN TD5 TD6 TDP TE0 TE1 TEN TE2 TE3 TEP TE4 TE5 TE6 XRST VDD RS *2 R/F
LGND PVDD 0.1uF 0.01uF 0.1uF 0.01uF 100Ω PGND
RARA+ RBRB+ RCRC+ RCLKRCLK+ RDRD + RERE+
100Ω
100Ω
100Ω
100Ω
100Ω
CLKOUT RA0 RA1 RA2 RA3 RA4 RA5 RA6 RB0 RB1 RB2 RB3 RB4 RB5 RB6 RC0 RC1 RC2 RC3 RC4 RC5 RC6 RD0 B90R104 RD1 RD2 RD3 RD4 RD5 RD6 RE0 RE1 RE2 RE3 RE4 RE5 RE6 PD OE DK R/F
XRST 0.1uF
100Ωtwist pair Cable or PCB trace
PCB(Transmitter)
PCB(Receiver)
*1: Recommended Parts: F.Bead : BLM18A-Series (Murata Manufacturing Co.) *2 : If RS pin is tied to VDD, LVDS swing is 350 mV. If RS pin is tied to GND, LVDS swing is 200 mV.
Fig.13
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BU90R104
●10bit Small Swing Input & LVCMOS Level Output
Technical Note
Example: BU8254KVT : LVCMOS level input/Falling edge/LVDS normal(350mV) swing output BU90R104 : LVCMOS level output/Falling edge
VDD F.Bead *3 F.Bead *3 VDD
0.1uF 0.01uF CLKIN R4 R5 R6 R7 R8 R9 G4 G5 G6 G7 G8 G9 B4 B5 B6 B7 B8 B9 HSYNC VSYNC DE R2 R3 G2 G3 B2 B3 R0 R1 G0 G1 B0 B1
VDD GND
LVDS VDD 0.1uF 0.01uF 0.1uF 0.01uF
LVDD
VDD GND
0.1uF 0.01uF CLKOUT R4 R5 R6 R7 R8 R9 G4 G5 G6 G7 G8 G9 B4 B5 B6 B7 B8 B9 HSYNC VSYNC DE R2 R3 G2 G3 B2 B3 OPEN R0 R1 G0 G1 B0 B1 OPEN PD OE
CLKIN LVDS TA0 TA1 GND TA2 TA3 PLL VDD TA4 TA5 PLL GND TA6 TB0 TB1 TB2 TAN TB3 TB4 TAP TB5 TB6 TBN TC0 TC1 TBP TC2 TC3 TCN TC4 TC5 TCP TC6 TD0 TCLKN TD1 BU8254KVT TD2 TCLKP TD3 TD4 TDN TD5 TD6 TDP TE0 TE1 TEN TE2 TE3 TEP TE4 TE5 TE6 XRST *4 RS *4 R/F
LGND PVDD 0.1uF 0.01uF 0.1uF 0.01uF 100Ω PGND
RARA+ RBRB+ RCRC+ RCLKRCLK+ RDRD+ RERE+
100Ω
100Ω
100Ω
100Ω
100Ω
CLKOUT RA0 RA1 RA2 RA3 RA4 RA5 RA6 RB0 RB1 RB2 RB3 RB4 RB5 RB6 RC0 RC1 RC2 RC3 RC4 RC5 RC6 RD0 BU90R104 RD1 RD2 RD3 RD4 RD5 RD6 RE0 RE1 RE2 RE3 RE4 RE5 RE6 PD OE DK R/F
XRST
100Ωtwist pair Cable or PCB trace
PCB(Transmitter)
PCB(Receiver)
*3 Recommended Parts: F.Bead : BLM18A-Series (Murata Manufacturing Co.) *4 : RS pin acts as VREF input pin when input voltage is set to half of high level signal input. We recommend to locate by-pass condenser near the RS pin.
VDD R1 15k RS pin. R2 5.6k C1=0.1µF
Example for LVTTL(1.8V input):(R1,R2)=(15kΩ,5.6kΩ)
Fig.14
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BU90R104
●Notes for use 1) This chip is not designed to protect from radioactivity.
Technical Note
2) 3)
The chip is made strictly for the specific application or equipment. Then it is necessary that the unit is measured as need. This document may be used as strategic technical data which subjects to COCOM regulations.
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BU90R104
●Ordering part number
Technical Note
B
U
9
Part No. 90R104
0
R
1
0
4
-
E
2
Part No.
Packaging and forming specification E2: Embossed tape and reel
Package TQFP64V
TQFP64V
12.0±0.3 10.0±0.2
48 33
Tape Quantity
32
Embossed carrier tape (with dry pack) 1000pcs E2
direction the at left when you ( The on the leftishand1pin of product is thethe upperthe right hand hold ) reel and you pull out tape on
49
12.0±0.3
10.0±0.2
Direction of feed
1
16
0.125±0.1
1.0±0.1 0.1±0.1
0.5
64
17
0.5
0.2 ± 0.1
0.1
1pin (Unit : mm) Reel
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
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Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuelcontroller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
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R1120A