LVDS Interface ICs
27bit LVDS Transmitter
BU90T81
●General Description
The BU90T81 transmitter operates from 20MHz to
112MHz wide clock range, and 27bits data of parallel
LVCMOS level inputs(R/G/B24bits and VSYNC,HSYNC,DE)
are converted to four channels of LVDS data stream. Data is
transmitted seven times (7X) stream and reduce cable
number by 3(1/3) or less.
The BU90T81 operates from a single 1.8V supply for low
power. And the BU90T81 has low swing mode to be able to
expect further low power and low EMI .
●Key Specifications
▆Supply Voltage range
▆Operating frequency
▆Operating Temperature Range
▆Power Consumption
●Features
▆24bits data of parallel LVCMOS level inputs are
converted to four channels of LVDS data stream.
▆Support clock frequency from 20MHz up to 112MHz.
▆Low power 1.8V CMOS design
▆Power down mode
▆Clock edge selectable
▆Support 6bit/8bit mode selectable
▆Support reduced swing LVDS for low EMI.
▆Support LVDS Outputs pin reverse function
▆Support spread spectrum clock generator input
●Applications
▆Tablet
▆Netbook PC
▆Digital Picture Frame
●Packages
VBGA048W040
1.65 to 1.95 V
20 to 112MHz
–20 to 85℃
50mW(Typ)
4.00 ㎜×4.00 ㎜×0.90 ㎜
●Block Diagram
LVCMOS
Input
LVDS
CLKIIN
(20-112MHz)
PLL
Output
TCLK +/(20-112MHz)
8
R[7:0]
TA +/8
G[7:0]
TB +/-
8
B[7:0]
Parallel to Serial
HSYNC
TC +/-
VSYNC
DE
TD +/FLIP
6B8B
RS[1:0]
RF
XRST
Figure-1 Block Diagram
○Product structure:Silicon monolithic integrated circuit
○This product is not designed protection against radioactive rays
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Datasheet
BU90T81
●Pin Configuration
Top view
1
2
3
4
5
6
7
A
G[5]
G[7]
R[1]
R[3]
R[5]
R[6]
R[7]
B
-
G[6]
R[0]
R[2]
R[4]
TA-
TA+
C
G[3]
G[4]
GND
RS[1] RS[0]
TB-
TB+
D
G[1]
G[2]
RF
VDD
VDD
TC-
TC+
E
G[0]
B[7]
FLIP
6B8B
GND TCLK- TCLK+
F
B[6]
B[5]
B[2]
B[0]
G
B[4]
B[3]
B[1] HSYNC VSYNC CLKIN XRST
DE
TD-
TD+
48pin VBGA
Figure-2 Pin Diagram (Top View)
●Pin Description
Pin Name
TA+/-, TB+/-,
TC+/-,TD+/TCLK+/-
Pin No.
Type
B7,B6,C7,C6,D7,D6,F7,F6
LVDS
OUT
E7,6
R[7:0]
A7,A6,A5,B5,A4,B4,A3,B3
G[7:0]
A2,B2,A1,C2,C1,D2,D1,E1
B[7:0]
HSYNC,VSYNC,
DE
CLKIN
E2,F1,F2,G1,G2,F3,G3,F4
XRST
G7
RF
D3
CMOS
IN
Descriptions
LVDS Data out
LVDS Clock out
Pixel and control data inputs
G4,G5,F5
G6
Clock input
Power Down
H:Normal operation
L:Power down ( all LVDS output signal are Hi-z)
Input CLK Triggering Edge Select.
H:Rising edge
L:Falling edge
LVDS swing mode select
RS[1:0]
C3,C5
CMOS
IN
RS0
L
H
L
H
LVDS swing
TYP=160mV
TYP=200mV
TYP=350mV
Reserved
6bit/8bit mode select
H : 6bit mode(FLIP=L TD+/- is Hiz)
(FLIP=H TA+/- is Hiz)
L : 8bit mode
LVDS output pin reverse select.
H : Reverse
L : Normal
6B8B
E4
FLIP
E3
VDD
D4,D5
POWER
GND
C3,E5
GND
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L
H
H
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1.8V Power supply
Ground Pins
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Datasheet
BU90T81
●Absolute Maximum Ratings
Rating
Parameter
Symbol
Units
Min
Max
Supply Voltage
VDD
-0.3
2.5
V
Input Voltage
VIN
-0.3
VDD+0.3
V
Output Voltage
VOUT
-0.3
VDD+0.3
V
Storage Temperature Range
Tstg
-55
125
℃
●Operating Ratings
Rating
Units
Symbol
Parameter
Min
Typ
Max
Supply Voltage
VDD
1.65
1.8
1.95
V
Operating Temperature Range
Topr
-20
-
85
℃
Operating frequency
Fmax
20
-
112
MHz
Conditions
●Package Power
Package
Power Dissipation (mW)
De-rating (mW/℃)*1
VBGA048W040
800*1
8.0*1
*1:Package power when mounting on the PCB board.
The size of PCB board
The material of PCB board
: 114.3×76.2×1.6(mm3)
: The FR4 glass epoxy board.
●DC characteristics
Table 1 : LVCMOS DC Specifications(VDD=1.65V~1.95V, Ta=-20℃~+85℃)
Rating
Symbol
Parameter
Units
Min
Typ
Max
VIH
High Level Input Voltage
VDD×0.7
-
VDD
V
VIL
Low Level Input Voltage
GND
-
VDD×0.3
V
IINC
Input Current
-10
-
+10
μA
Conditions
0V≤VIN≤VDD
Table2: LVDS Transmitter DC Specifications(VDD=1.65V~1.95V, Ta=-20℃~+85℃)
Rating
Symbol
VOD
Parameter
Differential Output Voltage
Units
Min
Typ
Max
250
350
450
mV
130
200
270
mV
110
160
210
mV
Conditions
RS[1:0]= HL
RL=100Ω
RS[1:0]= LH
RS[1:0]= LL
ΔVOD
Change in VOD between
complementary output states
-
-
35
mV
VOC
Common Mode Voltage
1.125
1.25
1.375
V
ΔVOC
Change in VOC between
complementary output states
-
-
35
mV
IOS
Output Short Circuit Current
-90
-
-
mA
VOUT=0V
IOZ
Output TRI-STATE Current
-10
-
+10
μA
XRST=0V,
VOUT=0V to VDD
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Datasheet
BU90T81
●AC characteristics
Table 3 : Switching Characteristics(VDD=1.8V, Ta=25℃ RL=100Ω CL=5pF RS[1:0]=HL)
Parameter
Symbol
Min
Typ
Max
Units
tTCP
CLK OUT Period
8.93
-
50
ns
tTCIT
CLK IN Transition time
-
-
5.0
ns
tTCH
CLK IN High Time
0.35tTCP
0.5tTCP
0.65tTCP
ns
tTCL
CLK IN Low Time
0.35tTCP
0.5tTCP
0.65tTCP
ns
tTS
LVSMOS Data Set up to CLK IN
2.5
-
-
ns
tTH
LVCMOS Data Hold from CLK IN
0
-
-
ns
LVDS Transition Time
-
0.6
1.5
ns
CLKOUT=112MHz
-
-
200
ps
CLKOUT=112MHz
-
-
200
ps
tLVT
Differential Output
Set up Time
Differential Output
Hold time
TTSUP
TTHLD
tTOP6
Output Data Position 6
tTOP5
Output Data Position 5
tTOP4
Output Data Position 4
tTOP3
Output Data Position 3
tTOP2
Output Data Position 2
tTOP1
Output Data Position 1
tTOP0
Output Data Position 0
tTPLL
Phase Locked Loop Set Time
tTCP
- TTHLD
7
tTCP
- TTHLD
3
7
tTCP
- TTHLD
4
7
tTCP
5
- TTHLD
7
tTCP
- TTHLD
6
7
tTCP
- TTHLD
7
7
tTCP
8
- TTHLD
7
2
tTCP
7
tTCP
3
7
tTCP
4
7
tTCP
5
7
tTCP
6
7
tTCP
7
7
tTCP
8
7
tTCP
+ TTSUP
7
tTCP
3
+ TTSUP
7
tTCP
4
+ TTSUP
7
tTCP
5
+ TTSUP
7
tTCP
6
+ TTSUP
7
tTCP
7
+ TTSUP
7
tTCP
8
+ TTSUP
7
2
-
2
-
10
ns
ns
ns
ns
ns
ns
ns
ms
●AC Timing Diagrams
LVCMOS Input
tTCP
CLKIN
LVCMOS Input
90%
t TCH
90%
RF=L
10%
CLKIN
10%
V DD /2
V DD/2
tTCL
tTCIT
tTCIT
V DD/2
tTS
RF=H
tTH
LVDS Output
Vdiff=(Tx+)-(Tx-)
DATA_IN
Tx+
Vdiff
CL
RL
80%
V DD/2
80%
20%
V DD/2
tTCD
TCLK+
20%
V OC
Tx-
TCLK-
LVDS Output Load
tLVT
t LVT
x=A,B,C.D,CLK
DATA_IN= R[7:0], G[7:0], B[7:0], VSYNC, HSYNC, DE
Figure-3 LVCMOS Input AC Timing Diagrams
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BU90T81
TCLK OUT
(Differential)
TA+/-
G[2]
R[7]
R[6]
R[5]
R[4]
R[3]
R[2]
TB+/-
B[3]
B[2]
G[7] G[6] G[5] G[4] G[3]
TC+/-
DE
VSY
NC
HSY
NC
B[7]
B[6]
B[5]
B[4]
TD+/-
L
B[1]
B[0]
G[1] G[0]
R[1]
R[0]
Previous Cycle
tTOP1
tTOP0
tTOP6
tTOP5
tTOP4
tTOP3
tTOP2
Next Cycle
Figure-4 LVDS Output AC Timing Diagrams
●Phase Locked Loop Set Time
1.65
V DD
V DD
V DD×0.7
XRST
tTPLL
CLKIN
V diff=0V
TCLK+/-
Figure-5 Phase Locked Loop Set Time
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Datasheet
BU90T81
●Supply Current
Table 4: Supply Current (6B8B = L)
Symbol
ITCCG
ITCCW
ITCCS
Parameter
Min
Rating
Typ
Max
-
30.4
-
mA
RL=100Ω,CL=5pF
VDD=1.8V,RS[1:0]=HL
Gray Scale Pattern
f=85MHz
-
22.5
-
mA
RL=100Ω,CL=5pF
VDD=1.8V,RS[1:0]=LH
Gray Scale Pattern
f=85MHz
-
20.4
-
mA
RL=100Ω,CL=5pF
VDD=1.8V, RS[1:0]=LL
Gray Scale Pattern
f=85MHz
-
32.4
-
mA
RL=100Ω,CL=5pF
VDD=1.8V, RS[1:0]=HL
Worst case Pattern
f=85MHz
-
24.5
-
mA
RL=100Ω,CL=5pF
VDD=1.8V, RS[1:0]=LH
Worst case Pattern
f=85MHz
-
22.4
-
mA
RL=100Ω,CL=5pF
VDD=1.8V, RS[1:0]=LL
Worst case Pattern
f=85MHz
-
-
10
μA
Transmitter Supply
Current
Transmitter Supply
Current
Transmitter Power Down
Supply Current
Units
Conditions
XRST=L
Gray Scale Pattern
CLKIN
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
D=R,G,B
Figure -6 Gray Scale Pattern
Worst Case Pattern (Maximum Power condition)
CLKIN
D[0]
D[1]
D[2]
D[3]
D[4]
[
D[5]
D[6]
D[7]
D=R,G,B
Figure -7 Worst Case Pattern
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Datasheet
BU90T81
●LVDS Data Output Table for Function of FLIP pin
Table 5: LVDS Data Output Pin Name
Output Pin Names
Pin No
FLIP=L
FLIP=H
B7
TA+
TD-
B6
TA-
TD+
C7
TB+
TCLK-
C6
TB-
TCLK+
D7
D6
E7
TC+
TCTCLK+
TCTC+
TB-
E6
TCLK-
TB+
F7
F6
TD+
TD-
TATA+
TA-
TA+
TD+ TD-
TB-
TB+
TCLK+ TCLK-
TC-
TC+
TCLK- TCLK+
TD-
TD+
FLIP=L
TC+
TC-
TB+
TB-
TA+
TA-
FLIP=H
●LVCMOS Data Inputs Pixel Map Table
Table 6: LVCMOS Data Inputs Pixel Map Table
TFT Panel Data
LSB
24Bit
18Bit
R0
-
BU90T81 Input
R0
R1
-
R0
R2
R0
R1
R3
R1
R2
R4
R2
R3
R5
R3
R4
R6
R4
R5
MSB
R7
R5
R6
LSB
G0
-
R7
G1
-
G0
G2
G0
G1
G3
G1
G2
G4
G2
G3
G5
G3
G4
G6
G4
G5
MSB
G7
G5
G6
LSB
B0
-
G7
MSB
B1
-
B0
B2
B0
B1
B3
B1
B2
B4
B2
B3
B5
B3
B4
B6
B4
B5
B7
B5
B6
VSYNC
VSYNC
B7
HSYNC
HSYNC
HSYNC
DE
DE
DE
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Datasheet
BU90T81
●LVDS Output Data Mapping
TCLK OUT
(Differential)
TA+/-
G[2]
R[7]
R[6]
R[5]
R[4]
R[3]
R[2]
TB+/-
B[3]
B[2]
G[7]
G[6]
G[5]
G[4]
G[3]
TC+/-
DE
VSY
NC
HSY
NC
B[7]
B[6]
B[5]
B[4]
TD+/-
L
B[1]
B[0]
G[1]
G[0]
R[1]
R[0]
Figure-8 LVDS output mapping (6B8B=L, FLIP=L)
TCLK OUT
(Differential)
TA+/-
G[2]
R[7]
R[6]
TB+/-
B[3]
B[2]
G[7] G[6] G[5] G[4] G[3]
TC+/-
DE
VSY
NC
HSY
NC
TD+/-
R[5]
B[7]
R[4]
B[6]
R[3]
B[5]
R[2]
B[4]
Hiz
Figure-9 LVDS output mapping (6B8B=H, FLIP=L)
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Datasheet
BU90T81
●Typical Application Circuit ( 24bit mode)
Example
BU90T81: LVCMOS Data Input /rising edge/200mV swing output/normal output mapping
Figure-10 Application Circuit (24bit mode)
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Datasheet
BU90T81
●Typical Application Circuit ( 18bit mode)
Example
BU90T81: LVCMOS Data Input /rising edge/200mV swing output/normal output mapping
Figure-11 Application Circuit (18bit mode)
●Status of this document
The Japanese version of this document is formal specification. A customer may use this translation
version only for a reference to help reading the formal version.
If there are any differences in translation version of this document formal version takes priority
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Datasheet
Notice
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(Note 1)
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intend to use our Products in devices requiring extremely high reliability (such as medical equipment
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De-rate Power Dissipation (Pd) depending on Ambient temperature (Ta). When used in sealed area, confirm the actual
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Confirm that operation temperature is within the specified range described in the product specification.
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Precaution for Mounting / Circuit board design
1.
When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
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2.
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For details, please refer to ROHM Mounting specification
Notice - GE
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Datasheet
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Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
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4.
The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice - GE
© 2014 ROHM Co., Ltd. All rights reserved.
Rev.002
Datasheet
General Precaution
1. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents.
ROHM shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this docume nt is current as of the issuing date and subj ect to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the la test information with a ROHM sale s
representative.
3.
The information contained in this doc ument is provi ded on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate an d/or error-free. ROHM shall not be in an y way responsible or
liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccur acy or errors of or
concerning such information.
Notice – WE
© 2014 ROHM Co., Ltd. All rights reserved.
Rev.001