Datasheet
Low Duty LCD Segment Driver
for Automotive application
BU91520KV-M
MAX 276 Segments (69SEG × 4COM)
General Description
Key Specifications
■
■
■
■
■
■
The BU91520KV-M is 1/4 or 1/3 Duty General-purpose
LCD driver. The BU91520KV-M can drive up to 276 LCD
Segments directly. The BU91520KV-M can also control
up to 6 General-purpose output pins / 6 PWM output pins.
These products also incorporate a key scan circuit that
accepts input from up to 30 keys to reduce printed circuit
board wiring.
Supply Voltage Range:
+2.7V to +6.0V
Operating Temperature Range:
-40°C to +105°C
Max Segments:
276 Segments
Display Duty
1/3, 1/4 Selectable
Bias:
1/2, 1/3 Bias
Interface:
3wire Serial Interface
Special Characteristics
Features
■ Electrostatic Discharge Voltage(HBM):
■ Latch-up Current:
AEC-Q100 Qualified (Note 1)
Key Input Function for up to 30 Keys (A key scan is
performed only when a key is pressed.)
Either 1/4 or 1/3 Duty can be Selected with the Serial
Control Data.
1/4 Duty Drive: up to 276 Segments
1/3 Duty Drive: up to 207 Segments
Selectable Display Frame Frequency for Common
and Segment Output Waveforms.
Configurable Output Pin to Segment Output / PWM
Output / General-purpose Output.(Max 6 Pins)
Built-in OSC Circuit
The INHb Pin can Force the Display to the off State
Integrated Voltage Detect Type Power on Reset
(VDET) circuit
No External Component
Low Power Consumption Design
Supports Line and Frame Inversion
Package
±2000V
±100mA
W(Typ) × D(Typ) × H(Max)
VQFP80
14.00mm x 14.00mm x 1.60mm
(Note 1) Grade 2
Applications
Car Audio, Home Electrical Appliance,
Meter Equipment etc.
Typical Application Circuit
Key matrix
(P1/G1)
(P6/G6)
KS1/S56
|
KS6/S61
+5V
KI1/S62
|
KI5/S66
(General purpose/PWM pins)
(For use control of backlight)
COM1
COM2
COM3
COM4
S1/P1/G1
S2/P2/G2
VDD
(Note 2)
S6/P6/G6
S7
INHb
From
Controller
SCE
SCL
SDI
To Controller
LCD Panel
(Up to 276
Segments)
SDO
S66
S67
S68
OSC/S69
(Note2) Insert capacitors between VDD and VSS C≥0.1µF
Figure 1. Typical Application Circuit
〇Product structure : Silicon monolithic integrated circuit
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〇This product has no designed protection against radioactive rays
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BU91520KV-M
COMMON Driver
---
S1/P1/G1
S7
---
S6/P6/G6
S55
S67
S68
COM1
COM2
COM3
COM4
Block Diagram
SEGMENT Driver
INHb
Clock / Timing
Generator
OSC/
S69
Control Register
SCE
PWM Register
Shift Register
SCL
Serial
Interface
SDI
LCD v oltage
Generator
SDO
KEY Buffer
VLCD
VDD
VLCD1
VDET
KEY SCAN
VLCD2
KS1/S56
KS2/S57
KS3/S58
KS4/S59
KS5/S60
KS6/S61
KI1/S62
KI2/S63
KI3/S64
KI4/S65
KI5/S66
VSS
Figure 2. Block Diagram
S43
41
S44
S45
S46
S47
S48
S49
S50
S51
S52
S53
S54
S55
KS1 / S56
KS2 / S57
KS3 / S58
KS4 / S59
KS5 / S60
KI1 / S62
60
KS6 / S61
Pin Configuration
61
40
KI2 / S63
S42
KI3 / S64
S41
KI4 / S65
S40
KI5 / S66
S39
COM1
S38
COM2
S37
COM3
S36
COM4
S35
S67
S34
VDD
S33
S68
S32
SDO
S31
VSS
S30
OSC / S69
S29
INHb
S28
SCE
S27
SCL
S26
SDI
S25
S1 / P1 / G1
S24
S2 / P2 / G2
S23
21
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S9
S10
S8
S7
S6 / P6 / G6
S5 / P5 / G5
S4 / P4 / G4
S3 / P3 / G3
1
20
80
Figure 3. Pin Configuration (TOP VIEW)
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BU91520KV-M
Absolute Maximum Ratings (VSS = 0.0V)
Parameter
Maximum Supply Voltage
Input Voltage
Allowable Loss
Operating Temperature
Storage Temperature
Symbol
VDD
VIN1
VIN2
Pd
Topr
Tstg
Conditions
VDD
SCE, SCL, SDI, INHb, OSC
KI1 to KI5
-
Rating
-0.3 to +7.0
-0.3 to +7.0
-0.3 to +7.0
1.20(Note)
-40 to +105
-55 to +125
Unit
V
V
V
W
°C
°C
(Note) Derate by 12.0mW/°C when operating above Ta=25°C (when mounted in ROHM’s standard board).
(Board size: 70mm×70mm×1.6mm material: FR4 board copper foil: land pattern only)
Caution1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open
circuit between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case
the IC is operated over the absolute maximum ratings.
Caution2: Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in deterioration of the
properties of the chip. In case of exceeding this absolute maximum rating, design a PCB boards with power dissipation taken into consideration by
increasing board size and copper area so as not to exceed the maximum junction temperature rating.
Recommended Operating Conditions (Ta = -40°C to +105°C, VSS = 0V)
Parameter
Supply Voltage
Symbol
VDD
Conditions
-
Min
2.7
Rating
Typ
5.0
Max
6.0
Limit
Typ
0.03VDD
0.1VDD
Max
-
Unit
V
Electrical Characteristics (Ta = -40°C to +105°C, VDD = 2.7V to 6.0V, VSS = 0V)
Parameter
Symbol
Pin
Conditions
Unit
Hysteresis
VH1
VH2
SCE, SCL, SDI, INHb, OSC KI1 to KI5
-
Min
-
Power-on Detection
Voltage
VDET
VDD
-
1.4
1.8
2.2
V
“H” Level Input Voltage
VIH1
VIH2
VIH3
4.0V ≤ VDD ≤ 6.0V
2.7V ≤ VDD < 4.0V
-
0.4VDD
0.8VDD
0.7VDD
-
VDD
VDD
VDD
V
“L” Level Input Voltage
VIL1
0
-
0.2VDD
V
Input Floating Voltage
VIF
RPD
IOFFH
IIH1
IIL1
VOH1
VOH2
VOH3
VOH4
VOL1
VOL2
VOL3
VOL4
VOL5
VMID1
SCE, SCL, SDI, INHb, OSC
SCE, SCL, SDI, INHb, OSC
KI1 to KI5
SCE, SCL, SDI, INHb, OSC
KI1 to KI5
KI1 to KI5
KI1 to KI5
SDO
SCE, SCL, SDI, INHb, OSC
SCE, SCL, SDI, INHb, OSC
S1 to S69
COM1 to COM4
P1/G1 to P6/G6
KS1 to KS6
S1 to S69
COM1 to COM4
P1/G1 to P6/G6
KS1 to KS6
SDO
S1 to S69
V
kΩ
µA
µA
µA
VMID2
COM1 to COM4
VMID3
S1 to S69
VMID4
S1 to S69
VMID5
COM1 to COM4
VMID6
COM1 to COM4
0.05VDD
50
100
250
6.0
5.0
-5.0
VDD-0.9
VDD-0.9
VDD-0.9
VDD-1.0 VDD-0.5 VDD-0.2
0.9
0.9
0.9
0.2
0.5
1.5
0.1
0.5
1/2VDD
1/2VDD
-0.9
+0.9
1/2VDD
1/2VDD
-0.9
+0.9
2/3VDD
2/3VDD
-0.9
+0.9
1/3VDD
1/3VDD
-0.9
+0.9
2/3VDD
2/3VDD
-0.9
+0.9
1/3VDD
1/3VDD
-0.9
+0.9
15
Pull-down Resistance
Output Off Leakage
“H” Level Input Current
Current
“L” Level Input Current
“H” Level
Output Voltage
“L” Level
Output Voltage
Middle Level
Output Voltage
IDD1
VDD
IDD2
VDD
Current Consumption
IDD3
VDD
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VDD = 5.0V
VO = 6.0V
VI = 5.5V
VI = 0V
IO = -20µA
IO = -100µA
IO = -1mA
IO = -500µA
IO = 20µA
IO = 100µA
IO = 1mA
IO = 25µA
IO = 1mA
1/2 Bias
IO =Bias
±20µA
1/2
IO = ±100µA
1/3 Bias
IO = ±20µA
1/3 Bias
IO = ±20µA
1/3 Bias
IO = ±100µA
1/3 Bias
IO = ±100µA
Power-saving mode
VDD = 5.0V
Output open ,1/2 Bias
Frame frequency =
80Hz
VDD = 5.0V
Output open ,1/3 Bias
Frame frequency =
80Hz
-
85
V
V
V
V
V
170
µA
-
110
210
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BU91520KV-M
Oscillation Characteristics(Ta = -40°C to +105°C, VDD = 2.7V to 6.0V, VSS = 0V)
Parameter
Symbol
Oscillator Frequency 1
Oscillator Frequency 2
External Clock Frequency
fOSC1
fOSC2
External Clock Rise Time
External Clock Fall Time
External Clock Duty
tr
tf
(Note 1)
Pin
Conditions
VDD = 2.7V to 6.0V
VDD = 5V
-
fOSC3
OSC
External clock mode (OC=1)
tDTY
Min
300
510
Limit
Typ
600
Max
720
690
30
-
1000
kHz
30
160
160
50
70
ns
ns
%
Limit
Typ
-
Max
-
Unit
kHz
kHz
(Note 1 ) Frame frequency is decided by external clock and dividing ratio of FC0, FC1, FC2 setting.
[Reference Data]
700
VDD=6.0V
650
VDD=5.0V
600
fosc[kHz]
550
500
VDD=3.3V
VDD=2.7V
450
400
350
300
-40
-20
0
20
40
60
80
Temperature[°C]
Figure 4. Oscillator Frequency Typical Temperature Characteristics
MPU Interface Characteristics (Ta = -40°C to +105°C, VDD = 2.7V to 6.0V, VSS = 0V)
Parameter
Data Setup Time
Data Hold Time
SCE Wait Time
SCE Setup Time
SCE Hold Time
Clock Cycle Time
High-level Clock Pulse
Width
Low-Level Clock Pulse
Width (Write)
Low-Level Clock Pulse
Width (Read)
Symbol
Pin
Conditions
Unit
SCL, SDI
SCL, SDI
SCE, SCL
SCE, SCL
SCE, SCL
SCL
-
Min
120
120
120
120
120
320
tCHW
SCL
-
120
-
-
ns
tCLWW
SCL
-
120
-
-
ns
tCLWR
SCL
RPU=4.7kΩ,CL=10pF(Note 2 )
1.6
-
-
µs
-
-
160
-
ns
-
-
160
-
ns
10
-
-
1.5
1.5
µs
µs
µs
tDS
tDH
tCP
tCS
tCH
tCCYC
Rise Time
tr
Fall Time
tf
INHb Switching Time
SDO Output Delay Time
SDO Rise Time
tC
tDC
tDR
SCE, SCL,
SDI
SCE, SCL,
SDI
INHb, SCE
SDO
SDO
RPU=4.7kΩ, CL=10pF(Note 2 )
RPU=4.7kΩ, CL=10pF(Note 2 )
ns
ns
ns
ns
ns
ns
(Note 2 ) Since SDO is an open-drain output, “tDC” and “tDR” depend on the resistance of the pull-up resistor RPU and the load capacitance CL.
RPU: 1kΩ≤RPU≤10kΩ is recommended.
CL: A parasitic capacitance to VSS in an application circuit. Any component is not necessary to be attached.
Power supply for I/O level
RPU
SDO
Host
CL
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MPU Interface Characteristics – continued
1. When SCL is stopped at the low level
VIH1
SCE
VIL1
tCCYC
tCLWW
tCHW
tCLWR
VIH1
SCL
VIL1
tr
tCH
tCS
tf
VIH1
SDI
VIL1
tDS
tDH
SDO
VOL5
tDC
tDR
2. When SCL is stopped at the high level
VIH1
SCE
VIL1
tCCYC
tCHW
tCLWW
SCL
tCLWR
VIH1
VIL1
SDI
tCP
tr
tf
tCH
VIH1
VIL1
tDS
tDH
SDO
VOL5
tDR
tDC
Figure 5. Serial Interface Timing
Pin Description
Pin
Pin No.
S1/P1/G1 to
S6/P6/G6
79,80,
1 to 4,
S7 to S55
S67,S68
5 to 53,
69,71
KS1/S56 to
KS6/S61
54 to 59
KI1/S62 to
KI5/S66
60 to 64
COM1 to COM4
65 to 68
OSC/S69
74
SCE
SCL
SDI
76
77
78
SDO
72
Function
Segment output for displaying the display data transferred by
serial data input. The S1/P1/G1 to S6/P6/G6 pins can also
be used as General-purpose / PWM outputs when so set up
by the control data.
Segment output for displaying the display data transferred by
serial data input.
Key scan outputs
Although normal key scan timing lines require diodes to be
inserted in the timing lines to prevent shorts, since these
outputs are unbalanced CMOS transistor outputs, these
outputs will not be damaged by shorting when these outputs
are used to form a key matrix. The KS1/S56 to KS6/S61 pins
can be used as segment outputs when so specified by the
control data.
Key scan inputs
These pins have built-in pull-down resistors.
The KI1/S62 to KI5/S66 pins can be used as segment
outputs when so specified by the control data.
Common driver output pins. The frame frequency is fo[Hz].
Segment output for displaying the display data transferred by
serial data input.
The pin OSC/S69 can be used as external clock input pin
when set up by the control data.
Serial data transfer inputs. Must be connected to the
controller.
SCE: Chip enable
SCL: Clock for serial data transfer.
SDI: Transfer data
Output data
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Active
I/O
Handling
when
unused
-
O
OPEN
-
O
OPEN
-
O
OPEN
I
VSS
O
OPEN
O
OPEN
I
VSS
O
OPEN
H
↑
-
I
I
I
VSS
VSS
VSS
-
O
OPEN
-
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BU91520KV-M
Pin Description – continued
Pin No.
Pin
INHb(Note)
75
VDD
70
VSS
73
Function
Display off control input.
When INHb=low (VSS), Display forced off
S1/P1/G1 to S6/P6/G6=low (VSS)
S7 to S69=low (VSS)
COM1 to COM4=low (VSS)
Stop the LCD drive bias voltage generation divider
resistors.
Stop the internal oscillation circuit.
When INHb=high (VDD), Display on
However, serial data transfer is possible when the display is
forced off.
Power supply pin.
A supply voltage of 2.7V to 6.0V must be applied to this pin.
Power supply pin. Must be connected to Ground.
Active
I/O
Handling
when
unused
L
I
VDD
-
-
-
-
-
-
(Note) Regarding the details of the INHb pin and the control of each output, refer to “INHb Pin and Display Control”
IO Equivalence Circuit
VDD
VDD
SCE, SDI, SCL,INHb
VSS
VSS
VDD
VDD
OSC/S69
S7 to S55, S67, S68
COM1 to COM4
VSS
VSS
VDD
KI1/S62 to KI5/S66
VDD
S1/P1/G1 to
S6/P6/G6,
KS1/S56 to KS6/S61
VSS
VSS
VDD
SDO
VSS
Figure 6. I/O Equivalence Circuit
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BU91520KV-M
Serial Data Transfer Formats
1. 1/4 Duty
(1) When SCL is stopped at the low level
SCE
SCL
L
SDI
0
1
0
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
D1
Device Code
D2
D71
D72
0
0
0
0
0
KM0
KM1
KM2
P0
P1
P2
Display Data
8bit
0
1
0
0
0
0
1
0
B1
B2
B3
A0
A1
A2
A3
D73
D74
DR
DT
FC0
FC1
D143
D144
D145
D146
1
0
0
0
0
1
0
B2
B3
A0
A1
A2
A3
D157
Device Code
D158
D147
D148
D149
D150
D151
D152
0
1
0
0
0
0
1
0
B1
B2
B3
A0
A1
A2
A3
Device Code
D217
D216
D218
0
0
0
0
0
D276
0
0
0
0
0
Display Data
8bit
BU2
0
D153
D154
D155
D156
PG1
PG2
PG3
PG4
PG5
PG6
PF0
PF1
PF2
PF3
0
0
W10
60bit
0
0
W40
W11
W16
W17
0
0
W20
W21
W26
W27
1
DD
10bit
60bit
B0
BU1
Control Data
Display Data
8bit
BU0
DD
84bit
B1
SC
2bit
Display Data
8bit
0
OC
22bit
Device Code
B0
FC2
Control Data
72bit
B0
FL
2bit
W30
W31
W36
W37
1
0
Control Data
DD
34bit
2bit
W41
W46
W47
W50
W51
W56
W57
W60
W61
W66
W67
1
1
Control Data
DD
34bit
2bit
Figure 7. 3-SPI Data Transfer Format
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Serial Data Transfer Formats – continued
(2) When SCL is stopped at the high level
SCE
SCL
L
SDI
0
1
0
0
0
0
1
B0
B1
B2
B3
A0
A1
A2
0
D1
D2
D71
D72
0
0
Device Code
0
0
KM0
KM1
KM2
P0
P1
P2
Display Data
8bit
0
1
0
0
0
0
1
B1
B2
B3
A0
A1
A2
FL
DR
DT
FC0
FC1
0
0
0
0
1
B2
B3
A0
A1
A2
0
D73
0
D157
D74
D143
D144
D145
D146
D147
D148
D149
D150
D151
D152
D153
D154
D155
D156
PG1
PG2
PG3
PG4
1
0
0
0
0
1
B2
B3
A0
A1
A2
Device Code
PG5
PG6
PF0
PF1
PF2
PF3
0
0
1
D158
D216
0
0
0
0
DD
10bit
0
0
0
W10
60bit
B1
0
Control Data
Display Data
8bit
0
BU2
W11
W16
W17
W20
W21
W26
W27
2bit
W30
W31
W36
W37
1
0
A3
Device Code
B0
BU1
DD
84bit
1
BU0
2bit
Display Data
B1
SC
A3
8bit
0
OC
22bit
Device Code
B0
FC2
Control Data
72bit
B0
8bit
0
A3
0
D217
D218
D276
0
0
0
0
0
0
0
W40
Control Data
DD
34bit
2bit
W41
W46
W47
W50
W51
W56
W57
W60
W61
W66
W67
1
1
A3
Display Data
60bit
Control Data
DD
34bit
2bit
Figure 8. 3-SPI Data Transfer Format
Device code ----------------------------- “42H”
D1 to D276 ------------------------------ Display data
KM0 to KM2 ----------------------------- Key Scan output pin / Segment output pin switching control data
P0 to P2 ---------------------------------- Segment / PWM / General-purpose output pin switching control data
FL ------------------------------------------ Line Inversion or Frame Inversion switching control data
DR ----------------------------------------- 1/3 Bias drive or 1/2 Bias drive switching control data
DT ----------------------------------------- 1/4 Duty drive or 1/3 Duty drive switching control data
FC0 to FC2 ------------------------------ Common / Segment output waveform frame frequency switching control data
OC ----------------------------------------- Internal oscillator operating mode / External clock operating mode switching control data
SC ----------------------------------------- Segment on/off control data
BU0 to BU2 ------------------------------ Normal mode / power-saving mode control data
PG1 to PG6 ------------------------------ PWM / General-purpose output control data
PF0 to PF3 ------------------------------- PWM output waveform frame frequency control data
Wn0 to Wn7 (n=1 to 6) ---------------- PWM output waveform duty control data
DD------------------------------------------- Direction data
When it is coincident with device code, BU91520KV-M capture display data and control data at falling edge of SCE.
So, please transfer the bit number of send display data and control data as specified number in the above figure.
Specified number of bits is 104bit (Device code: 8bit, Display data and Control data: 94bit, DD: 2bit).
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BU91520KV-M
Serial Data Transfer Formats – continued
2. 1/3 Duty
(1) When SCL is stopped at the low level
SCE
SCL
L
SDI
0
1
0
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
D1
Device Code
D2
D71
D72
0
0
0
0
0
KM0
KM1
KM2
P0
P1
P2
Display Data
8bit
FL
0
1
0
0
0
0
1
0
B1
B2
B3
A0
A1
A2
A3
D73
D74
DT
FC0
FC1
D143
D144
D145
D146
1
0
0
0
0
1
0
B2
B3
A0
A1
A2
A3
D157
Device Code
D158
D147
D148
D149
D150
D151
D152
0
1
0
0
0
0
1
0
B1
B2
B3
A0
A1
A2
A3
0
D207
0
BU2
0
D153
D154
D155
D156
PG1
PG2
PG3
PG4
0
0
0
0
0
0
0
0
0
PG5
PG6
PF0
PF1
PF2
PF3
0
0
0
W10
0
0
Device Code
8bit
0
W40
W11
W16
W17
0
0
W20
W21
W26
W27
1
DD
10bit
51bit
B0
BU1
Control Data
Display Data
8bit
BU0
DD
84bit
B1
SC
2bit
Display Data
8bit
0
OC
22bit
Device Code
B0
FC2
Control Data
72bit
B0
DR
2bit
W30
W31
W36
W37
1
0
Control Data
DD
39bit
2bit
W41
W46
W47
W50
W51
W56
W57
W60
W61
W66
W67
1
1
Control Data
DD
94bit
2bit
Figure 9. 3-SPI Data Transfer Format
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Serial Data Transfer Formats – continued
(2) When SCL is stopped at the high level
SCE
SCL
L
SDI
0
1
0
0
0
0
1
B0
B1
B2
B3
A0
A1
A2
0
D1
D2
D71
D72
0
0
0
0
0
KM0
KM1
KM2
P0
P1
P2
Device Code
Display Data
8bit
0
1
0
0
0
0
1
B1
B2
B3
A0
A1
A2
DR
DT
FC0
FC1
0
0
0
0
1
B2
B3
A0
A1
A2
0
D73
D74
0
D157
D143
D158
D144
D145
D146
D147
D148
D149
D150
D151
D152
D153
D154
D155
D156
PG1
PG2
PG3
PG4
1
0
0
0
0
1
B2
B3
A0
A1
A2
PG5
PG6
PF0
PF1
PF2
PF3
0
0
1
D207
0
0
0
0
DD
10bit
0
0
0
W10
51bit
B1
0
Control Data
Display Data
8bit
0
BU2
W11
W16
W17
W20
W21
W26
W27
2bit
W30
W31
W36
W37
1
0
A3
Device Code
B0
BU1
DD
84bit
1
BU0
2bit
Display Data
B1
SC
A3
8bit
0
OC
22bit
Device Code
B0
FC2
Control Data
72bit
B0
FL
A3
0
0
0
0
0
0
0
0
0
0
0
W40
Control Data
DD
39bit
2bit
W41
W46
W47
W50
W51
W56
W57
W60
W61
W66
W67
1
1
A3
Device Code
8bit
Control Data
DD
94bit
2bit
Figure 10. 3-SPI Data Transfer Format
Device code ----------------------------- “42H”
D1 to D276 ------------------------------ Display data
KM0 to KM2 ----------------------------- Key Scan output pin / Segment output pin switching control data
P0 to P2 ---------------------------------- Segment / PWM / General-purpose output pin switching control data
FL ------------------------------------------ Line Inversion or Frame Inversion switching control data
DR ----------------------------------------- 1/3 Bias drive or 1/2 Bias drive switching control data
DT ----------------------------------------- 1/4 Duty drive or 1/3 Duty drive switching control data
FC0 to FC2 ------------------------------ Common / Segment output waveform frame frequency switching control data
OC ----------------------------------------- Internal oscillator operating mode / External clock operating mode switching control data
SC ----------------------------------------- Segment on/off control data
BU0 to BU2 ------------------------------ Normal mode / power-saving mode control data
PG1 to PG6 ------------------------------ PWM / General-purpose output control data
PF0 to PF3 ------------------------------- PWM output waveform frame frequency control data
Wn0 to Wn7 (n=1 to 6) ---------------- PWM output waveform duty control data
DD------------------------------------------- Direction data
When it is coincident with device code, BU91520KV-M capture display data and control data at falling edge of SCE.
So, please transfer the bit number of send display data and control data as specified number in the above figure.
Specified number of bits is 104bit (Device code: 8bit, Display data and Control data: 94bit, DD: 2bit).
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Control Data Functions
1. KM0, KM1 and KM2: Key Scan output pin / Segment output pin switching control data
These control data bits switch the functions of the KS1/S56 to KS6/S61 output pins between key scan output and segment
output.
Output Pin State
Maximum
Reset
KM0
KM1
KM2
Number of
Condition
KS1/S56 KS2/S57 KS3/S58 KS4/S59 KS5/S60 KS6/S61
Input keys
0
0
0
KS1
KS2
KS3
KS4
KS5
KS6
30
0
0
1
S56
KS2
KS3
KS4
KS5
KS6
25
0
1
0
S56
S57
KS3
KS4
KS5
KS6
20
0
1
1
S56
S57
S58
KS4
KS5
KS6
15
1
0
0
S56
S57
S58
S59
KS5
KS6
10
1
0
1
S56
S57
S58
S59
S60
KS6
5
1
1
0
S56
S57
S58
S59
S60
S61
0
1
1
1
S56
S57
S58
S59
S60
S61
0
○
2. P0, P1, and P2: Segment / PWM / General-purpose output pin switching control data
These control data bits are used to select the function of the S1/P1/G1 to S6/P6/G6 output pins (Segment Output Pins or
PWM Output Pins or General-purpose Output Pins).
Reset
P0
P1
P2
S1/P1/G1
S2/P2/G2
S3/P3/G3
S4/P4/G4
S5/P5/G5
S6/P6/G6
Condition
0
0
0
S1
S2
S3
S4
S5
S6
○
0
0
1
P1/G1
S2
S3
S4
S5
S6
0
1
0
P1/G1
P2/G2
S3
S4
S5
S6
0
1
1
P1/G1
P2/G2
P3/G3
S4
S5
S6
1
0
0
P1/G1
P2/G2
P3/G3
P4/G4
S5
S6
1
0
1
P1/G1
P2/G2
P3/G3
P4/G4
P5/G5
S6
1
1
0
P1/G1
P2/G2
P3/G3
P4/G4
P5/G5
P6/G6
1
1
1
S1
S2
S3
S4
S5
S6
PWM output or General-purpose output pin is selected by PGx (x=1 to 6) control data bit.
When the General-purpose Output Pin Function is selected, the correspondence between the output pins and the respective
display data is given in the table below.
Corresponding Display Data
Output Pins
1/4 Duty Mode
1/3 Duty Mode
S1/P1/G1
D1
D1
S2/P2/G2
D5
D4
S3/P3/G3
D9
D7
S4/P4/G4
D13
D10
S5/P5/G5
D17
D13
S6/P6/G6
D21
D16
When the General-purpose Output Pin Function is selected, the respective output pin outputs a “HIGH” level when its
corresponding display data is set to “1”. Likewise, it will output a “LOW” level, if its corresponding display data is set to “0”.
For example, S4/P4/G4 is used as a General -purpose Output Pin in case of 1/4 Duty, if its corresponding display data
D13 is set to “1”, then S4/P4/G4 will output “HIGH(VDD)” level. Likewise, if D13 is set to “0”, then S4/P4/G4 will output
“LOW(VSS)” level.
3. DR: 1/3 Bias drive or 1/2 Bias drive switching control data
This control data bit selects either 1/3 Bias drive or 1/2 Bias drive.
DR
Bias Drive Scheme
0
1/3 Bias drive
1
1/2 Bias drive
Reset Condition
○
-
4. FL: Line Inversion or Frame Inversion switching control data
This control data bit selects either Line Inversion or Frame Inversion.
FL
Inversion Setting
Reset Condition
0
Line
○
1
Frame
Typically, when driving large capacitance LCD, Line inversion will increase the influence of crosstalk.
Regarding driving waveform, refer to LCD Driving Waveform
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Control Data Functions – continued
5. DT: 1/4 Duty drive or 1/3 Duty drive switching control data
This control data bit selects either 1/4 Duty drive or 1/3 Duty drive.
DT
Duty Drive Scheme
0
1/4 Duty drive
1
1/3 Duty drive
Reset Condition
○
-
6. FC0, FC1 and FC2: Common / Segment output waveform frame frequency switching control data
These control data bits set the display frame frequency.
Display Frame Frequency
FC0
FC1
FC2
Reset Condition
fo(Hz)
fOSC(Note)/12288
0
0
0
○
0
0
1
fOSC/10752
0
1
0
fOSC/9216
0
1
1
fOSC/7680
1
0
0
fOSC/6144
1
0
1
fOSC/4608
1
1
0
fOSC/3840
1
1
1
fOSC/3072
(Note) fOSC: Internal oscillation frequency (600 kHz Typ)
7. OC: Internal oscillator operating mode / External clock operating mode switching control data
This control data bit selects the oscillation mode.
OC
Operating Mode
In/Out Pin(OSC/S69) Status
Reset Condition
0
Internal oscillator
S69 (segment output)
○
1
External Clock
OSC (clock input)
Internal oscillation / external clock select signal behavior is below.
Please input external clock after serial data sending.
SCE
SCL
SDI
0
1
0
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
D1
D2
OC
Display Data/
Control Data
Dev ice Code
8bits
SC
BU0
BU1
BU2
0
0
DD
2 bits
Internal oscillation・Extarnal Clock
Select signal(Internal signal)
Internal oscillation
(Internal signal)
Extarnal Clock
(OSC)
8. SC: Segment on/off control data
This control data bit controls the on/off state of the segments.
SC
Display State
Reset Condition
0
On
1
Off
○
Note that when the segments are turned off by setting SC to “1”, the segments are turned off by outputting segment off
waveforms from the segment output pins.
9. BU, BU1 and BU2: Normal mode / power-saving mode control data
This control data bit selects either normal mode or power-saving mode.
Segment Outputs Output Pin States During Key Scan Standby
OSC
BU0 BU1 BU2
Mode
Oscillator
Common Outputs KS1
KS2
KS3
KS4
KS5
KS6
0
0
0
Normal
Operating
Operating
H
H
H
H
H
H
0
0
1
L
L
L
L
L
H
0
1
0
L
L
L
L
H
H
0
1
1
L
L
L
H
H
H
Power1
0
0
Stopped
Low(VSS)
L
L
H
H
H
H
saving
1
0
1
L
H
H
H
H
H
1
1
0
H
H
H
H
H
H
1
1
1
H
H
H
H
H
H
Power-saving mode status: S1/P1/G1 to S6/P6/G6=active only General-purpose output
S7 to S69=low(VSS)
COM1 to COM4=low(VSS)
Stop the LCD drive bias voltage generation circuit
Stop the Internal oscillation circuit
However, serial data transfer is possible.
Regarding the details of the INHb pin and the control of each output, refer to “INHb Pin and Display Control”.
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Reset
Condition
○
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BU91520KV-M
Control Data Functions – continued
10. PG1, PG2, PG3, PG4, PG5 and PG6: PWM / General-purpose output control data
This control data bit select either PWM output or General-purpose output of Sx/Px/Gx pins.(x=1 to 6)
PGx(x=1 to 6)
Mode
Reset Condition
0
PWM output
○
1
General-purpose output
Normal behavior of changing GPO to PWM is below.
- PWM operation is started by command import timing of DD:01 during GPO - PWM change.
- Please take care of reflect timing of new duty setting of DD:10 and DD: 11 is from the next PWM.
SCE
DD:01
DD:00
DD:10
GPO--> PWM change
DD:11
New duty decided timing
PWM / GPO output
Start of PWM operation
(PWM waveform in immediate duty)
Next PWM cycle
(PWM waveform in new duty)
In order to avoid this operation, please input commands in reverse as below
DD:10
DD:11
DD:01
DD:00
SCE
New duty decided timing
GPO--＞PWM change
PWM / GPO output
Start of PWM operation
(PWM waveform on new duty)
11. PF0, PF1, PF2 and PF3: PWM output waveform frame frequency control data
These control data bits set the frame frequency for PWM output waveforms.
PWM output Frame Frequency
PF0
PF1
PF2
PF3
fp(Hz)
0
0
0
0
fOSC/4096
0
0
0
1
fOSC/3840
0
0
1
0
fOSC/3584
0
0
1
1
fOSC/3328
0
1
0
0
fOSC/3072
0
1
0
1
fOSC/2816
0
1
1
0
fOSC /2560
0
1
1
1
fOSC /2304
1
0
0
0
fOSC/2048
1
0
0
1
fOSC/1792
1
0
1
0
fOSC/1536
1
0
1
1
fOSC/1280
1
1
0
0
fOSC/1024
1
1
0
1
fOSC/768
1
1
1
0
fOSC/512
1
1
1
1
fOSC/256
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Reset
Condition
○
-
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BU91520KV-M
Control Data Functions – continued
12. W10 to W17(Note), W20 to W27, W30 to W37, W40 to W47, W50 to W57 and W60 to W67: PWM output waveform duty
control data.
These control data bits set the high level pulse width for PWM output waveforms
N=1 to 6, Tp=1/fp
Wn0
Wn1
Wn2
Wn3
Wn4
Wn5
Wn6
Wn7
PWM Duty
Reset Condition
0
0
0
0
0
0
0
0
(1/256) x Tp
○
0
0
0
0
0
0
0
1
(2/256) x Tp
0
0
0
0
0
0
1
0
(3/256) x Tp
0
0
0
0
0
0
1
1
(4/256) x Tp
0
0
0
0
0
1
0
0
(5/256) x Tp
0
0
0
0
0
1
0
1
(6/256) x Tp
0
0
0
0
0
1
1
0
(7/256) x Tp
0
0
0
0
0
1
1
1
(8/256) x Tp
0
0
0
0
1
0
0
0
(9/256) x Tp
0
0
0
0
1
0
0
1
(10/256) x Tp
0
0
0
0
1
0
1
0
(11/256) x Tp
0
0
0
0
1
0
1
1
(12/256) x Tp
0
0
0
0
1
1
0
0
(13/256) x Tp
0
0
0
0
1
1
0
1
(14/256) x Tp
0
0
0
0
1
1
1
0
(15/256) x Tp
0
0
0
0
1
1
1
1
(16/256) x Tp
0
0
0
1
0
0
0
0
(17/256) x Tp
0
0
0
1
0
0
0
1
(18/256) x Tp
0
0
0
1
0
0
1
0
(19/256) x Tp
0
0
0
1
0
0
1
1
(20/256) x Tp
0
0
0
1
0
1
0
0
(21/256) x Tp
0
0
0
1
0
1
0
1
(22/256) x Tp
0
0
0
1
0
1
1
0
(23/256) x Tp
0
0
0
1
0
1
1
1
(24/256) x Tp
0
0
0
1
1
0
0
0
(25/256) x Tp
0
0
0
1
1
0
0
1
(26/256) x Tp
0
0
0
1
1
0
1
0
(27/256) x Tp
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
(230/256) x Tp
(231/256) x Tp
(232/256) x Tp
(233/256) x Tp
(234/256) x Tp
(235/256) x Tp
(236/256) x Tp
(237/256) x Tp
(238/256) x Tp
(239/256) x Tp
(240/256) x Tp
(241/256) x Tp
(242/256) x Tp
(243/256) x Tp
(244/256) x Tp
(245/256) x Tp
(246/256) x Tp
(247/256) x Tp
(248/256) x Tp
(249/256) x Tp
(250/256) x Tp
(251/256) x Tp
(252/256) x Tp
(253/256) x Tp
(254/256) x Tp
(255/256) x Tp
(256/256) x Tp
-
(Note):W10 to W17:S1/P1/G1 PWM duty data
W20 to W27:S2/P2/G2 PWM duty data
W30 to W37:S3/P3/G3 PWM duty data
W40 to W47:S4/P4/G4 PWM duty data
W50 to W57:S5/P5/G5 PWM duty data
W60 to W67:S6/P6/G6 PWM duty data
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BU91520KV-M
Display Data and Output Pin Correspondence
1. 1/4 Duty
Output Pin(Note)
S1/P1/G1
S2/P2/G2
S3/P3/G3
S4/P4/G4
S5/P5/G5
S6/P6/G6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
S46
S47
S48
S49
S50
S51
S52
S53
S54
S55
S56
S57
S58
S59
S60
S61
S62
S63
COM1
D1
D5
D9
D13
D17
D21
D25
D29
D33
D37
D41
D45
D49
D53
D57
D61
D65
D69
D73
D77
D81
D85
D89
D93
D97
D101
D105
D109
D113
D117
D121
D125
D129
D133
D137
D141
D145
D149
D153
D157
D161
D165
D169
D173
D177
D181
D185
D189
D193
D197
D201
D205
D209
D213
D217
D221
D225
D229
D233
D237
D241
D245
D249
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TSZ22111 • 15 • 001
COM2
D2
D6
D10
D14
D18
D22
D26
D30
D34
D38
D42
D46
D50
D54
D58
D62
D66
D70
D74
D78
D82
D86
D90
D94
D98
D102
D106
D110
D114
D118
D122
D126
D130
D134
D138
D142
D146
D150
D154
D158
D162
D166
D170
D174
D178
D182
D186
D190
D194
D198
D202
D206
D210
D214
D218
D222
D226
D230
D234
D238
D242
D246
D250
15/42
COM3
D3
D7
D11
D15
D19
D23
D27
D31
D35
D39
D43
D47
D51
D55
D59
D63
D67
D71
D75
D79
D83
D87
D91
D95
D99
D103
D107
D111
D115
D119
D123
D127
D131
D135
D139
D143
D147
D151
D155
D159
D163
D167
D171
D175
D179
D183
D187
D191
D195
D199
D203
D207
D211
D215
D219
D223
D227
D231
D235
D239
D243
D247
D251
COM4
D4
D8
D12
D16
D20
D24
D28
D32
D36
D40
D44
D48
D52
D56
D60
D64
D68
D72
D76
D80
D84
D88
D92
D96
D100
D104
D108
D112
D116
D120
D124
D128
D132
D136
D140
D144
D148
D152
D156
D160
D164
D168
D172
D176
D180
D184
D188
D192
D196
D200
D204
D208
D212
D216
D220
D224
D228
D232
D236
D240
D244
D248
D252
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18.Jul.2019 Rev.003
BU91520KV-M
Display Data and Output Pin Correspondence – continued
Output pin(Note)
S64
S65
S66
S67
S68
S69
COM1
D253
D257
D261
D265
D269
D273
COM2
D254
D258
D262
D266
D270
D274
COM3
D255
D259
D263
D267
D271
D275
COM4
D256
D260
D264
D268
D272
D276
(Note) The Segment Output Pin function is assumed to be selected for the output pins – S1/P1/G1 to S6/P6/G6.
To illustrate further, the states of the S21 output pin is given in the table below.
Display Data
State of S21 Output Pin
D81
D82
D83
D84
0
0
0
0
LCD Segments corresponding to COM1 to COM4 are OFF.
0
0
0
1
LCD Segment corresponding to COM4 is ON.
0
0
1
0
LCD Segment corresponding to COM3 is ON.
0
0
1
1
LCD Segments corresponding to COM3 and COM4 are ON.
0
1
0
0
LCD Segment corresponding to COM2 is ON.
0
1
0
1
LCD Segments corresponding to COM2 and COM4 are ON.
0
1
1
0
LCD Segments corresponding to COM2 and COM3 are ON.
0
1
1
1
LCD Segments corresponding to COM2, COM3 and COM4 are ON.
1
0
0
0
LCD Segment corresponding to COM1 is ON.
1
0
0
1
LCD Segments corresponding to COM1 and COM4 are ON.
1
0
1
0
LCD Segments corresponding to COM1 and COM3 are ON.
1
0
1
1
LCD Segments corresponding to COM1, COM3 and COM4 are ON.
1
1
0
0
LCD Segments corresponding to COM1 and COM2 are ON.
1
1
0
1
LCD Segments corresponding to COM1, COM2 and COM4 are ON.
1
1
1
0
LCD Segments corresponding to COM1, COM2 and COM3 are ON.
1
1
1
1
LCD Segments corresponding to COM1 to COM4 are ON.
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BU91520KV-M
Display Data and Output Pin Correspondence – continued
2. 1/3 Duty
Output Pin(Note)
S1/P1/G1
S2/P2/G2
S3/P3/G3
S4/P4/G4
S5/P5/G5
S6/P6/G6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
S46
S47
S48
S49
S50
S51
S52
S53
S54
S55
S56
S57
S58
S59
S60
S61
S62
S63
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TSZ22111 • 15 • 001
COM1
D1
D4
D7
D10
D13
D16
D19
D22
D25
D28
D31
D34
D37
D40
D43
D46
D49
D52
D55
D58
D61
D64
D67
D70
D73
D76
D79
D82
D85
D88
D91
D94
D97
D100
D103
D106
D109
D112
D115
D118
D121
D124
D127
D130
D133
D136
D139
D142
D145
D148
D151
D154
D157
D160
D163
D166
D169
D172
D175
D178
D181
D184
D187
COM2
D2
D5
D8
D11
D14
D17
D20
D23
D26
D29
D32
D35
D38
D41
D44
D47
D50
D53
D56
D59
D62
D65
D68
D71
D74
D77
D80
D83
D85
D89
D92
D95
D98
D101
D104
D107
D110
D113
D116
D119
D122
D125
D128
D131
D134
D137
D140
D143
D146
D149
D152
D155
D158
D161
D164
D167
D170
D173
D176
D179
D182
D185
D188
17/42
COM3
D3
D6
D9
D12
D15
D18
D21
D24
D27
D30
D33
D36
D39
D42
D45
D48
D51
D54
D57
D60
D63
D66
D69
D72
D75
D78
D81
D84
D87
D90
D93
D96
D99
D102
D105
D108
D111
D114
D117
D120
D123
D126
D129
D132
D135
D138
D141
D144
D147
D150
D153
D156
D159
D162
D165
D168
D171
D174
D177
D180
D183
D186
D189
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18.Jul.2019 Rev.003
BU91520KV-M
Display Data and Output Pin Correspondence – continued
Output Pin(Note)
S64
S65
S66
S67
S68
S69
COM1
D190
D193
D196
D199
D202
D205
COM2
D191
D194
D197
D200
D203
D206
COM3
D192
D195
D198
D201
D204
D207
(Note) The Segment Output Pin function is assumed to be selected for the output pins – S1/P1/G1 to S6/P6/G6.
To illustrate further, the states of the S21 output pin is given in the table below.
Display Data
State of S21 Output Pin
D61
D62
D63
0
0
0
LCD Segments corresponding to COM1, COM2 and COM3 are OFF.
0
0
1
LCD Segment corresponding to COM3 is ON.
0
1
0
LCD Segment corresponding to COM2 is ON.
0
1
1
LCD Segments corresponding to COM2 and COM3 are ON.
1
0
0
LCD Segment corresponding to COM1 is ON.
1
0
1
LCD Segments corresponding to COM1 and COM3 are ON.
1
1
0
LCD Segments corresponding to COM1 and COM2 are ON.
1
1
1
LCD Segments corresponding to COM1, COM2 and COM3 are ON.
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BU91520KV-M
Serial Data Output
1. When SCL is stopped at the low level(Note 1)
SCE
SCL
SDI
1
1
0
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
SDO
X
KD1
KD2
KD27
KD28
KD29
KD30
PA
Output Data
Figure 11. Serial data output format
(Note 1)
1. X=Don’t care
2. B0 to B3, A0 to A3: Serial Interface address
3. Serial Interface address: 43H
4. KD1 to KD30: Key data
5. PA: Power-saving acknowledge data
6. If a key data read operation is executed when SDO is high, the read key data (KD1 to KD30) and power-saving acknowledge data (PA) will be invalid.
2. When SCL is stopped at the high level(Note 2 )
SCE
SCL
SDI
1
1
0
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
SDO
X
KD1
KD2
KD3
KD28
KD29
KD30
PA
X
Output Data
Figure 12. Serial Data Output Format
(Note 2 )
1. X=Don’t care
2. B0 to B3, A0 to A3: Serial Interface address
3. Serial Interface address: 43H
4. KD1 to KD30: Key data
5. PA: Power-saving acknowledge data
6. If a key data read operation is executed when SDO is high, the read key data (KD1 to KD30) and power-saving acknowledge data (PA) will be invalid.
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BU91520KV-M
Output Data
1. KD1 to KD30: Key Data
When a key matrix of up to 30 keys is formed from the KS1 to KS6 output pins and the KI1 to KI5 input pins and one of those
keys is pressed, the key output data corresponding to that key will be set to 1. The table shows the relationship between
those pins and the key data bits.
Item
KS1
KS2
KS3
KS4
KS5
KS6
KI1
KD1
KD6
KD11
KD16
KD21
KD26
KI2
KD2
KD7
KD12
KD17
KD22
KD27
KI3
KD3
KD8
KD13
KD18
KD23
KD28
KI4
KD4
KD9
KD14
KD19
KD24
KD29
KI5
KD5
KD10
KD15
KD20
KD25
KD30
2. PA: Power-saving Acknowledge Data
This output data is set to the state when the key was pressed. In that case SDO will go to the low level. If serial data is input
during this period and the mode is set (normal mode or power-saving mode), the IC will be set to that mode. PA is set to 1 in
the power-saving mode and to 0 in the normal mode.
Power-saving Mode
Power-saving mode is activated when least one of control data BU0 or BU1 or BU2 is set to 1. All segment and common
outputs will go low. The oscillation circuit will stop (It can be restarted by a key press), thus reducing power consumption This
mode can be disabled when control data bits BU0, BU1 and BU2 are all set to 0. However, note that the S1/P1/G1 to
S6/P6/G6 outputs can still be used as General-purpose output pins according to the state of the P0 to P2 control data bits,
even in power-saving mode. (See Control Data Functions.)
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BU91520KV-M
Key Scan Operation Function
1. Key Scan Timing
The key scan period is 4608T(s). To reliably determine the on/off state of the keys, the BU91520KV-M scans the keys twice
and determines that a key has been pressed when the key data agrees. It outputs a key data read request (a low level on
SDO) 9840T(s) after starting a key scan. If the key data does not agree and a key was pressed at that point, it scans the
keys again. Thus the BU91520KV-M cannot detect a key press shorter than 9840T(s).
KS1
*
KS2
*
KS3
*
KS4
*
KS5
*
1
1
*
2
2
*
3
3
4
*
4
5
*
5
6
KS6
*
6
9216T(s)
T=
1
fOSC
Figure 13. Key Scan Timing(Note)
(Note) In power-saving mode the high/low state of these pins is determined by the BU0 to BU2 bits in the control data. Key scan output signals are not output
from pins that are set “L”.
2. In Normal Mode
The pins KS1 to KS6 are set “H”.
When a key is pressed a key scan is started and the keys are scanned until all keys are released. Multiple key presses are
recognized by determining whether multiple key data bits are set.
If a key is pressed for longer than 9840T(s) (Where T=1/fOSC ) the BU91520KV-M outputs a key data read request (a low
level on SDO) to the controller. The controller acknowledges this request and reads the key data. However, if SCE is high
during a serial data transfer, SDO will be set “H”.
After the controller reads the key data, the key data read request is cleared (SDO is set high) and the BU91520KV-M
performs another key scan. Also note that SDO, being an open-drain output, requires a pull-up resistor (between 1 kΩ and
10kΩ).
Key Input 1
Key Input 2
Key scan
9840T(s)
9840T(s)
9840T(s)
SCE
Serial data transf er
Serial data transf er
Key address(43H)
Serial data transf er
Key address
Key address
SDI
SDO
Key data read
Key data read
Key data read request
Key data read request
Key data read
Key data read request
1
T=
f OSC
Figure 14. Key Scan Operation In Normal Mode
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BU91520KV-M
Key Scan Operation Function – continued
3. In Power-saving Mode
The pins KS1 to KS6 are set to high or low by the BU0 to BU2 bits in the control data. (See the Control Data Functions for
details.)
If a key on one of the lines corresponding to a KS1 to KS6 pin which is set high is pressed, the oscillation is started and a
key scan is performed. Keys are scanned until all keys are released. Multiple key presses are recognized by determining
whether multiple key data bits are set.
If a key is pressed for longer than 9840T(s) (Where T=1/fOSC) the BU91520KV-M outputs a key data read request (a low level
on SDO) to the controller. The controller acknowledges this request and reads the key data. However, if SCE is high during a
serial data transfer, SDO will be set high.
After the controller reads the key data, the key data read request is cleared (SDO is set high) and the BU91520KV-M
performs another key scan. However, this does not clear power-saving mode. Also note that SDO, being an open-drain output,
requires a pull-up resistor (between 1kΩ and 10kΩ).
Power-saving mode key scan example
Example: BU0=0, BU1=0, BU2=1 (only KS6 high level output)
(L)KS1
(L)KS2
(L)KS3
When any one of these keys is pressed,
the oscillation is started and the keys are scanned.
(L)KS4
(L)KS5
(H)KS6
(Note)
Kl1
Kl2
Kl3
Kl4
Kl5
(Note)
These diodes are required to reliable recognize multiple key presses on the KS6 line when power-saving mode state with only KS6 high, as in the above
example. That is, these diodes prevent incorrect operations due to sneak currents in the KS6 key scan output signal when keys on the KS1 to KS5 lines are
pressed at the same time.
Key Input 2
(KS6 line)
Key scan
9840T(s)
9840T(s)
SCE
Serial data transf er
Serial data transf er
Key address(43H)
Serial data transf er
Key address
SDI
SDO
Key data read
Key data read
Key data read request
Key data read request
T=
1
f OSC
Figure 15. Key Scan Operation In Power-saving Mode
Multiple Key Press
Although the BU91520KV-M is capable of key scanning without inserting diodes for dual key presses, triple key presses on
the KI1 to KI5 input pin lines, or multiple key presses on the KS1 to KS6 output pin lines, multiple key presses other than
these cases may result in keys that were not pressed recognized as having been pressed. Therefore, a diode must be
inserted in series with each key. Applications that do not recognize multiple key presses of three or more keys should ignore
the key data if the key data contains three or more bits that has a value of “1”.
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BU91520KV-M
Controller Key Data Read Technique
When the controller receives a key data read request from BU91520KV-M, it performs a key data read acquisition operation
using either the Timer Based Key Data Acquisition or the Interrupt Based Key Data Acquisition.
1. Timer Based Key Data Acquisition Technique
Under the Timer Based Key Data Acquisition Technique, the controller uses a timer to determine the states of the keys
(on or off) and read the key data. Please refer to the flow chart below.
SCE ＝ 「L 」
NO
SDO ＝ 「L 」
YES
Key data read
processing
Key data read processing: Refer to “Serial Data Output”
Figure 16. Flowchart
In this technique, the controller uses a timer to determine key on/off states and read the key data. The controller must check
the SDO state when SCE is low every t7 period without fail. If SDO is low, the controller recognizes that a key has been
pressed and executes the key data read operation.
The period t7 in this technique must satisfy the following condition.
t7>t4+t5+t6
If a key data read operation is executed when SDO is high, the read key data (KD1 to KD30) and power-saving acknowledge
data (PA) will be invalid.
Key on
Key on
Key Input 1
Key scan
t3
t3
t4
t3
SCE
t6
t6
t6
SDI
t5
t5
t5
Key data read
SDO
Key data read request
t7
Controller determination
(key on)
t7
t7
t7
Controller determination
(key on)
Controller determination
(key on)
Controller determination
(key on)
Controller determination
(key on)
t3: Key scan execution time when the key data agreed for two key scans. 9840T(s)
t4: Key scan execution time when the key data did not agree for two key scans and the key scan was executed again.
19680T(s) (T=1/fOSC)
t5: Key address (43H) transfer time
t6: Key data read time
Figure 17. Timer Based Key Data Read Operation
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BU91520KV-M
Controller Key Data Read Technique – continued
2. Interrupt Based Key Data Acquisition Technique
Under the Interrupt Based Key Data Acquisition Technique, the controller uses interrupts to determine the state of the keys
(on or off) and read the key data. Please refer to the flow chart diagram below.
SCE＝
「L」
SDO ＝「L」
NO
YES
Key data read
processing
Wait for at
least t8
NO
「H」
SDO ＝
YES
Key off
Key data read processing: Refer to “Serial Data Output”
Figure 18. Flowchart
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BU91520KV-M
Controller Key Data Read Technique – continued
In this technique, the controller uses interrupts to determine key on/off states and read the key data. The controller must
check the SDO state when SCE is low. If SDO is low, the controller recognizes that a key has been pressed and executes
the key data read operation. After that the next key on/off determination is performed after the time t8 has elapsed by
checking the SDO state when SCE is low and reading the key data. The period t8 in this technique must satisfy t8 > t4.
If a key data read operation is executed when SDO is high, the read key data (KD1 to KD30) and power-saving acknowledge
data (PA) will be invalid.
Key on
Key on
Key Input 1
Key scan
t3
t3
t4
t3
SCE
t6
t6
t6
t6
SDI
t5
t5
t5
t5
Key data read
SDO
Key data read request
Controller
Controller
determination determination
(key on)
(key on)
t8
t8
t8
t8
Controller
determination
(key on)
Controller
determination
(key on)
Controller
determination
(key on)
Controller
determination
(key on)
t3: Key scan execution time when the key data agreed for two key scans. 9840T(s)
t4: Key scan execution time when the key data did not agree for two key scans and the key scan was executed again.
19680T(s) (T=1/fOSC)
t5: Key address (43H) transfer time
t6: Key data read time
Figure 19. Interrupt Based Key Data Read Operation
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BU91520KV-M
LCD Driving Waveform
1. Line Inversion 1/4 Duty 1/3 Bias Drive Scheme
fo[Hz]
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
COM1
COM2
COM3
COM4
LCD driver output when all LCD
segment correstpoding to COM1,
COM2,COM3, and COM4 are off.
LCD driver output when only LCD segments
corresponding to COM1 is on.
LCD driver output when only LCD segments
corresponding to COM2 is on.
LCD driver output when LCD segments
corresponding to COM1 and COM2 are on.
LCD driver output when only LCD segments
corresponding to COM3 is on.
LCD driver output when LCD segments
corresponding to COM1 and COM3 are on.
LCD driver output when LCD segments
corresponding to COM2 and COM3 are on.
LCD driver output when LCD segments
corresponding to COM1, COM2,
and COM3 are on.
LCD driver output when only LCD segments
corresponding to COM4 is on.
LCD driver output when LCD segments
corresponding to COM2 and COM4 are on.
LCD driver output when
all LCD segments corresponding
to COM1, COM2, COM3, and COM4 are on.
Figure 20. LCD Waveform (1/4 Duty, 1/3 Bias, Line Inversion)
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LCD Driving Waveform – continued
2. Line Inversion 1/4 Duty 1/2 Bias Drive Scheme
fo[Hz]
VLCD
VLCD1,VLCD2
COM1
0V
VLCD
VLCD1,VLCD2
COM2
0V
VLCD
VLCD1,VLCD2
COM3
0V
VLCD
VLCD1,VLCD2
COM4
0V
LCD driver output when all LCD
VLCD
segment corresponding to COM1,
VLCD1,VLCD2
COM2,COM3, and COM4 are off.
0V
VLCD
LCD driver output when only LCD segments
VLCD1,VLCD2
corresponding to COM1 are on.
0V
VLCD
LCD driver output when only LCD segments
VLCD1,VLCD2
corresponding to COM2 are on.
0V
VLCD
LCD driver output when LCD segments
VLCD1,VLCD2
corresponding to COM1 and COM2 are on.
0V
VLCD
LCD driver output when only LCD segments
VLCD1,VLCD2
corresponding to COM3 are on.
0V
VLCD
LCD driver output when LCD segments
VLCD1,VLCD2
corresponding to COM1 and COM3 are on.
0V
VLCD
LCD driver output when LCD segments
VLCD1,VLCD2
corresponding to COM2 and COM3 are on.
0V
VLCD
LCD driver output when LCD segments
VLCD1,VLCD2
corresponding to COM1,COM2 and COM3 are on.
0V
VLCD
LCD driver output when only LCD segments
VLCD1,VLCD2
corresponding to COM4 are on.
0V
VLCD
LCD driver output when LCD segments
VLCD1,VLCD2
corresponding to COM2 and COM4 are on.
0V
VLCD
LCD driver output when
VLCD1,VLCD2
all LCD segments corresponding
0V
to COM1, COM2, COM3, and COM4 are on.
Figure 21. LCD Waveform (1/4 Duty, 1/2 Bias, Line Inversion)
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LCD Driving Waveform – continued
3. Line Inversion 1/3 Duty 1/3 Bias Drive Scheme
fo[Hz]
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
COM1
COM2
COM3
LCD driver output when all LCD
segments correstpoding to COM1,
COM2 and COM3 are off.
LCD driver output when only LCD segments
corresponding to COM1 is on.
LCD driver output when only LCD segments
corresponding to COM2 is on.
LCD driver output when LCD segments
corresponding to COM1 and COM2 are on.
LCD driver output when only LCD segments
corresponding to COM3 is on.
LCD driver output when LCD segments
corresponding to COM1 and COM3 are on.
LCD driver output when LCD segments
corresponding to COM2 and COM3 are on.
LCD driver output when all LCD segments
corresponding to COM1, COM2,
and COM3 are on.
Figure 22. LCD Waveform (1/3 Duty, 1/3 Bias, Line Inversion)(Note)
(Note) COM4 function is same as COM1 at 1/3 Duty.
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LCD Driving Waveform – continued
4. Line Inversion 1/3 Duty 1/2 Bias Drive Scheme
fo[Hz]
VLCD
VLCD1,VLCD2
COM1
0V
VLCD
VLCD1,VLCD2
COM2
0V
VLCD
VLCD1,VLCD2
COM3
0V
LCD driver output when all LCD
VLCD
segments correstpoding to COM1,
VLCD1,VLCD2
COM2, and COM3 are off.
0V
VLCD
LCD driver output when only LCD segments
VLCD1,VLCD2
corresponding to COM1 is on.
0V
VLCD
LCD driver output when only LCD segments
VLCD1,VLCD2
corresponding to COM2 is on.
0V
VLCD
LCD driver output when LCD segments
VLCD1,VLCD2
corresponding to COM1 and COM2 are on.
0V
VLCD
LCD driver output when only LCD segments
VLCD1,VLCD2
corresponding to COM3 is on.
0V
VLCD
LCD driver output when LCD segments
VLCD1,VLCD2
corresponding to COM1 and COM3 are on.
0V
VLCD
LCD driver output when LCD segments
VLCD1,VLCD2
corresponding to COM2 and COM3 are on.
0V
VLCD
LCD driver output when all LCD segments
VLCD1,VLCD2
corresponding to COM1,COM2 and COM3 are on.
0V
Figure 23. LCD Waveform (1/3 Duty, 1/2 Bias, Line Inversion)(Note)
(Note) COM4 function is same as COM1 at 1/3 Duty.
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LCD Driving Waveform – continued
5. Frame Inversion 1/4 Duty 1/3 Bias Drive Scheme
fo[Hz]
VLCD
VLCD1
COM1
VLCD2
0V
VLCD
VLCD1
COM2
VLCD2
0V
VLCD
VLCD1
COM3
VLCD2
0V
VLCD
VLCD1
COM4
VLCD2
0V
VLCD
LCD driver output when all LCD
VLCD1
segments corresponding to COM1,
VLCD2
COM2, COM3 and COM4 are off.
0V
VLCD
LCD driver output when only LCD segments
VLCD1
corresponding to COM1 is on.
VLCD2
0V
VLCD
LCD driver output when only LCD segments
VLCD1
corresponding to COM2 is on.
VLCD2
0V
VLCD
LCD driver output when LCD segments
VLCD1
corresponding to COM1 and COM2 are on.
VLCD2
0V
VLCD
LCD driver output when only LCD segments
VLCD1
corresponding to COM3 is on.
VLCD2
0V
VLCD
LCD driver output when LCD segments
VLCD1
corresponding to COM1 and COM3 are on.
VLCD2
0V
VLCD
LCD driver output when LCD segments
VLCD1
corresponding to COM2 and COM3 are on.
VLCD2
0V
VLCD
LCD driver output when LCD segments
VLCD1
corresponding to COM1, COM2 and COM3 are on.
VLCD2
0V
VLCD
LCD driver output when only LCD segments
VLCD1
corresponding to COM4 is on.
VLCD2
0V
VLCD
LCD driver output when LCD segments
VLCD1
corresponding to COM2 and COM4 are on
VLCD2
0V
VLCD
LCD driver output when all LCD segments
VLCD1
corresponding to COM1, COM2, COM3
VLCD2
and COM4 are on.
0V
Figure 24. LCD Waveform (1/4 Duty, 1/3 Bias, Frame Inversion)
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LCD Driving Waveform – continued
6. Frame Inversion 1/4 Duty 1/2 Bias Drive Scheme
fo[Hz]
VLCD
VLCD1, VLCD2
COM1
0V
VLCD
VLCD1, VLCD2
COM2
0V
VLCD
VLCD1, VLCD2
COM3
0V
VLCD
VLCD1, VLCD2
COM4
0V
LCD driver output when all LCD
VLCD
segments corresponding to COM1,
VLCD1, VLCD2
COM2, COM3 and COM4 are off.
0V
VLCD
LCD driver output when only LCD segments
VLCD1, VLCD2
corresponding to COM1 is on.
0V
VLCD
LCD driver output when only LCD segments
VLCD1, VLCD2
corresponding to COM2 is on.
0V
VLCD
LCD driver output when LCD segments
VLCD1, VLCD2
corresponding to COM1 and COM2 are on.
0V
VLCD
LCD driver output when only LCD segments
VLCD1, VLCD2
corresponding to COM3 is on.
0V
VLCD
LCD driver output when LCD segments
VLCD1, VLCD2
corresponding to COM1 and COM3 are on.
0V
VLCD
LCD driver output when LCD segments
VLCD1, VLCD2
corresponding to COM2 and COM3 are on.
0V
VLCD
LCD driver output when LCD segments
VLCD1, VLCD2
corresponding to COM1, COM2 and COM3 are on.
0V
VLCD
LCD driver output when only LCD segments
VLCD1, VLCD2
corresponding to COM4 is on.
0V
VLCD
LCD driver output when LCD segments
VLCD1, VLCD2
corresponding to COM2 and COM4 are on.
0V
VLCD
LCD driver output when all LCD segments
VLCD1, VLCD2
corresponding to COM1, COM2, COM3
0V
and COM4 are on.
Figure 25. LCD Waveform (1/4 Duty, 1/2 Bias, Frame Inversion)
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LCD Driving Waveform – continued
7. Frame Inversion 1/3 Duty 1/3 Bias Drive Scheme
fo[Hz]
VLCD
VLCD1
COM1
VLCD2
0V
VLCD
VLCD1
COM2
VLCD2
0V
VLCD
VLCD1
COM3
VLCD2
0V
VLCD
LCD driver output when all LCD
VLCD1
segments corresponding to COM1,
VLCD2
COM2 and COM3 are off.
0V
VLCD
LCD driver output when only LCD segments
VLCD1
corresponding to COM1 is on.
VLCD2
0V
VLCD
LCD driver output when only LCD segments
VLCD1
corresponding to COM2 is on.
VLCD2
0V
VLCD
LCD driver output when LCD segments
VLCD1
corresponding to COM1 and COM2 are on.
VLCD2
0V
VLCD
LCD driver output when only LCD segments
VLCD1
corresponding to COM3 is on.
VLCD2
0V
VLCD
LCD driver output when LCD segments
VLCD1
corresponding to COM1 and COM3 are on.
VLCD2
0V
VLCD
LCD driver output when LCD segments
VLCD1
corresponding to COM2 and COM3 are on.
VLCD2
0V
VLCD
LCD driver output when all LCD segments
VLCD1
corresponding to COM1, COM2 and COM3 are on.
VLCD2
0V
Figure 26. LCD Waveform (1/3 Duty, 1/3 Bias, Frame Inversion)(Note)
(Note) COM4 function is same as COM1 at 1/3 Duty.
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LCD Driving Waveform – continued
8. Frame Inversion 1/3 Duty 1/2 Bias Drive Scheme
fo[Hz]
VLCD
VLCD1, VLCD2
COM1
0V
VLCD
VLCD1, VLCD2
COM2
0V
VLCD
VLCD1, VLCD2
COM3
0V
LCD driver output when all LCD
VLCD
segments corresponding to COM1,
VLCD1, VLCD2
COM2 and COM3 are off.
0V
VLCD
LCD driver output when only LCD segments
VLCD1, VLCD2
corresponding to COM1 is on.
0V
VLCD
LCD driver output when only LCD segments
VLCD1, VLCD2
corresponding to COM2 is on.
0V
VLCD
LCD driver output when LCD segments
VLCD1, VLCD2
corresponding to COM1 and COM2 are on.
0V
VLCD
LCD driver output when only LCD segments
VLCD1, VLCD2
corresponding to COM3 is on.
0V
VLCD
LCD driver output when LCD segments
VLCD1, VLCD2
corresponding to COM1 and COM3 are on.
0V
VLCD
LCD driver output when LCD segments
VLCD1, VLCD2
corresponding to COM2 and COM3 are on.
0V
VLCD
LCD driver output when all LCD
VLCD1, VLCD2
segments corresponding to COM1,
0V
COM2 and COM3 are on.
Figure 27. LCD Waveform (1/3 Duty, 1/2 Bias, Frame Inversion)(Note)
(Note) COM4 function is same as COM1 at 1/3 Duty
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INHb Pin and Display Control
The INHb pin operates Display off of LCD.
INHb control depends on set pin function.
Below table shows pin function and control by the INHb pin.
Control
Pin Function
INHb = L
INHb = H
SEG/COM
Display forced off
Display on
PWM/GPO
Operation Stop
Operation Available
Key Scan
Available regardless of INHb
External Clock Input
Available regardless of INHb
Below table shows pin name and pin state of INHb = L.
Each output state are decided by Control data(P0 to P2, KM0 to KM2, OC)
For the details, please refer to “Control Data Functions”.
Pin Function(Note) (In case of INHb = L)
Pin Name
SEG
COM
PWM
GPO
Keyscan
External
Clock Input
S1/P1/G1 to S6/P6/G6
Stop
(VSS)
-
Stop
(VSS)
Stop
(VSS)
-
-
S7 to S55, S67, S68
Stop
(VSS)
-
-
-
-
-
KS1/S56 to KS6/S61
Stop
(VSS)
-
-
-
Keyscan Output
Operation
-
KI1/S62 to KI5/S66
Stop
(VSS)
-
-
-
Keyscan
Input Operation
-
OSC/S69
Stop
(VSS)
-
-
-
-
Clock Input
Operation
COM1 to COM4
-
Stop
(VSS)
-
-
-
-
(Note) “-” means the pin does not have the function.
For example, S1/P1/G1 to S6/P6/G6 are not set COM, Keyscan and External Clock Input.
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INHb Pin and Display Control- continued
Since the IC internal data (the display data D1 to D276 and the control data) is undefined when power is first applied,
applications should set the INHb pin low at the same time as power is applied to turn off the display (This sets the S1/P1/G1
to S6/P6/G6, S7 to S69, COM1 to COM4 to the VSS level.) and during this period send serial data from the controller. The
controller should then set the INHb pin high after the data transfer has completed. This procedure prevents meaningless
displays at power on.
1. 1/4 Duty
t1
90%
VDD
(Note 1)
VDET (Min)
(Note 1)
INHb
VIL1
tC
t2
(Note 1)
VIL1
SCE
Display data and control data transfer
Internal data
D1 to D72, KM0 to KM2,
P0 to P2, FL, DR, DT, OC,
FC0 to FC2, SC, BU0 to BU2
Internal data
D73 to D156,PG1 to PG6,
PF0 to PF3
Internal data
D157 to D216, W10 to W37
Internal data
D217 to D276, W40 to W67
(Note 2)
Undefined
Default
(Note 2)
Undefined
Default
(Note 2)
Undefined
Default
Defined
Undefined
Defined
Undefined
Defined
Undefined
(Note 2)
Undefined
Undefined
Defined
Default
Figure 28. Power on/off and INHb Control Sequence (1/4 Duty)
(Note 1) t1≥0, t2≥0, tC: 10µs (Min)
When VDD level is over 90%, there may be cases where command is not received correctly in unstable VDD.
(Note 2) Display data are undefined. Regarding default value, refer to Reset Condition.
2. 1/3 Duty
(Note 3)
t1
90%
VDET (Min)
VDD
VIL1
(Note 3)
INHb
t2
tC
(Note 3)
VIL1
SCE
Internal data
D1 to D72 ,KM0 to KM2,
P0 to P2,FL,DR,DT,OC,
FC0 to FC2,SC,BU0 to BU2
Display data and control data transfer
Undefined
Internal data
D73 to D156,PG1 to PG6,
PF0 to PF3
Undefined
Internal data
D157 to D207,W10 to W37
Undefined
Internal data
W40 to W67
Undefined
(Note 4)
Default
(Note 4)
Default
Defined
Undefined
Defined
Undefined
Defined
Undefined
(Note 4)
Default
(Note 4)
Default
Defined
Undefined
Figure 29. Power ON/OFF and INHb Control Sequence (1/3 Duty)
(Note 3) t1≥0, t2≥0, tC: 10µs (Min)
When VDD level is over 90%, there may be cases where command is not received correctly in unstable VDD.
(Note 4) Display data are undefined. Regarding default value, refer to Reset Condition.
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Oscillation Stabilization Time
It must be noted that the oscillation of the internal oscillation circuit is unstable for a maximum of 100μs (oscillation
stabilization time) after oscillation has started.
Internal oscillation
circuit
Oscillation
stabilization time
(100µs Max)
Oscillation stopped
Oscillation operation
(under normal conditions)
1.If the INHb pin status is switched from "L" to "H"
when control data OC = "0" and BU0 to BU2 ="000"
2.If the contorol data BU is set from "1" to "0"
when INHb = "H" and contorol data OC ="0"
Figure 30. Oscillation Stabilization Time
Power-saving Mode Operation in External Clock Mode
After receiving [BU0,BU1,BU2]=[1,1,1], BU91520KV-M enter to power saving mode synchronized with frame then Segment
and Common pins output VSS level.
Therefore, in external clock mode, it is necessary to input the external clock based on each frame frequency setting after
sending [BU0,BU1,BU2]=[1,1,1].
For the required number of clock, refer to “6. FC0, FC1 and FC2: Common / Segment output waveform frame frequency
switching control data”.
For example, please input the external clock as below.
[FC0,FC1,FC2]=[0,0,0]: In case of fOSC/12288 setting, it needs over 12288clk,
[FC0,FC1,FC2]=[0,1,0]: In case of fOSC/9216 setting, it needs over 9216clk,
[FC0,FC1,FC2]=[1,1,1]: In case of fOSC/3072 setting, it needs over 3072clk
Please refer to the timing chart below.
SCE
SCL
SDI
0
1
0
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
Dev ice Code
8bits
D1
D2
OC
SC
BU0
Display Data/
Control Data
BU1
BU2
0
0
DD
2 bits
OSC
To input External clock at
least 1 f rame or more
SEG
VSS
COM1
VSS
COM2
VSS
COM3
VSS
COM4
VSS
Output at Power sav ing mode(VSS lev el)
Output at Normal mode
Power sav ing
Last Display f lame
of Sirial data
receiv ing
Figure 31. External Clock Stop Timing(1/4 Duty)
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Voltage Detection Type Reset Circuit (VDET)
The Voltage Detection Type Reset Circuit generates an output signal that resets the system when power is applied for
the first time and when the power supply voltage drops (that is, for example, the power supply voltage is less than or equal to
the power down detection voltage VDET=1.8V Typ.). To ensure that this reset function works properly, it is recommended
that a capacitor be connected to the power supply line so that both the power supply voltage (VDD) rise time when power is
first applied and the power supply voltage (VDD) fall time when the voltage drops are at least 1ms.
To refrain from data transmission is strongly recommended while power supply is rising up or falling down to prevent from the
occurrence of disturbances on transmission and reception
VDD
t1
t2
VDD Min
VDD Min
t3
VDD=1.0V
VSS
Figure 32. VDET Detection Timing
Power supply voltage VDD fall time: t1 > 1ms
Power supply voltage VDD rise time: t2 > 1ms
Internal reset power supply retain time: t3 > 1ms
When it is difficult to keep above conditions, it is possibility to cause meaningless display due to no IC initialization.
Please execute the IC initialization as quickly as possible after Power-on to reduce such an affect.
See the IC initialization flow as below.
But since commands are not received when the power is OFF, the IC initialization flow is not the same function as POR.
Set [BU0,BU1,BU2]=[1,1,1](power-saving mode) and SC=1(Display Off) as quickly as possible after Power-on.
BU91520KV-M can receive commands in 0ns after Power-on(VDD level is 90%).
Please refer to the timing chart of “INHb Pin and Display Control”.
Reset Condition
When BU91520KV-M is initialized,the internal status after power supply has been reset as the following table.
Instruction
Key Scan Mode
S1/P1/G1 to S6/P6/G6 Pin
LCD Bias
LCD Duty
Line / Frame Inversion Mode
Display Frame Frequency
Display Clock Mode
LCD Display
Power Mode
PWM / GPO Output
PWM Frequency
PWM Duty
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At Reset Condition
[KM0,KM1,KM2]=[1,1,1]: Key scan no use
[P0,P1,P2]=[0,0,0]:all segment output
DR=0:1/3 Bias
DT=0:1/4 Duty
FL=0:Line Inversion
[FC0,FC1,FC2]=[0,0,0]:fOSC/12288
OC=0:Internal oscillator
SC=1:OFF
[BU0,BU1,BU2]=[1,1,1]:Power saving mode
PGx=0:PWM output(x=1 to 6)
[PF0,PF1,PF2,PF3]=[0,0,0,0]: fOSC/4096
[Wn0 to Wn7]=[0,0,0,0,0,0,0,0]
1/256xTp(n=1 to 6,Tp=1/fp)
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Operational Notes
1.
Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power
supply pins.
2.
Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the
digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog
block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and
aging on the capacitance value when using electrolytic capacitors.
3.
Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.
4.
Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5.
Recommended Operating Conditions
These conditions represent a range within which the expected characteristics of the IC can be approximately
obtained. The electrical characteristics are guaranteed under the conditions of each parameter.
6.
Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow
instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power
supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring,
and routing of connections.
7.
Operation Under Strong Electromagnetic Field
Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction.
8.
Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may
subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply
should always be turned off completely before connecting or removing it from the test setup during the inspection
process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during
transport and storage.
9.
Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment)
and unintentional solder bridge deposited in between pins during assembly to name a few.
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BU91520KV-M
Operational Notes – continued
10. Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small
charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and
cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the
power supply or ground line.
11. Regarding the Input Pin of the IC
In the construction of this IC, P-N junctions are inevitably formed creating parasitic diodes or transistors. The
operation of these parasitic elements can result in mutual interference among circuits, operational faults, or physical
damage. Therefore, conditions which cause these parasitic elements to operate, such as applying a voltage to an
input pin lower than the ground voltage should be avoided. Furthermore, do not apply a voltage to the input pins when
no power supply voltage is applied to the IC. Even if the power supply voltage is applied, make sure that the input pins
have voltages within the values specified in the electrical characteristics of this IC.
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BU91520KV-M
Ordering Information
B
U
9
1
5
2
0
Part Number
K
V
Package
KV : VQFP80
-
ME2
Product Rank
M: for Automotive
Packaging Specification
E2: Embossed tape and reel
Marking Diagram
VQFP80 (TOP VIEW)
Part Number Marking
LOT Number
BU91520KV
Pin 1 Mark
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BU91520KV-M
Physical Dimension, Tape and Reel Information
VQFP80
Package Name
1PIN MARK
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BU91520KV-M
Revision History
Version
001
002
003
Date
Description
22.Jan.2016 New Release
Page 3. Modify Temparature condition in Absolute Maximum Ratings.Ta=25˚C → Removed
Page 3. Modify Maximum Supply Voltage in Absolute Maximum Ratings. -0.3 to +6.5 → -0.3 to +7.0.
Page 3. Modify Input Voltage in Absolute Maximum Ratings. -0.3 to +6.5 → -0.3 to +7.0.
Page 3. Add OSC in Absolute Maximum Ratings Input Voltage.
Page 3. Add Caution2 in Absolute Maximum Ratings condition. (Moved from Operational Notes)
Page.3. Add OSC pin in Electrical Characteristics table.
Page 4. Add External Clock Rise Time and External Clock Fall Time in Oscillation Characteristics.
Page 5. Add KI1/S62 to KI5/S66 in Pin Description I/O and Handling when unused Input terminal
description.
Page 5. Add OSC/S69 in Pin Description I/O and Handling when unused Input terminal description.
26.Jan.2018
Page 11 to 14. Add Reset condition in Control Data Functions.
Page 11. Add 4. FL: Line Inversion or Frame Inversion control data explanation.
Page 12. Add External Clock input timing function in 7. OC: Internal oscillator operating mode /
External clock operating mode control data.
Page 34. Modify Figure 28. Power on/off and INHb Control Sequence (1/4 Duty).
Page 34. Modify Figure 29. Power on/off and INHb Control Sequence (1/3 Duty).
Page 35. Add Power-saving mode operation in external clock mode.
Page 36. Add Voltage Detection Type Reset Circuit (VDET) explanation.
Correction of errors.
Minor translation to have more conformity between Japanese and English version.
Page.6 Add Pin Description Note
18.Jul.2019 Page.8,10,and 12 Add Description
Page.34 Add INHb Pin and Display Control description
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Notice
Precaution on using ROHM Products
1.
If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment (Note 1),
aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,
bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales
representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any
ROHM’s Products for Specific Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅣ
CLASSⅢ
2.
ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3.
Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below.
Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the
use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our
Products under any special or extraordinary environments or conditions (as exemplified below), your independent
verification and confirmation of product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used.
However, recommend sufficiently about the residue.); or Washing our Products by using water or water-soluble
cleaning agents for cleaning residue after soldering
[h] Use of the Products in places subject to dew condensation
4.
The Products are not subject to radiation-proof design.
5.
Please verify and confirm characteristics of the final or mounted products in using the Products.
6.
In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7.
De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in
the range that does not exceed the maximum junction temperature.
8.
Confirm that operation temperature is within the specified range described in the product specification.
9.
ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1.
When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2.
In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PAA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.004
Precautions Regarding Application Examples and External Circuits
1.
If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2.
You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1.
Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl 2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2.
Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3.
Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4.
Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
trade act, please consult with ROHM in case of export.
Precaution Regarding Intellectual Property Rights
1.
All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data.
2.
ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the
Products with other articles such as components, circuits, systems or external equipment (including software).
3.
No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM
will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to
manufacture or sell products containing the Products, subject to the terms and conditions herein.
Other Precaution
1.
This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2.
The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3.
In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4.
The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice-PAA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.004
Datasheet
General Precaution
1. Before you use our Products, you are requested to carefully read this document and fully understand its contents.
ROHM shall not be in any way responsible or liable for failure, malfunction or accident arising from the use of any
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this document is current as of the issuing date and subject to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the latest information with a ROHM sales
representative.
3.
The information contained in this document is provided on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate and/or error-free. ROHM shall not be in any way responsible or
liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccuracy or errors of or
concerning such information.
Notice – WE
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