Datasheet
Low Duty LCD Segment Driver
for Automotive Application
BU91797xxx-M Series
MAX 144 Segments (SEG36×COM4)
General Description
Key Specifications
■
■
■
■
■
■
BU91797MUF-M and BU91797FUV-M are a 1/4 duty
general-purpose LCD driver that can be used for
automotive applications and can drive up to 144 LCD
Segments.
It can support operating temperature of up to +105°C and
qualified for AEC-Q100 Grade2, as required for
automotive applications.
Wettable flank QFN package is suitable for small
footprint
applications
and
provides
significant
advantages in inspectability and solder joint reliability.
Special Characteristics
■
■
Features
Supply Voltage Range:
+2.5V to +6.0V
Operating Temperature Range:
-40°C to +105°C
Max Segments:
144Segments
Display Duty:
1/4
Bias:
1/3
Interface:
2wire Serial Interface
ESD(HBM):
Latch-up Current:
Package
W (Typ) x D (Typ) x H (Max)
AEC-Q100 Qualified (Note)
Integrated RAM for Display Data (DDRAM):
36 x 4 bit (Max 144 Segment)
LCD Drive Output:
4 Common Output, Max 36 Segment Output
Integrated Buffer AMP for LCD Driving
Integrated Oscillator Circuit
No External Components
Low Power Consumption Design
(Note) Grade 2
VQFN48FV7070
7.0mm x 7.0mm x 1.0mm
Applications
etc.
±2000V
±100mA
Instrument Clusters
Climate Controls
Car Audios / Radios
Metering
White Goods
Healthcare Products
Battery Operated Applications
TSSOP-C48V
12.5mm x 8.1mm x 1.0mm
Typical Application Circuit
VDD
C > 0.1μF
VDD
VLCD
COM0
COM1
COM2
COM3
SDA
SCL
Controller
SEG0
SEG1
・・
・・
・・
・
SEG35
OSCIN
TEST1
TEST2
VSS
Insert Capacitors
between VDD and VSS
Segment
LCD
・・
・・
・
・
・
Internal Clock Mode
Figure 1. Typical Application Circuit
〇Product structure : Silicon monolithic integrated circuit
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Datasheet
MAX 144 segments (SEG36×COM4)
Block Diagram / Pin Configuration / Pin Description
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
31
30
29
28
27
26
25
SEG22
VLCD
40
21
SEG21
VDD
41
20
SEG20
VSS
42
19
SEG19
TEST1
43
18
SEG18
OSCIN
44
17
SEG17
SCL
45
16
SEG16
SDA
46
15
SEG15
TEST2
47
14
SEG14
SEG0
48
13
SEG13
TEST1
SDA
TEST2
10
SEG10
12
9
SEG9
SEG12
8
SEG8
11
7
SEG7
IF FILTER
VSS
SEG11
6
Serial Interface
EXT-PAD
SEG6
Power On Reset
32
22
5
OSCILLATOR
SEG34
39
SEG5
OSCIN
33
SEG23
COM3
4
Command
Data Decoder
Command
Register
34
SEG24
23
DDRAM
VLCD
COM0
24
38
3
－
Blink Timing
Generator
SEG35
37
COM2
SEG4
Common
Counter
＋
35
COM1
LCD
BIAS
SELECTOR
SEG3
＋
－
2
Segment
Driver
1
Common
Driver
LCD voltage generator
SEG2
SEG0 …… SEG35
SEG1
COM 0……COM3
VDD
36
BU91797MUF-M
SCL
Figure 2. Block Diagram
Figure 3. Pin Configuration (TOP VIEW)
Table 1. Pin Description
Pin Name
Pin No.
I/O
TEST1
43
I
TEST2
47
I
OSCIN
44
I
SDA
46
I/O
SCL
45
VSS
Handling
when unused
Function
Test input (ROHM use only)
Must be connected to VSS
VSS
POR enable setting
VDD: POR disenable (Note 1)
VSS: POR enable
External clock input
External clock and Internal clock can be selected by command
Must be connected to VSS when using internal oscillator
VSS
VSS
Serial data in-out terminal
-
I
Serial clock terminal
-
42
-
GND
-
VDD
41
-
Power supply
-
VLCD
40
-
Power supply for LCD driving
-
SEG0 to SEG35
1 to 35,
48
O
SEGMENT output for LCD driving
OPEN
COM0 to COM3
36 to 39
O
COMMON output for LCD driving
OPEN
EXT-PAD
(Note 2)
-
Substrate
OPEN/VSS
(Note 1) This function is guaranteed by design, not tested in production process. Software Reset is necessary to initialize IC in case of TEST2=VDD.
(Note 2) To radiate heat, Contact a board with the EXT-PAD which is located at the bottom side of VQFN48FV7070 package.
Supply VSS level or Open state as the input condition for this PAD.
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Datasheet
MAX 144 segments (SEG36×COM4)
Block Diagram / Pin Configuration / Pin Description – continued
BU91797FUV-M
COM 0……COM3
SEG0 …… SEG35
SEG31
SEG30
SEG32
SEG29
SEG33
SEG28
SEG34
SEG27
SEG35
SEG26
COM0
SEG25
COM1
SEG24
COM2
SEG23
COM3
SEG22
VLCD
SEG21
VDD
SEG20
VSS
SEG19
TEST1
SEG18
OSCIN
SEG17
SCL
SEG16
SDA
SEG15
TEST2
SEG14
SEG0
SEG13
SEG1
SEG12
SEG2
SEG11
SEG3
SEG10
SEG4
SEG9
SEG5
SEG8
SEG6
SEG7
VDD
LCD voltage generator
＋
－
Common
Driver
Segment
Driver
LCD
BIAS
SELECTOR
Common
Counter
＋
－
Blink Timing
Generator
DDRAM
VLCD
Command
Data Decoder
Command
Register
OSCIN
OSCILLATOR
Power On Reset
Serial Interface
IF FILTER
VSS
TEST1
SDA
TEST2
SCL
Figure 4. Block Diagram
Figure 5. Pin Configuration (TOP VIEW)
Table 2. Pin Description
Pin Name
Pin No.
I/O
TEST1
13
I
TEST2
17
I
OSCIN
14
I
SDA
16
I/O
SCL
15
VSS
Handling
when unused
Function
Test input (ROHM use only)
Must be connected to VSS
VSS
POR enable setting
VDD: POR disenable (Note)
VSS: POR enable
External clock input
External clock and Internal clock can be selected by command
Must be connected to VSS when using internal oscillator
VSS
VSS
Serial data in-out terminal
-
I
Serial clock terminal
-
12
-
GND
-
VDD
11
-
Power supply
-
VLCD
10
-
Power supply for LCD driving
-
SEG0 to SEG35
18 to 48,
1 to 5
O
SEGMENT output for LCD driving
OPEN
COM0 to COM3
6 to 9
O
COMMON output for LCD driving
OPEN
(Note) This function is guaranteed by design, not tested in production process. Software Reset is necessary to initialize IC in case of TEST2=VDD.
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Datasheet
MAX 144 segments (SEG36×COM4)
Absolute Maximum Ratings (VSS=0V)
Parameter
Symbol
Ratings
Unit
Remarks
Maximum Voltage1
VDD
-0.5 to +7.0
V
Power Supply
Maximum Voltage2
VLCD
-0.5 to VDD
V
LCD Drive Voltage
0.93(Note 1)
W
BU91797MUF-M
0.64(Note 2)
W
BU91797FUV-M
Power Dissipation
Pd
Input Voltage Range
Operational Temperature
Range
Storage Temperature Range
VIN
-0.5 to VDD+0.5
V
Topr
-40 to +105
°C
Tstg
-55 to +125
°C
(Note 1) Derate by 9.3mW/°C when operating above Ta=+25°C (when mounted in ROHM’s standard board).
(Note 2) Derate by 6.4mW/°C when operating above Ta=+25°C (when mounted in ROHM’s standard board).
Caution: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated over
the absolute maximum ratings.
Recommended Operating Conditions (Ta=-40°C to +105°C, VSS=0V)
Parameter
Symbol
Ratings
Min
Typ
Max
Unit
Remarks
Power Supply Voltage1
VDD
2.5
-
6.0
V
Power Supply
Power Supply Voltage2
VLCD
0
-
VDD-2.4
V
LCD Drive Voltage, VDD-VLCD 2.4V
Electrical Characteristics
DC Characteristics (VDD=2.5V to 6.0V, VLCD=0V, VSS=0V, Ta=-40°C to +105°C, unless otherwise specified)
Limits
Parameter
Symbol
Unit
Conditions
Min
Typ
Max
“H” Level Input Voltage
VIH
0.7VDD
-
VDD
V
SDA, SCL, OSCIN
“L” Level Input Voltage
VIL
VSS
-
0.3VDD
V
SDA, SCL, OSCIN
“H” Level Input Current
IIH
-
-
1
µA
SDA, SCL, OSCIN(Note 3), TEST2
“L” Level Input Current
IIL
-1
-
-
µA
SDA, SCL, OSCIN, TEST2
VOL_SDA
0
-
0.4
V
Iload = 3mA
SEG
RON
-
3
-
kΩ
COM
RON
-
3
-
kΩ
VLCD
0
-
VDD-2.4
V
VDD-VLCD2.4V
Standby Current
IDD1
-
-
5
µA
Display off, Oscillation off
Power Consumption
IDD2
-
12.5
30
µA
VDD=3.3V, VLCD=0V, Ta=+25°C
Power save mode1, FR=71Hz
1/3 bias, Frame inverse
SDA “L” Level Output Voltage
LCD Driver On
Resistance
VLCD Supply Voltage
Iload=±10µA
(Note 3) For external clock mode only.
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Datasheet
MAX 144 segments (SEG36×COM4)
Electrical Characteristics – continued
Oscillation Characteristics (VDD=2.5V to 6.0V, VLCD=0V, VSS=0V, Ta=-40°C to +105°C, unless otherwise specified)
Limits
Parameter
Symbol
Unit
Conditions
Min
Typ
Max
FR = 80Hz setting,
Frame Frequency1
fCLK1
56
80
112
Hz
VDD=2.5V to 6.0V, Ta=-40°C to +105°C
FR = 80Hz setting, VDD=3.3V,
Frame Frequency2
fCLK2
70
80
90
Hz
Ta=+25°C
FR = 80Hz setting, VDD=5.0V,
Frame Frequency3
fCLK3
77.5
87.5
97.5
Hz
Ta=+25°C
FR = 80Hz setting, VDD=5.0V,
Frame Frequency4
fCLK4
67.5
87.5
108
Hz
Ta=-40°C to +105°C
External Clock Rise Time
tr
0.3
µs
External Clock Fall Time
tf
-
-
0.3
µs
External Frequency
fEXCLK
15
-
300
kHz
External Clock Duty
tDTY
30
50
70
%
(Note)
DISCTL 80HZ setting: Frame frequency [Hz] = external clock [Hz]
DISCTL 71HZ setting: Frame frequency [Hz] = external clock [Hz]
DISCTL 64HZ setting: Frame frequency [Hz] = external clock [Hz]
DISCTL 53HZ setting: Frame frequency [Hz] = external clock [Hz]
External clock mode (OSCIN) (Note)
/ 512
/ 576
/ 648
/ 768
[Reference Data]
110
Frame Frequency [Hz]
100
VDD = 6.0V
VDD = 5.0V
90
VDD = 3.3V
80
VDD = 2.7V
70
60
50
-40 -20
0
20
40
60
80 100
Temperature [°C]
Figure 6. Frame Frequency Typical Temperature Characteristics
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Datasheet
MAX 144 segments (SEG36×COM4)
Electrical Characteristics - continued
MPU interface Characteristics (VDD=2.5V to 6.0V, VLCD=0V, VSS=0V, Ta=-40°C to +105°C, unless otherwise specified)
Limits
Parameter
Symbol
Unit
Conditions
Min
Typ
Max
Input Rise Time
tr
-
-
0.3
µs
Input Fall Time
tf
-
-
0.3
µs
SCL Cycle Time
tSCYC
2.5
-
-
µs
“H” SCL Pulse Width
tSHW
0.6
-
-
µs
“L” SCL Pulse Width
tSLW
1.3
-
-
µs
SDA Setup Time
tSDS
100
-
-
ns
SDA Hold Time
tSDH
100
-
-
ns
Buss Free Time
tBUF
1.3
-
-
µs
tHD;STA
0.6
-
-
µs
START Condition Setup Time
tSU;STA
0.6
-
-
µs
STOP Condition Setup Time
tSU;STO
0.6
-
-
µs
START Condition Hold Time
SDA
tf
tSLW
tBUF
tSCYC
SCL
tHD;STA
tr
tSDH
t SHW
tSDS
SDA
tSU;STO
tSU;STA
Figure 7. Interface Timing
I/O Equivalence Circuit
VDD
VDD
VLCD
VSS
VSS
SDA
SCL
VSS
VSS
VDD
VDD
TEST1
TEST2
VSS
VSS
VDD
VDD
OSCIN
SEG/COM
VSS
VSS
Figure 8 I/O Equivalence Circuit
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Datasheet
MAX 144 segments (SEG36×COM4)
Application Example
VDD
VDD
VLCD
COM
COM
COM
COM
0
1
2
3
SDA
SCL
Controller
SEG 0
SEG 1
・
・
・
・
・
・
・
OSCIN
TEST 1
TEST 2
VSS
Segment
LCD
・
・
・
・
・
・
・
SEG 35
Internal Clock Mode
VDD
VDD
VLCD
Controller
COM 0
COM 1
COM 2
COM 3
SDA
SCL
SEG 0
SEG 1
・
・・
・
・
・
・
SEG 35
OSCIN
TEST 1
TEST 2
VSS
Segment
LCD
・
・
・
・
・
・
・
External Clock Mode
Figure 9. Example of Application Circuit
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Datasheet
MAX 144 segments (SEG36×COM4)
Functional Descriptions
Command / Data Transfer Method
BU91797MUF-M and BU91797FUV-M are controlled by 2wire signal (SDA, SCL).
SDA
SCL
START condition
STOP condition
Figure 10. 2 wire Command / Data Transfer Format
It is necessary to generate START and STOP condition when sending command or Display Data through this 2 wire serial
interface.
Slave Address
S 0 1 1 1 1 1 0 0
11 10 9 8 7 6 5 4 3
A
Command
A C
A P
Display Data
1 0
2 12
Command or Data judgment bit
START condition
STOP condition
Acknowledge
Figure 11. Interface Protcol
Slave Address = “01111100”: Write Mode
The following procedure shows how to transfer command and Display Data.
(1) Generate “START condition”.
(2) Issue Slave Address.
(3) Transfer command and Display Data.
(4) Generate “STOP condition”
Acknowledge (ACK)
Data format is comprised of 8 bits, Acknowledge bit is returned after sending 8-bit data.
After the transfer of 8-bit data (Slave Address, Command, Display Data), release the SDA line at the falling edge of the 8th
clock. The SDA line is then pulled “Low” until the falling edge of the 9th clock SCL.
(Output cannot be pulled “High” because of open drain NMOS).
If acknowledge function is not required, keep SDA line at “Low” level from 8th falling edge to 9th falling edge of SCL.
SDA
1 to 7
8
9
1 to 7
8
9
1 to 7
8
9
SCL
S
P
Slave Address
ACK
DATA
ACK
START
condition
DATA
ACK
STOP
condition
Figure 12. Acknowledge Timing
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MAX 144 segments (SEG36×COM4)
Functional Descriptions - continued
Command Transfer Method
Issue Slave Address (“01111100”) after generating “START condition”.
The 1st byte after Slave Address always becomes command input.
MSB (“command or data judge bit”) of command decide to next data is command or Display Data.
When set “command or data judge bit”=‘1’, next byte will be command.
When set “command or data judge bit”=‘0’, next byte data is Display Data.
S Slave Address A 1 Command A
1 Command A
1 Command A
0 Command A Display Data
… P
It cannot accept input command once it enters into Display Data transfer state.
In order to input command again it is necessary to generate “START condition”.
If “START condition” or “STOP condition” is sent in the middle of command transmission, command will be cancelled.
If Slave Address is continuously sent following “START condition”, it remains in command input state.
“Slave Address” must be sent right after the “START condition”.
When Slave Address cannot be recognized in the first data transmission, no Acknowledge bit is generated and next
transmission will be invalid. When data is invalid status, if “START condition” is transmitted again, it will return to valid
status.
Consider the MPU interface characteristic such as Input rise time and Setup/Hold time when transferring command and
data (Refer to MPU Interface Characteristics).
Write Display and Transfer Method
BU91797MUF-M and BU91797FUV-M have Display Data RAM (DDRAM) of 36×4=144bit.
The relationship between data input and Display Data, DDRAM Data and address are as follows;
Slave Address
S
01111100
Command
A
0
0000000
A
a
b c
d
e f
g h A
i
j
k l m
n o p
A
… P
Display Data
8-bit data is stored in DDRAM. ADSET command specifies the address to be written, and address is automatically
incremented in every 4-bit data.
Data can be continuously written in DDRAM by transmitting data continuously.
When RAM data is written successively, after writing RAM data to 23h (SEG35), the address is returned to 00h (SEG0) by
the auto-increment function.
BIT
01h
02h
03h
0
a
e
i
m
COM0
1
b
f
j
n
COM1
2
c
g
k
o
COM2
3
d
h
l
p
SEG0
SEG1
SEG2
SEG3
04h
DDRAM address
05h
06h
07h
00h
...
21h
22h
23h
COM3
SEG4
SEG5
SEG6
SEG7
SEG33
SEG34
SEG35
Display Data is written to DDRAM every 4-bit data.
No need to wait for ACK bit to complete data transfer.
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MAX 144 segments (SEG36×COM4)
Functional Descriptions - continued
Oscillator
The clock signals for logic and analog circuit can be generated from internal oscillator or external clock.
If internal oscillator circuit is used, OSCIN must be connected to VSS level.
When using external clock mode, input external clock to OSCIN terminal after ICSET command setting.
OSCIN
OSCIN
BU91797xxx-M
VSS
BU91797xxx-M
VSS
Figure 13. Internal Clock Mode
Clock
Figure 14. External Clock Mode
LCD Driver Bias Circuit
BU91797MUF-M and BU91797FUV-M generate LCD driving voltage with on-chip Buffer AMP.
And it can drive LCD at low power consumption.
Line or frame inversion can be set by DISCTL command.
Refer to the “LCD Driving Waveform” for each LCD bias setting.
Blink Timing Generator
BU91797MUF-M and BU91797FUV-M have Blink function.
Blink mode is asserted by BLKCTL command.
The Blink frequency varies depending on fCLK characteristics at internal clock mode.
Refer to Oscillation Characteristics for fCLK.
Reset Initialize Condition
Initial condition after executing Software Reset is as follows.
- Display is OFF.
- DDRAM address is initialized (DDRAM Data is not initialized).
Refer to Command Description for initial value of registers.
Command / Function List
Description List of Command / Function
No.
Command
Function
1
Set IC Operation (ICSET)
Software Reset, internal/external clock setting
2
Display Control (DISCTL)
Frame frequency, power save mode setting
3
Address Set (ADSET)
DDRAM address setting (00h to 23h)
4
Mode Set (MODESET)
Display on/off, 1/3bias setting
5
Blink Control (BLKCTL)
Blink off/0.5Hz/1Hz/2Hz Blink setting
6
All Pixel Control (APCTL)
All pixels on/off during DISPON
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MAX 144 segments (SEG36×COM4)
Functional Descriptions - continued
Detailed Command Description
D7 (MSB) is a command or data judgment bit.
Refer to Command / Data Transfer Method.
C:
0: Next byte is RAM write data.
1: Next byte is command.
Set IC Operation (ICSET)
MSB
D7
D6
D5
C
1
1
D4
0
D3
1
D2
P2
D1
P1
LSB
D0
P0
P2: MSB data of DDRAM address. Refer to “ADSET” command.
Set software reset execution.
Setup
P1
Software Reset Not Execute
0
Software Reset Execute
1
When “Software Reset” is executed, BU91797MUF-M and BU91797FUV-M are reset to initial condition.
(Refer to Reset initialize condition)
Don’t set Software Reset (P1) with P2, P0 at the same time.
Set oscillator mode
Setup
Internal clock
P0
Reset initialize condition
0
○
External clock
1
Internal clock mode: OSCIN must be connected to VSS level.
External clock mode: Input external clock to OSCIN terminal.
-
DISCTL 80Hz setting: Frame frequency [Hz] = external clock [Hz] / 512
DISCTL 71Hz setting: Frame frequency [Hz] = external clock [Hz] / 576
DISCTL 64Hz setting: Frame frequency [Hz] = external clock [Hz] / 648
DISCTL 53Hz setting: Frame frequency [Hz] = external clock [Hz] / 768
Command
OSCIN_EN
(Internal signal)
ICSET
Internal clock mode
External clock mode
Internal oscillation
(Internal signal)
External clock
(OSCIN)
Figure 15. OSC MODE Switch Timing
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BU91797xxx-M Series
Datasheet
MAX 144 segments (SEG36×COM4)
Functional Descriptions - continued
Display Control (DISCTL)
MSB
D7
D6
D5
C
0
1
D4
P4
D3
P3
Set Power save mode FR.
Setup
D2
P2
D1
P1
LSB
D0
P0
P4
P3
Reset initialize condition
Normal mode (80Hz)
0
0
○
Power save mode 1 (71Hz)
0
1
-
Power save mode 2 (64Hz)
1
0
-
Power save mode 3 (53Hz)
1
1
Power consumption is reduced in the following order:
Normal mode > Power save mode1 > Power save mode 2 > Power save mode 3
Set LCD drive waveform.
Setup
P2
Reset initialize condition
Line inversion
0
○
Frame inversion
1
-
Power consumption is reduced in the following order:
Line inversion > Frame inversion
Typically, when driving large capacitance LCD, Line inversion will increase the influence of crosstalk.
Regarding driving waveform, refer to LCD Driving Waveform.
Set Power save mode SR.
Setup
P1
P0
Reset initialize condition
Power save mode 1
0
0
-
Power save mode 2
0
1
-
Normal mode
1
0
○
High power mode
1
1
Power consumption is increased in the following order:
Power save mode 1 < Power save mode 2 < Normal mode < High power mode
Use VDD- VLCD ≥ 3.0V in High power mode condition.
(Reference current consumption data)
Setup
Current consumption
Power save mode 1
×0.5
Power save mode 2
×0.67
Normal mode
×1.0
High power mode
×1.8
The data above is for reference only. Actual consumption depends on Panel load.
Address Set (ADSET)
MSB
D7
D6
D5
C
0
0
D4
D3
D2
D1
LSB
D0
P4
P3
P2
P1
P0
The range of address can be set from 000000 to 100011(bin).
Internal register
Command
MSB
Address
[5]
ICSET
P2
Address
[4]
ADSET
P4
Address
[3]
ADSET
P3
Address
[2]
ADSET
P2
Address
[1]
ADSET
P1
LSB
Address
[0]
ADSET
P0
Address [5:0]: MSB bit is specified as ICSET P2 and [4:0] are specified as ADSET P4 to P0.
Don’t set out of range address, otherwise address will be set to 000000.
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Datasheet
MAX 144 segments (SEG36×COM4)
Functional Descriptions - continued
Mode Set (MODESET)
MSB
D7
D6
D5
C
1
0
D4
*
D3
P3
D2
0
D1
*
LSB
D0
*
(*: Don’t care)
Set display off and on.
Setup
P3
Reset initialize condition
Display off (DISPOFF)
0
○
Display on (DISPON)
1
-
Display off:
Regardless of DDRAM data, all SEGMENT and COMMON output will be stopped after 1frame of
OFF data write. Display off mode will be disabled after Display on command.
SEGMENT and COMMON output will be active and start to read the Display Data from DDRAM.
Display on:
Set bias level
Setup
1/3 Bias
Prohibit
Refer to LCD Driving Waveform.
Blink Control (BLKCTL)
MSB
D7
D6
D5
C
1
1
P2
Reset initialize condition
0
○
1
-
D4
D3
D2
D1
LSB
D0
1
0
*
P1
P0
(*: Don’t care)
Set Blink mode.
Blink mode (Hz)
P1
P0
Reset initialize condition
OFF
0
0
○
0.5
0
1
-
1.0
1
0
-
2.0
1
1
The Blink frequency varies depending on fCLK characteristics at internal clock mode.
Refer to Oscillation Characteristics for fCLK.
All Pixel Control (APCTL)
MSB
D7
D6
D5
C
1
1
D4
1
D3
1
D2
1
D1
P1
LSB
D0
P0
All display set ON, OFF
Setup
P1
Reset initialize condition
Normal
0
○
All pixel on (APON)
1
-
Setup
P0
Reset initialize condition
Normal
0
○
All pixel off (APOFF)
1
All pixels on: All pixels are ON regardless of DDRAM data.
All pixels off: All pixels are OFF regardless of DDRAM data.
This command is valid in Display on status. The data of DDRAM is not changed by this command.
If set both P1 and P0 =”1”, APOFF will be selected.
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Datasheet
MAX 144 segments (SEG36×COM4)
LCD Driving Waveform
(1/3bias)
Line Inversion
Frame Inversion
SEGn SEGn+1 SEGn+2 SEGn+3
SEGn SEGn+1 SEGn+2 SEGn+3
COM0
stateA
COM0
stateA
COM1
stateB
COM1
stateB
COM2
COM2
COM3
COM3
1frame
1frame
VDD
COM0
VDD
COM0
VLCD
VLCD
VDD
COM1
VDD
COM1
VLCD
VLCD
VDD
COM2
VDD
COM2
VLCD
VLCD
VDD
VDD
COM3
COM3
VLCD
VLCD
VDD
SEGn
VDD
SEGn
VLCD
VLCD
VDD
SEGn+1
VDD
SEGn+1
VLCD
VLCD
VDD
SEGn+2
VDD
SEGn+2
VLCD
VLCD
VDD
VDD
SEGn+3
SEGn+3
VLCD
VLCD
stateA
(COM0-SEGn)
stateA
(COM0-SEGn)
(VDD-VLCD)
2/3 (VDD-VLCD)
1/3 (VDD-VLCD)
0
(VDD-VLCD)
2/3 (VDD-VLCD)
1/3 (VDD-VLCD)
0
-1/3 (VDD-VLCD)
-2/3 (VDD-VLCD)
- (VDD-VLCD)
-1/3 (VDD-VLCD)
-2/3 (VDD-VLCD)
- (VDD-VLCD)
stateB
(COM1-SEGn)
(VDD-VLCD)
stateB
(COM1-SEGn)
2/3 (VDD-VLCD)
(VDD-VLCD)
1/3 (VDD-VLCD)
2/3 (VDD-VLCD)
0
1/3 (VDD-VLCD)
-1/3 (VDD-VLCD)
0
-2/3 (VDD-VLCD)
-1/3 (VDD-VLCD)
- (VDD-VLCD)
-2/3 (VDD-VLCD)
-(VDD-VLCD)
Figure 16. LCD Waveform at Line Inversion (1/3bias)
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Figure 17. LCD Waveform at Frame Inversion (1/3bias)
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BU91797xxx-M Series
Datasheet
MAX 144 segments (SEG36×COM4)
Example of Display Data
If LCD layout pattern is like Figure 18 and Figure 19, and display pattern is like Figure 20,
Display Data will be shown as below.
COM0
COM1
COM2
COM3
Figure 18. Example COM Line Pattern
SEG1 SEG3
SEG2
SEG5 SEG7
SEG4 SEG6 SEG8
SEG9
SEG10
Figure 19. Example SEG Line Pattern
Figure 20. Example Display Pattern
S
E
G
0
S
E
G
1
S
E
G
2
S
E
G
3
S
E
G
4
S
E
G
5
S
E
G
6
S
E
G
7
S
E
G
8
S
E
G
9
S
E
G
10
S
E
G
11
S
E
G
12
S
E
G
13
S
E
G
14
S
E
G
15
S
E
G
16
S
E
G
17
S
E
G
18
S
E
G
19
COM0
D0
0
1
1
0
1
1
1
1
0
1
1
0
0
0
0
0
0
0
0
0
COM1
D1
0
0
1
1
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
COM2
D2
0
0
0
1
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
0
COM3
D3
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
Address
00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h
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Datasheet
MAX 144 segments (SEG36×COM4)
Initialize Sequence
Follow the Power-on sequence below to initialize condition.
Power on
↓
STOP condition
↓
START condition
↓
Issue Slave Address
↓
Execute Software Reset by sending ICSET command.
After Power-on and before sending initialize sequence, each register value, DDRAM address and DDRAM Data are
random.
Start Sequence
Start Sequence Example1
No.
Input
2
3
4
5
6
7
8
9
10
D5
D4
D3
D2
D1
D0
Power on
↓
Wait min100µs
↓
STOP
↓
START
↓
Slave Address
↓
ICSET
↓
BLKCTL
↓
DISCTL
↓
ICSET
↓
ADSET
↓
Display Data
Display Data
Descriptions
VDD=0V→5V
(Tr: Min 1ms to Max 500ms)
Initialize BU91797xxx-M
STOP condition
START condition
0
1
1
1
1
1
0
0
Issue Slave Address
1
1
1
0
1
0
1
0
Software Reset
1
1
1
1
0
*
0
0
Blink off
1
0
1
0
0
1
0
0
80Hz, Frame inv., Power save mode1
1
1
1
0
1
*
0
1
External clock input
0
0
0
0
0
0
0
0
RAM address set
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
address
address
00h to 01h
02h to 03h
*
*
*
*
*
*
*
*
address
22h to 23h
…
11
D6
…
1
D7
Display Data
↓
12
STOP
↓
13
START
↓
14
Slave Address
↓
15
MODESET
↓
16
STOP
(*: Don’t care)
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STOP condition
START condition
0
1
1
1
1
1
0
0
Issue Slave Address
1
1
0
*
1
0
*
*
Display on
STOP condition
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BU91797xxx-M Series
MAX 144 segments (SEG36×COM4)
Datasheet
Start Sequence Example2
Initialize
Initialize Sequence
DISPON
DISPON Sequence
RAM Write
RAM Write Sequence
DISPOFF
DISPOFF Sequence
BU91797MUF-M and BU91797FUV-M are initialized with Start Sequence, start to display with “DISPON Sequence”,
update Display Data with “RAM Write Sequence” and stop the display with “DISPOFF Sequence”.
Execute “DISPON Sequence” in order to restart display.
Initialize Sequence
Input
DATA
Description
D7 D6 D5 D4 D3 D2 D1 D0
Power on
Wait 100μs
STOP
START
Slave Address
ICSET
MODESET
ADSET
Display Data
…
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
*
*
*
*
*
*
*
*
Execute Software Reset
Display off
RAM address set
Display Data
STOP
DISPON Sequence
Input
DATA
Description
D7 D6 D5 D4 D3 D2 D1 D0
START
Slave Address
ICSET
DISCTL
BLKCTL
APCTL
MODESET
0
1
1
1
1
1
0
0
1
1
1
0
1
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
0
0
0
Execute internal OSC mode
Set Display Control
Set BLKCTL
Set APCTL
Display on
STOP
RAM Write Sequence
DATA
Input
Description
D7 D6 D5 D4 D3 D2 D1 D0
START
Slave Address
ICSET
DISCTL
BLKCTL
APCTL
MODESET
ADSET
Display Data
…
STOP
0
1
1
1
1
1
0
0
1
1
1
0
1
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
*
*
*
*
*
*
*
*
Execute internal OSC mode
Set Display Control
Set BLKCTL
Set APCTL
Display on
RAM address set
Display Data
DISPOFF Sequence
Input
DATA
Description
D7 D6 D5 D4 D3 D2 D1 D0
START
Slave Address
ICSET
MODESET
STOP
0
1
1
1
1
1
0
0
1
1
1
0
1
0
0
0
1
1
0
0
0
0
0
0
Execute internal OSC mode
Display off
Abnormal operation may occur in BU91797MUF-M and BU91797FUV-M due to the effect of noise or other external factor.
To avoid this phenomenon, it is highly recommended to input command according to sequence described above during
initialization, display on/off and refresh of RAM data.
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MAX 144 segments (SEG36×COM4)
Datasheet
Cautions in Power ON/OFF
To prevent incorrect display, malfunction and abnormal current, follow Power On/Off sequence shown in waveform below.
VDD must be turned on before VLCD during power up sequence.
VDD must be turned off after VLCD during power down sequence.
Set VDD-2.4≥ VLCD, t1>0ns and t2>0ns.
To refrain from data transmission is strongly recommended while power supply is rising up or falling down to prevent from
the occurrence of disturbances on transmission and reception.
t1
VLCD
VDD
t2
10%
10%
VDD min
VDD min
Figure 21. Power ON/OFF Waveform
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Datasheet
MAX 144 segments (SEG36×COM4)
Caution in POR Circuit Use
BU91797MUF-M and BU91797FUV-M have “POR” (Power-on Reset) circuit and Software Reset function.
Keep the following recommended Power-on conditions in order to power up properly.
Set power up conditions to meet the recommended t R, tF, tOFF, and VBOT specification below in order to ensure P.O.R
operation.
Set pin TEST2=”L” to enable POR circuit.
VDD
tF
tR
tOFF
VBOT
Recommended condition of tR, tF, tOFF, VBOT (Ta=+25°C)
tR(Note)
tF(Note)
tOFF(Note)
VBOT(Note)
1ms
1ms
Less than
Min 20ms
to 500ms to 500ms
0.1V
(Note) This function is guaranteed by design, not tested in production process.
Figure 21. Power ON/OFF Waveform
When it is difficult to keep above conditions, it is possibility to cause meaningless display due to no IC initialization.
Please execute the IC initialization as quickly as possible after Power-on to reduce such an affect.
See the IC initialization flow as below.
Setting TEST2="H" disables the POR circuit, in such case, execute the following sequence.
Note however that it cannot accept command while supply is unstable or below the minimum supply range.
Note also that software reset is not a complete alternative to POR function.
1. Generate STOP Condition
VDD
SDA
SCL
STOP condition
Figure 22. STOP Condition
2. Generate START Condition.
VDD
SDA
SCL
START condition
Figure 23. START Condition
3. Issue Slave Address
4. Execute Software Reset (ICSET) Command
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Datasheet
MAX 144 segments (SEG36×COM4)
Display off Operation in External Clock Mode
After receiving MODESET(Display off), BU91797MUF-M and BU91797FUV-M enter to DISPOFF sequence synchronized
with frame then Segment and Common ports output VSS level after 1frame of OFF data write.
Therefore, in external clock mode, it is necessary to input the external clock based on each frame frequency setting after
sending MODESET (Display off).
For the required number of clock, refer to Power save mode FR of DISCTL.
Please input the external clock as below.
DISCTL 80HZ setting (Frame frequency [Hz] = external clock [Hz]
DISCTL 71HZ setting (Frame frequency [Hz] = external clock [Hz]
DISCTL 64HZ setting (Frame frequency [Hz] = external clock [Hz]
DISCTL 53HZ setting (Frame frequency [Hz] = external clock [Hz]
/ 512), it needs over 1024clk
/ 576), it needs over 1152clk
/ 648), it needs over 1296clk
/ 768), it needs over 1536clk
Please refer to the timing chart below.
Command
MODESET
OSCIN
To input External clock at
least 2 f rames or more
SEG
VSS
COM0
VSS
COM1
VSS
COM2
VSS
COM3
VSS
Display on
Display of f
Last Display f rame of
MODESET receiv ing
1 f rame of OFF
data write
Figure 25. External Clock Stop Timing
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Datasheet
MAX 144 segments (SEG36×COM4)
Note on the Multiple Devices be Connected to 2 Wire Interface
Do not access the other device without power supply (VDD) to the BU91797MUF-M and BU91797FUV-M.
BU91797xxx-M
Controller
Device1
Figure 26.
Example of BUS connection
To control the slope of the falling edge, a capacitor is connected between gate and drain of a NMOS transistor (Refer to
Figure 27).
The gate is in a high-impedance state when the power supply (VDD) is not supplied.
In this condition, the gate voltage is pulled up by the current flow through the capacitance as a result of the SDA signal's
transition from LOW to HIGH.
The NMOS transistor turns on and draws some current (Ids) from the SDA port if the gate voltage (Vg) is higher than the
threshold voltage (Vth).
An external resistor (R) is connected between the power line and SDA line to keep the SDA line as logic HIGH.
But the line cannot be kept as logic HGH if the voltage drop (R*Ids) is large.
Apply power supply (VDD) to BU91797MUF-M and BU91797FUV-M when the multiple devices are on the same bus.
Z=1/jωC
VDD
SDA
Vg
Internal circuit
Figure 27.
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SDA output cell structure
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Datasheet
MAX 144 segments (SEG36×COM4)
Operational Notes
1.
Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power
supply pins.
2.
Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the
digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog
block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and
aging on the capacitance value when using electrolytic capacitors.
3.
Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.
4.
Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5.
Thermal Consideration
Should by any chance the power dissipation rating be exceeded the rise in temperature of the chip may result in
deterioration of the properties of the chip. The absolute maximum rating of the Pd stated in this specification is when
the IC is mounted on a 70mm x 70mm x 1.6mm glass epoxy board. In case of exceeding this absolute maximum rating,
increase the board size and copper area to prevent exceeding the Pd rating.
6.
Recommended Operating Conditions
These conditions represent a range within which the expected characteristics of the IC can be approximately obtained.
The electrical characteristics are guaranteed under the conditions of each parameter.
7.
Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow
instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power
supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and
routing of connections.
8.
Operation Under Strong Electromagnetic Field
Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction.
9.
Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may
subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply
should always be turned off completely before connecting or removing it from the test setup during the inspection
process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during
transport and storage.
10. Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and
unintentional solder bridge deposited in between pins during assembly to name a few.
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MAX 144 segments (SEG36×COM4)
Datasheet
Operational Notes – continued
11. Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small
charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and
cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the
power supply or ground line.
12. Regarding the Input Pin of the IC
In the construction of this IC, P-N junctions are inevitably formed creating parasitic diodes or transistors. The operation
of these parasitic elements can result in mutual interference among circuits, operational faults, or physical damage.
Therefore, conditions which cause these parasitic elements to operate, such as applying a voltage to an input pin
lower than the ground voltage should be avoided. Furthermore, do not apply a voltage to the input pins when no power
supply voltage is applied to the IC. Even if the power supply voltage is applied, make sure that the input pins have
voltages within the values specified in the electrical characteristics of this IC.
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BU91797xxx-M Series
Datasheet
MAX 144 segments (SEG36×COM4)
Ordering Information
B
U
9
1
7
9
7
Part Number
x
x
x
-
Package
MUF
FUV
: VQFN48FV7070
: TSSOP-C48V
ME2
Product Rank
M: for Automotive
Packaging and forming specification
E2: Embossed tape and reel
Lineup
Package
Orderable Part Number
VQFN48FV7070
Reel of 1500
BU91797MUF-ME2
TSSOP-C48V
Reel of 2000
BU91797FUV-ME2
Marking Diagram
TSSOP-C48V(TOP VIEW)
VQFN48FV7070 (TOP VIEW)
Part Number Marking
Part Number Marking
BU91797
BU91797
LOT Number
1PIN MARK
1PIN MARK
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LOT Number
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BU91797xxx-M Series
MAX 144 segments (SEG36×COM4)
Datasheet
Physical Dimension Tape and Reel Information
Package Name
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VQFN48FV7070
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BU91797xxx-M Series
Package Name
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© 2015 ROHM Co., Ltd. All rights reserved.
TSZ22111･15･001
MAX 144 segments (SEG36×COM4)
Datasheet
TSSOP-C48V
26/27
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28.Mar.2017 Rev.002
BU91797xxx-M Series
Datasheet
MAX 144 segments (SEG36×COM4)
Revision History
Date
Revision
21. Dec. 2015
001
12. Jun. 2017
002
Changes
First release
Add BU91797FUV-M(TSSOP-C48)
Prohibit 1/2 bias setting
P.8 Modify Figure 11,Interface Protocol
P.10 Modify BLKCTL of Description List of Command / Function
P.12 Modify Set Power save mode FR table.(50Hz -> 53Hz)
P.18 Add “Caution in Power ON / OFF” Sequence
P.19 Modify the comment in Caution in POR Circuit Use
P.20 Add Display off operation in external clock mode
P.21 Add Note on the multiple devices be connected to 2 wire interface
P.23 Delete Operational Notes 13. Data transmission
P.24 Add TSSOP-C48V to Ordering Information, Lineup and Marking Diagram
P.26 Add TSSOP-C48V Physical Dimension, Tape and Reel Information
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Notice
Precaution on using ROHM Products
1.
(Note 1)
If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment
,
aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,
bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales
representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any
ROHM’s Products for Specific Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅣ
CLASSⅢ
2.
ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3.
Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below.
Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the
use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our
Products under any special or extraordinary environments or conditions (as exemplified below), your independent
verification and confirmation of product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of
flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning
residue after soldering
[h] Use of the Products in places subject to dew condensation
4.
The Products are not subject to radiation-proof design.
5.
Please verify and confirm characteristics of the final or mounted products in using the Products.
6.
In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7.
De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in
the range that does not exceed the maximum junction temperature.
8.
Confirm that operation temperature is within the specified range described in the product specification.
9.
ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1.
When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2.
In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PAA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.003
Precautions Regarding Application Examples and External Circuits
1.
If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2.
You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1.
Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2.
Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3.
Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4.
Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
trade act, please consult with ROHM in case of export.
Precaution Regarding Intellectual Property Rights
1.
All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data.
2.
ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the
Products with other articles such as components, circuits, systems or external equipment (including software).
3.
No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM
will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to
manufacture or sell products containing the Products, subject to the terms and conditions herein.
Other Precaution
1.
This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2.
The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3.
In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4.
The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice-PAA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.003
Datasheet
General Precaution
1. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents.
ROHM shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this docume nt is current as of the issuing date and subj ect to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the la test information with a ROHM sale s
representative.
3.
The information contained in this doc ument is provi ded on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate an d/or error-free. ROHM shall not be in an y way responsible or
liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccur acy or errors of or
concerning such information.
Notice – WE
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