BU9728AKV

Standard ICs LCD driver for segment-type LCDs BU9728AKV The BU9728AKV is a segment-type LCD system driver which can accommodate microcomputer control and a serial interface. An internal 4-bit common output and LCD drive power supply circuit enable configuration of a display system at low cost. •Applications car audio systems, telephones Movie projectors, •Features 1) Serial interface. (8-bit length) 2) Display RAM: Internal, 128 bits. (up to 128 segments can be displayed) 3) Internal power supply circuit for LCD drive. 4) Display duty: 1 / 4 5) Can be driven with low voltage and low current dissipation. •Absolute maximum ratings (Ta = 25°C, V Parameter Power supply voltage 1 Power supply voltage 2 Power dissipation Operating temperature Storage temperature SS = 0V) Limits – 0.3 ~ + 7.0 – 0.3 ~ + VDD 400∗ – 20 ~ + 75 – 55 ~ + 125 Unit V V mW °C °C Symbol VDD VLCD Pd Topr Tstg over 25°C . ∗ Reduced by 4.0mW for each increase in Ta of 1°C •Recommended operating conditions (Ta = 25°C, V Parameter Power supply voltage 1 Power supply voltage 2 (VDD - V3) Oscillation frequency SS = 0V) Max. 5.5 VDD — Unit V V kHz Conditions — The following relationship should be maintained: VDD V1 V2 V3 Rf = 470kΩ VSS. Symbol VDD VLCD fOSC Min. 2.5 0 — Typ. — — 36 1 Standard ICs BU9728AKV •Block diagram VDD LCD Driver Bias Circuit RESET V1 V2 V3 VSS SD SCK C/D CS SEG0 Serial Interface Address Counter Display Data RAM (DD RAM) LCD Segment Driver 32bits SEG1 SEG31 Command / Data Register LCD Common Driver 4bits COM0 COM1 COM2 COM3 Command Decoder Timing Generator Common Counter OSC1 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 36 35 34 33 32 31 30 29 28 27 26 25 37 24 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 23 22 21 20 19 18 17 16 15 14 13 9 10 11 12 SEG8 •Pin assignments OSC2 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 RESET COM3 COM2 COM1 BU9728AKV C/D 2 COM0 VDD SD OSC1 OSC2 SCK VSS CS V1 V2 V3 Standard ICs BU9728AKV Pin NO. 1 2 3~5 6 7 8 I/O I O — — — I Function Input / output pins for the internal oscillator. Resistance is connected between these pins when the internal clock is running. When an external clock is running, the clock is input from OSC1 and OSC2 is left open. These are power supply pins for LCD drive. The following relationship must be satisfied: VDD This is the VSS power supply pin. This is the VDD power supply pin. This is the shift clock input pin for serial data. The contents of the SD pin are read one bit at a time at the rising edge of SCK. This is the serial data input pin, used to input display data and commands. Display data is displayed when this is "1" and not displayed when it is "0". This is the chip select signal input pin. When this pin is LOW, SD input can be received. The SCK counter is reset when the CS pin goes from HIGH to LOW. This signal detects whether the SD input is command or display data. If the pin is LOW at the rising edge of the 8th SCK pulse, the input is recognized as display data, and if HIGH, the input is recognized as command data. These are the common output pins for LCD drive. They are connected to the LCD panel commons. This is the reset input pin. When this pin is LOW, the BU9728AKV is initialized. It resets the address counter and turns the display off. These are the segment output pins for LCD drive. They are connected to the LCD panel segments. V1 V2 V3 VSS (Low) . •Pin descriptions Pin name OSC1 OSC2 V1 ~ V3 VSS VDD SCK SD 9 I CS 10 I C/D COM0 11 I 12 ~ 15 COM3 RESET SEG0 17 ~ 48 SEG31 16 O I O •Input / output equivalent circuits Pin name I / O SD SCK C/D CS I VDD IN GND Equivalent Circuit Pin name I / O SEG0 SEG31 OUT Equivalent Circuit VLCD O ~ VLCD COM0 COM3 ~ GND OSC1 OSC2 — OSC1 VDD OSC2 GND RESET I IN VDD GND 3 Standard ICs BU9728AKV •Electrical characteristics otherwise noted, V DC characteristics (unless Parameter Input high level voltage Input low level voltage LCD driver ON resistance∗1 Input low level current 1 Input low level current 2 Input high level current Input capacitance DD = 2.5 ~ 5.5V, VSS = 0V, Ta = 25°C) Max. VDD 0.2 × VDD 30 100 2 — — 1 80 250 Unit V V kΩ µA µA µA pF µA µA µA Conditions — — ∆VON = 0.1V VIN = 0V VIN = 0V VIN = VDD — In wait state∗2 When display is operating∗3 During access operation∗4 Symbol VIH1 VIL1 RON IIL1 IIL2 IIH CIN Min. 0.8 × VDD 0 — — — –2 — — Typ. — — — — — — 5 0.05 40 100 Pin OSC1, SD, SCK, C / D, CS RESET SEG0 ~ 31, COM0 ~ 3 RESET OSC1, SD, SCK, C / D, CS OSC1, SD, SCK, C / D, CS, RESET SD, SCK, C / D, CS Current dissipation IDD — — VDD ∗1 Internal power supply impedance is not included in the LCD driver ON resistance. ∗2 All inputs, including V3 = 0V and OSC1, are fixed at either VDD or VSS. ∗3 Except for V3 = 0V, Rf = 470kΩ , and OSC1, all inputs are fixed at either VDD or VSS. ∗4 V3 = 0V, Rf = 470kΩ , f = 200kHz SCK AC characteristics (unless otherwise noted, VDD = 2.5 ~ 5.5V, VSS = 0V, Ta = 25°C) Parameter SCK rise time SCK fall time SCK cycle time Command wait time SCK pulse width "H" SCK pulse width "L" Data setup time Data hold time CS pulse width "H" CS pulse width "L" CS set-up time CS hold time C / D set-up time C / D hold time C / D - CS time∗5 C / D - SCK time∗5 Symbol tTLH tTHL tCYC tWAIT tWH1 tWL1 tSU1 tH1 tWH2 tWL2 tSU2 tH2 tSU3 tH3 tCCH tSCH Min. — — 800 800 300 300 100 100 300 6400 100 100 100 100 100 100 Typ. — — — — — — — — — — — — — — — — Max. 100 100 — — — — — — — — — — — — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Conditions — — — — — — — — — — — — — Use rise for 8th CK of SCK as standard Use CS riss as standard Use rise for 8th CK of SCK as standard ∗5 Only one (either one) of the conditions needs to be satisfied. 4 Standard ICs BU9728AKV •Timing charts CS tSU2 tCYC tWH1 SCK tWL2 tWH2 tH2 tWL1 tTLH tSU1 SD tH1 tTHL tCCH tSCH tSU3 tH3 C/D Fig.1 Interface timing tCYC tWAIT SCK SD D7 D6 D0 D7 Fig.2 Command cycle format •Datadata is 4-line data transmitted in synchronization with the clock. Serial data with a bit length of 8 bits is input in Serial synchronization with SCK. If C / D is HIGH at the rising edge of the 8 × nth SCK clock pulse, the serial data is recognized as command data, and if C / D is LOW, the serial data is recognized as display data. Serial data is input in sequential order, starting from the MSB. 5 Standard ICs BU9728AKV •A detailed look at commands commands (C / D is HIGH at 8 × nth clock pulse of SCK). The BU9728AKV has the following (1) Address Set MSB 0 0 0 A A A A LSB A AAAAA and the address data displayed in binary format are set in the address counter. Each time input of the display data (8 bits) has been completed, the address is incremented by + 2. (2) Display On MSB 0 0 1 LSB ∗ ∗ ∗ ∗ ∗ ∗ Irrelevant All display segments light, regardless of the contents of the Display Data RAM (DDRAM). The contents of the DDRAM do not change. (3) Display Off MSB 0 1 0 LSB ∗ ∗ ∗ ∗ ∗ ∗ Irrelevant All display segments go out, regardless of the contents of the DDRAM. The contents of the DDRAM do not change. (4) Display Start MSB 0 1 1 LSB ∗ ∗ ∗ ∗ ∗ ∗ Irrelevant Display begins, in accordance with the contents of the DDRAM. (5) Rewrite Display Data RAM (DDRAM) MSB 1 0 0 LSB ∗ D D D D ∗ Irrelevant The binary bit data DDDD is written to the DDRAM. The data is written to the address specified by the Address Set command, and after this command is executed, the address is automatically incremented by + 1. (6) Reset MSB 1 1 0 LSB ∗ ∗ ∗ ∗ ∗ ∗ Irrelevant This command should be executed before any other command, immediately after the power supply is turned on. This command resets the BU9728AKV to the following status: • Display is off • Address counter is reset 6 Standard ICs BU9728AKV •Description of functions (1) Register The BU9728AKV has a command / data register configured of eight bits. Serial data is read in 8-pulse units of the SCK clock. If the data read to the register is display data (C / D is LOW at the 8th clock pulse of SCK), it is written to the DDRAM, and if the data is command data (C / D is HIGH at the 8th clock pulse of SCK), it is output to a command decoder and used to control the BU9728AKV. (2) Address counter The address counter indicates the DDRAM address. When the set address is written to the command / data register, the address data is automatically sent to the address counter. After the data is written to the DDRAM, the address counter is automatically incremented by either + 1 or + 2. The amount by which the counter is incremented is determined automatically, based on the following statuses: 8 bits written to DDRAM (C / D LOW at 8th clock pulse of SCK) → + 2 4 bits written to DDRAM (C / D HIGH at 8th clock pulse of SCK) → + 1 When the address counter reaches 1FH, it will be reset back to 00H the next time it is incremented. (3) Display Data RAM (DDRAM) The Display Data RAM (DDRAM) is where displays are stored. The capacity of the DDRAM is 32 addresses × 4 bits. The illustration below shows the relationship between the DDRAM and the display positions. DDRAM address 00 0 1 bit 2 3 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG29 SEG30 SEG31 COM2 COM3 01 02 03 04 05 06 07 1D 1E 1F COM0 COM1 DDRAM addresses set in the address counter are in hexadecimal format and are indicated as follows. MSB AC4 AC3 AC2 AC1 LSB AC0 (Example) For a DDRAM address of “14” (display position: SEG20) MSB 1 1 0 1 4 0 LSB 0 7 Standard ICs BU9728AKV The display data input to the command / data register (when C / D is LOW) is written to the DDRAM address and the address consisting of the specified address + 1, which are indicated by the upper four and lower four bits of the data, respectively. The four bits of the display data are written sequentially, starting from the MSB, to the MSB of the DDRAM bits. MSB LSB D7 D6 D5 D4 D3 D2 D1 D0 Specified address (bit3 bit0) (bit3 Specified address + 1 bit0) If the Rewrite DDRAM command is input (C / D is HIGH), the four bits of the display data in the Rewrite DDRAM command are written to the specified DDRAM address. The four bits of the display data are written sequentially, starting from the MSB, to the MSB of the DDRAM bits. MSB 1 0 0 LSB ∗ D3 D2 D1 D0 Rewrite DDRAM command (bit3 Display data bit0) (4) Timing generator Connecting Rf between OSC1 and OSC2 causes the internal oscillator circuit to start oscillating, and generates a display timing signal. The oscillator can also be started by inputting an external clock. OSC1 Rf OSC2 OSC2 OPEN OSC1 EXIT CLOCK INPUT Fig. 3 Rf oscillator circuit Fig. 4 External clock input (5) LCD drive power supply The LCD drive power supply is generated by the BU9728AKV. The LCD drive voltage (VLCD) is supplied by VDD - V3, and the power supply is generated by V1 = 2 • VLCD / 3, V2 = VLCD / 3. If an external bleeder resistance is used to supply the LCD drive voltage externally, the following relationship must be observed: VDD = V1 V2 V3 VSS VDD V1 V2 V3 VSS VDD V1 V2 V3 VSS Fig. 5 Example of connection when using internal power supply Fig. 6 Example of connection when using external power supply (6) LCD drive circuit The LCD drive circuit is configured of four common drivers and 32 segment drivers. When oscillation begins, selected waveforms are output automatically for valid common outputs by the common counter, and de-selected waveforms are output for other outputs. For segment outputs, drive waveforms are output automatically by the display data and common counter. The following page shows examples of common / segment output waveforms. 8 Standard ICs BU9728AKV •LCD drive waveforms VDD V1 COM0 V2 V3 VDD V1 COM1 V2 V3 VDD V1 COM2 V2 V3 VDD V1 COM3 V2 V3 Frame cycle VDD V1 V2 V3 VDD V1 V2 V3 VDD SEG0 SEG31 V1 V2 V3 VDD V1 V2 V3 VDD V1 V2 V3 COM0 COM1 COM2 COM3 0 0 0 0 Display none of the segments COM0 to 3. 1 0 0 Display segment which applies to COM0. 0 0 1 0 Display segment which applies to COM1. 0 ~ 0 1 0 1 Display segments which apply to COM1 and COM3. 1 1 1 1 Display segments which apply to COM0 to COM3. 9 Standard ICs BU9728AKV •External dimensions (Units: mm) 9.0 ± 0.3 7.0 ± 0.2 36 9.0 ± 0.3 7.0 ± 0.2 37 48 1 1.425 ± 0.1 0.10 25 24 13 12 0.5 0.125 ± 0.1 0.10 0.5 0.2 ± 0.1 VQFP48 10