Datasheet
LCD Segment Drivers
Multi-function LCD Segment Drivers
BU97530KVT
MAX 445 Segment(89SEGx5COM)
General Description
Key Specifications
■
■
■
■
■
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The BU97530KVT is 1/5, 1/4, 1/3 duty or Static
General-purpose LCD driver. The BU97530KVT can
drive up to 445 LCD Segments directly. The
BU97530KVT can also control up to 9 General-purpose
output pins / 9 PWM output pins.
These products also incorporate a key scan circuit that
accepts input from up to 30 keys to reduce printed circuit
board wring.
Features
Supply Voltage Range:
+2.7V to +6.0V
Operating Temperature Range:
-40°C to +85°C
Max Segments:
445 Segments
Display Duty
Static, 1/3, 1/4, 1/5 Selectable
Bias:
1/2, 1/3 Selectable
Interface:
3wire Serial Interface
Package
W (Typ) x D (Typ) x H (Max)
Key Input Function for up to 30 Keys (A key scan is
performed only when a key is pressed.)
Either 1/5, 1/4, 1/3 Duty or Static
Can be Selected with the Serial Control Data.
1/5 Duty Drive: Up to 445 Segments can be Driven
1/4 Duty Drive: Up to 360 Segments can be Driven
1/3 Duty Drive: Up to 270 Segments can be Driven
Static Drive: Up to 90 Segments can be Driven
Selectable Display Frame Frequency for Common
and Segment Output Waveforms.
Configurable Output Pin to Segment Output / PWM
Output / General-purpose Output.(Max 9 Pins)
Built-in OSC Circuit
Integrated Voltage Detect Type Power on
Reset(VDET) Circuit
No External Component
Low Power Consumption Design
Supports Line and Frame Inversion
TQFP100V
16.00mm x 16.00mm x 1.20mm
Applications
Car Audio, Home Electrical Appliance,
Meter Equipment etc.
Typical Application Circuit
Key Matrix
(P1/G1)
(General purpose/PWM ports)
(For use control of backlight)
(P9/G9)
KS1/S79
+5V
KI1/S85
|
|
KS6/S84
KI5/S89
COM1
COM2
COM3
COM4
COM5/S78
S1/P1/G1
LCD Panel
VDD
(Up to 445
(Note)
S9/P9/G9
S10
From
Control
SCE
SCL
SDI
To Control
Segments)
SDO
S77
OSC/S90
(Note) Insert capacitors between VDD and VSS C≥0.1µF
Figure 1. Typical Application Circuit
○Product structure：Silicon monolithic integrated circuit
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COMMON Driver
S1/P1/G1
・・・
SEGMENT Driver/Latch
Clock /Timing
Generator
OSC / S90
S9/P9/G9
・・・
S10
S75
S76
S77
COM5/S78
COM4
COM3
COM2
COM1
Block Diagram
Control Register
PWM Register
SCE
Shift Register
SCL
Serial
Interface
SDI
LCD voltage
Generator
SDO
KEY BUFFER
VLCD
VDD
VLCD1
VDET
KEY SCAN
VLCD2
VSS
KS1/ S79
KS2/ S80
KS3/ S81
KS5/ S83
S52
KS4/ S82
KS6/ S84
S53
KI1 / S85
KI2 / S86
KI3 / S87
KI4 / S88
KI5 / S89
VSS
Figure 2. Block Diagram
75
51
S51
S54
S55
S56
S57
S58
S59
S60
S61
S63
S62
S64
S65
S66
S67
S68
S69
S71
S70
S72
S73
S74
S75
Pin Arrangement
50
76
S76
S50
S77
S49
COM5/S78
S48
COM4
S47
COM3
S46
COM2
S45
COM1
S44
KS1/S79
S43
KS2/S80
S42
KS3/S81
S41
KS4/S8
KS4/S82
2
KS5/S8
KS5/S83
3
KS6/S8
KS6/S84
4
KI1/S85
S40
KI2/S86
S36
KI3/S87
S35
KI4/S88
S34
KI5/S89
S33
VDD
S32
DO
SDO
S31
VSS
S30
OSC/S90
S29
SCE
CE
S28
SCL
CL
S27
S39
S38
S37
S26
DI
SDI
26
S25
S24
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9/P9/G9
S8/P8/G8
S7/P7/G7
S6/P6/G6
S5/P5/G5
S4/P4/G4
S3/P3/G3
S2/P2/G2
S1/P1/G1
1
25
100
Figure 3. Pin Configuration(TOP VIEW)
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Absolute Maximum Ratings(VSS = 0.0V)
Parameter
Symbol
Maximum Supply Voltage
VDD
VIN1
Input Voltage
VIN2
Allowable Loss
Pd
Operating Temperature
Topr
Storage Temperature
Tstg
Pin / Conditions
VDD
SCE, SCL, SDI, OSC
KI1 to KI5
-
Ratings
-0.3 to +7.0
-0.3 to +7.0
-0.3 to +7.0
1.49(Note)
-40 to +85
-55 to +125
Unit
V
V
V
W
°C
°C
(Note) Derate by 1.49mW/°C when operating above Ta=25°C (when mounted in ROHM’s standard board).
(Board size: 70mm×70mm×1.6mm material: FR4 board copper foil: land pattern only)
Caution1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is
operated over the absolute maximum ratings.
Caution 2:Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in deterioration of the
properties of the chip. In case of exceeding this absolute maximum rating, design a PCB with power dissipation taken into consideration by
increasing board size and copper area so as not to exceed the maximum junction temperature rating.
Recommended Operating Conditions (Ta = -40°C to +85°C, VSS = 0.0V)
Parameter
Supply Voltage
Symbol
VDD
Ratings
Typ
5.0
Max
6.0
Min
-
Limit
Typ
0.03VDD
0.1VDD
Max
-
1.4
1.8
2.2
V
0.4VDD
0.8VDD
0.7VDD
-
VDD
VDD
VDD
V
-
0
-
0.2VDD
V
VDD=5.0V
50
100
0.05VDD
250
V
kΩ
-
-
6.0
µA
µA
µA
Conditions
Min
2.7
-
Unit
V
Electrical Characteristics (Ta = -40°C to +85°C, VDD = 2.7V to 6.0V, VSS = 0.0V)
Parameter
Symbol
Pin
Conditions
VH1
VH2
SCE, SCL, SDI, OSC
KI1 to KI5
-
VDET
VDD
-
“H” Level Input Voltage
VIH1
VIH2
VIH3
4.0V ≤ VDD ≤ 6.0V
2.7V ≤ VDD < 4.0V
-
“L” Level Input Voltage
VIL1
Input Floating Voltage
Pull-down Resistance
Output Off Leakage
Current
“H” Level Input Current
“L” Level Input Current
VIF
RPD
SCE, SCL, SDI, OSC
SCE, SCL, SDI, OSC
KI1 to KI5
SCE, SCL, SDI, OSC
KI1 to KI5
KI1 to KI5
KI1 to KI5
IOFFH
SDO
VO=6.0V
SCE, SCL, SDI, OSC
SCE, SCL, SDI, OSC
VI = 5.5V
VI = 0V
IO = -20µA,
VLCD=1.00*VDD
IO = -100µA,
VLCD=1.00*VDD
-5.0
-
5.0
-
VDD-0.9
-
-
VDD-0.9
-
-
-
-
Hysteresis
Power-on
Voltage
Detection
“H” Level
Output Voltage
“L” Level
Output Voltage
Middle Level
Output Voltage
IIH1
IIL1
VOH1
S1 to S90
VOH2
COM1 to COM5
VOH3
P1/G1 to P9/G9
IO = -1mA
VDD-0.9
VOH4
KS1 to KS6
IO = -500µA
VDD-1.0 VDD-0.5 VDD-0.2
VOL1
VOL2
VOL3
VOL4
VOL5
S1 to S90
COM1 to COM5
P1/G1 to P9/G9
KS1 to KS6
SDO
VMID1
S1 to S90
VMID2
COM1 to COM5
VMID3
S1 to S90
VMID4
S1 to S90
VMID5
COM1 to COM5
VMID6
COM1 to COM5
IO = 20µA
IO = 100µA
IO = 1mA
IO = 25µA
IO = 1mA
1/2 Bias IO = ±20µA
VLCD=1.00*VDD
1/2 Bias IO = ±100µA
VLCD=1.00*VDD
1/3 Bias IO = ±20µA
VLCD=1.00*VDD
1/3 Bias IO = ±20µA
VLCD=1.00*VDD
1/3 Bias IO = ±100µA
VLCD=1.00*VDD
1/3 Bias IO = ±100µA
VLCD=1.00*VDD
0.2
1/2VDD
-0.9
1/2VDD
-0.9
2/3VDD
-0.9
1/3VDD
-0.9
2/3VDD
-0.9
1/3VDD
-0.9
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Unit
V
V
0.5
0.1
-
0.9
0.9
0.9
1.5
0.5
1/2VDD
+0.9
1/2VDD
+0.9
2/3VDD
+0.9
1/3VDD
+0.9
2/3VDD
+0.9
1/3VDD
+0.9
V
V
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BU97530KVT
Electrical Characteristics– continued
Parameter
Symbol
Pin
IDD1
VDD
IDD2
VDD
Conditions
Power-saving mode
VDD = 5.0V
Output open
1/2 Bias
Frame frequency=80Hz
VLCD=1.00*VDD
VDD = 5.0V
Output open
1/3 Bias
Frame frequency=80Hz
VLCD=1.00*VDD
Current Consumption
IDD3
VDD
Min
-
Limit
Typ
-
Max
15
-
100
200
Unit
µA
-
130
250
Min
300
510
Limit
Typ
600
Max
720
690
30
-
1000
kHz
-
160
-
ns
-
160
-
ns
30
50
70
%
Oscillation Characteristics (Ta = -40°C to +85°C, VDD = 2.7V to 6.0V, VSS = 0.0V)
Parameter
Symbol
Pin
Oscillator Frequency 1
Oscillator Frequency 2
External Clock
Frequency(Note)
External Clock Rise Time
fOSC1
fOSC2
-
External Clock Fall Time
External Clock Duty
Conditions
VDD = 2.7V to 6.0V
VDD = 5V
fOSC3
tr
External clock mode
(OC=1)
OSC/S90
tf
tDTY
Unit
kHz
kHz
(Note) Frame frequency is decided external clock and dividing ratio of FC0,FC1,FC2,FC3 setting.
[Reference Data]
fosc[kHz]
700
650
VDD = 6.0V
600
VDD = 5.0V
550
VDD = 3.3V
500
450
VDD = 2.7V
400
350
300
-40
-20
0
20
40
60
80
Temperature[°C]
Figure 4. Oscillator Frequency Typical Temperature Characteristics
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MPU Interface Characteristics (Ta = -40°C to +85°C, VDD = 2.7V to 6.0V, VSS = 0.0V)
Parameter
Symbol
Data Setup Time
Data Hold Time
SCE Wait Time
SCE Setup Time
SCE Hold Time
Clock Cycle Time
High-level Clock Pulse
Width
Low-level Clock Pulse
Width (Write)
Low-Level Clock Pulse
Width (Read)
Rise Time
Fall Time
Pin
Conditions
Limit
Typ
-
Max
-
Unit
tCCYC
SCL, SDI
SCL, SDI
SCE, SCL
SCE, SCL
SCE, SCL
SCL
-
Min
120
120
120
120
120
320
tCHW
SCL
-
120
-
-
ns
tCLWW
SCL
-
120
-
-
ns
1.6
-
-
µs
-
160
160
-
ns
ns
-
-
1.5
µs
-
-
1.5
µs
tDS
tDH
tCP
tCS
tCH
tCLWR
RPU=4.7kΩ
CL=10pF(Note)
RPU=4.7kΩ
CL=10pF(Note)
RPU=4.7kΩ
CL=10pF(Note)
SCL
tr
tf
SCE, SCL, SDI
SCE, SCL, SDI
SDO Output Delay Time
tDC
SDO
SDO Rise Time
tDR
SDO
ns
ns
ns
ns
ns
ns
(Note) Since SDO is an open-drain output, “tDC” and “tDR” depend on the resistance of the pull-up resistor RPU and the load capacitance CL.
RPU: 1kΩ≤RPU≤10kΩ is recommended.
CL: A parasitic capacitance to VSS in an application circuit. Any component is not necessary to be attached.
Power supply for I/O level
RPU
SDO
Host
CL
1. When SCL is stopped at the low level
VIH1, VIH2
SCE
VIL1
tCCYC
tCHW
tCLWW
tCLWR
VIH1, VIH2
SCL
VIL1
tr
SDI
tCS
tf
tCH
VIH1, VIH2
VIL1
tDS
tDH
SDO
VOL5
tDR
tDC
2. When SCL is stopped at the high level
VIH1, VIH2
SCE
VIL1
tCCYC
tCHW
tCLWW
SCL
tCLWR
VIH1,VIH2
VIL1
tf
SDI
tCH
tCP
tr
VIH1,VIH2
VIL1
tDS
tDH
SDO
VOL5
tDC
tDR
Figure 5. Serial Interface Timing
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Pin Description
Pin
Pin No.
S1/P1/G1 to
S9/P9/G9
1 to 9
S10 to S77
10 to 77
KS1/S79 to
KS6/S84
83 to 88
KI1/S85 to
KI5/S89
89 to 93
COM1 to
COM4
79 to 82
COM5/S78
78
OSC/S90
97
SCE
SCL
SDI
98
99
100
SDO
95
VDD
94
VSS
96
Function
Segment output for displaying the display data transferred by
serial data input. The S1/P1/G1 to S9/P9/G9 pins can also be
used as General-purpose or PWM outputs when so set up by
the control data.
Segment output for displaying the display data transferred by
serial data input.
Key scan outputs
Although normal key scan timing lines require diodes to be
inserted in the timing lines to prevent shorts, since these
outputs are unbalanced CMOS transistor outputs, these
outputs will not be damaged by shorting
when these outputs are used to form a key matrix. The
KS1/S79 to KS6/S84 pins can be used as segment outputs
when so specified by the control data.
Key scan inputs
These pins have built-in pull-down resistors.
The KI1/S85 to KI5/S89 pins can be used as segment outputs
when so specified by the control data.
Common driver output pins. The frame frequency is fo[Hz].
Common / Segment output for LCD driving
Assigned as Common output in1/5 Duty mode and Segment
output in Static, 1/3 Duty and 1/4 Duty modes
Segment output for displaying the display data transferred by
serial data input.
The pin OSC/S90 can be used as external clock input pin when
set up by the control data.
Serial data transfer inputs. Must be connected to the controller.
SCE: Chip enable
SCL: Clock for serial data transfer.
SDI: Transfer data
Output data
Power supply pin of the IC
A power voltage of 2.7V to 6.0V must be applied to this pin.
Power supply pin. Must be connected to ground.
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Active
I/O
Handling
when
unused
-
O
OPEN
-
O
OPEN
-
O
OPEN
I
VSS
O
OPEN
-
O
OPEN
-
O
OPEN
I
VSS
O
OPEN
-
I
I
I
VSS
VSS
VSS
O
OPEN
-
-
-
-
-
-
-
-
H
↑
TSZ02201-0P4P0D300570-1-2
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BU97530KVT
IO Equivalent Circuit
VDD
VDD
SCE/SDI/SCL
VSS
VSS
VDD
VDD
S10 to S77,
COM1 to COM4
OSC/S90
VSS
VSS
VDD
KI1/S85 to KI5/S89
VDD
S1/P1/G1 to S9/P9/G9,
KS1/S79 to KS6/S84
VSS
VSS
VDD
VDD
COM5/S78
SDO
VSS
VSS
Figure 6. I/O Equivalent Circuit
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Serial Data Transfer Formats
1. 1/5 Duty
(1)When SCL is stopped at the low level
SCE
SCL
SDI
1
0
1
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
D1
D2
D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 D120
KM0 KM1 KM2 P0
P1
P2
P3
FL
1
0
1
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
D121
D122
D225 D226 D227 D228 D229 D230 D231 D232 D233 D234 D235 D236 D237 D238 D239 D240
Device Code
8bits
0
0
0
0
0
1
0
1
0
0
0
1
0
B1
B2
B3
A0
A1
A2
A3
D241
D242
1
0
1
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
D341
D342
FC1
FC2 FC3
OC
SC
BU0 BU1 BU2
D330 D331 D332 D333 D334 D335 D336 D337 D338 D339 D340 0
0
0
0
W11
W16 W17 W18
0
W21
W26 W27 W28
0
W31
0
W51
W56 W57 W58
0
W61
W66 W67 W68
0
W71
0
1
W36 W37 W38
0
W41
W46 W47 W48
1
0
DD
2 bits
W76 W77 W78
Control Data
45bits
Display Data
105bits
0
DD
2 bits
Control Data
50bits
D437 D438 D439 D440 D441 D442 D443 D444 D445
0
DD
2 bits
Control Data
30bits
Display Data
100bits
Device Code
8bits
DT0 DT1 FC0
PG1 PG2 PG3 PG4 PG5 PG6 PG7 PG8 PG9 PF0 PF1 PF2 PF3 CT0 CT1 CT2 CT3
Display Data
120bits
B0
DR
Control Data
30bits
Display Data
120bits
Device Code
8bits
Device Code
8bits
0
0
0
W81
W86 W87 W88
0
W91
W96 W97 W98
1
1
DD
2 bits
Figure 7. 3-SPI Data Transfer Format
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Serial Data Transfer Formats – continued
(2)When SCL is stopped at the high level
SCE
SCL
SDI
1
0
1
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
D1
D2
D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 D120
KM0 KM1 KM2 P0
P1
P2
P3
FL
Display Data
120bits
Device Code
8bits
1
0
1
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
D121
D122
0
0
0
0
0
1
0
1
0
0
0
1
0
B1
B2
B3
A0
A1
A2
A3
D241
D242
Device Code
8bits
1
0
1
0
0
0
1
0
B1
B2
B3
A0
A1
A2
A3
D341
D342
FC3 OC
SC
BU0 BU1 BU2
D330 D331 D332 D333 D334 D335 D336 D337 D338 D339 D340 0
0
0
0
W11
W16 W17 W18
0
W21
W26 W27 W28
0
W31
0
W51
W56 W57 W58
0
W61
W66 W67 W68
0
Display Data
105bits
W71
0
0
1
DD
2 bits
W36 W37 W38
0 W41
W46 W47 W48
Control Data
50bits
D437 D438 D439 D440 D441 D442 D443 D444 D445
0
DD
2 bits
Control Data
30bits
Display Data
100bits
B0
DT1 FC0 FC1 FC2
PG1 PG2 PG3 PG4 PG5 PG6 PG7 PG8 PG9 PF0 PF1 PF2 PF3 CT0 CT1 CT2 CT3
Display Data
120bits
B0
DR DT0
Control Data
30bits
D225 D226 D227 D228 D229 D230 D231 D232 D233 D234 D235 D236 D237 D238 D239 D240
Device Code
8bits
Device Code
8bits
0
0
1
0
DD
2 bits
W76 W77 W78
0
W81
W86 W87 W88
0
W91
W96 W97 W98
Control Data
45bits
1
1
DD
2 bits
Figure 8. 3-SPI Data Transfer Format
Device code ························· “45H”
KM0 to KM2 ························· Key Scan output pin / Segment output pin switching control data
D1 to D445 ·························· Display data
P0 to P3 ······························ Segment / PWM / General-purpose output pin switching control data
FL ······································ Line Inversion or Frame Inversion switching control data
DR ····································· 1/3 Bias drive or 1/2 Bias drive switching control data
DT0 to DT1 ·························· 1/5 Duty drive, 1/4 Duty drive, 1/3 Duty drive or Static drive switching control data
FC0 to FC3 ·························· Common / Segment output waveform frame frequency switching control data
OC ····································· Internal oscillator operating mode / External clock operating mode switching control data
SC ····································· Segment on/off switching control data
BU0 to BU2 ························· Normal mode / power-saving mode switching control data
PG1 to PG9 ························· PWM / General-purpose output switching control data
PF0 to PF3 ·························· PWM output waveform frame frequency switching control data
CT0 to CT3 ·························· LCD display contrast switching control data
W11 to W18, W21 to W28, W31 to W38, W41 to W48, W51 to W58, W61 to W68, W71 to W78, W81 to W88, W91 to W98
······································ PWM output duty switching control data
DD ····································· Direction data
When it is coincident with device code, BU97530KVT capture display data and control data at falling edge of SCE.
So, please transfer the bit number of send display data and control data as specified number in the above figure.
Specified number of bits is 160bit (Device code: 8bit, Display data and Control data: 150bit, DD: 2bit).
www.rohm.com
© 2014 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
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TSZ02201-0P4P0D300570-1-2
02.Aug.2019 Rev.006
BU97530KVT
Serial Data Transfer Formats – continued
2. 1/4 Duty
(1)When SCL is stopped at the low level
1/5 ,1/4,1/3,は同じ波形（HとLも）
SCE
SCL
SDI
1
0
1
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
D1
D2
D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 D120
Device Code
8bits
1
0
1
0
0
0
1
0
B1
B2
B3
A0
A1
A2
A3
D121
D122
0
1
B1
B2
1
B0
0
B1
1
B2
0
0
0
1
0
A0
A1
A2
A3
0
B3
0
A0
Device Code
8bits
P2
P3
FL
0
0
0
0
0
0
A1
1
A2
0
A3
D241
D242
D342
D330 D331 D332 D333 D334 D335 D336 D337 D338 D339 D340
D360
0
0
0
DT0 DT1 FC0
FC1
FC2 FC3
OC
SC
BU0 BU1 BU2
0
0
0
0
W11
W16 W17 W18
0
W21
W26 W27 W28
0
W31
0
0
0
0
0 W51
W56 W57 W58
0
W61
W66 W67 W68
0
Control Data
130bits
W71
0
0
1
DD
2 bits
W36 W37 W38
0 W41
W46 W47 W48
Control Data
50bits
Display Data
20bits
0
DD
2 bits
Control Data
30bits
Display Data
100bits
D341
DR
PG1 PG2 PG3 PG4 PG5 PG6 PG7 PG8 PG9 PF0 PF1 PF2 PF3 CT0 CT1 CT2 CT3
Display Data
120bits
B3
Device Code
8bits
P1
Control Data
30bits
D225 D226 D227 D228 D229 D230 D231 D232 D233 D234 D235 D236 D237 D238 D239 D240
Device Code
8bits
1
KM0 KM1 KM2 P0
Display Data
120bits
B0
B0
0
0
1
0
DD
2 bits
W76 W77 W78
0
W81
W86 W87 W88
0
W91
W96 W97 W98
1
1
DD
2 bits
Figure 9. 3-SPI Data Transfer Format
www.rohm.com
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BU97530KVT
Serial Data Transfer Formats – continued
(2)When SCL is stopped at the high level
1/5 ,1/4,1/3,は同じ波形（HとLも）
SCE
SCL
SDI
1
0
1
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
D1
D2
D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 D120
0
0
KM0 KM1 KM2 P0
P1
P2
P3
FL
Display Data
120bits
Device Code
8bits
1
0
1
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
D121
D122
0
0
0
0
0
1
0
1
0
0
0
1
0
B1
B2
B3
A0
A1
A2
A3
D241
D242
0
0
0
W11
W16 W17 W18
0
W21
1
0
1
0
0
0
1
0
B1
B2
B3 A0
A1
A2
A3
Device Code
8bits
D341
D342
D360
0
0
0
OC
SC
BU0 BU1 BU2
W26 W27 W28
0
W31
0
0
0
0
0 W51
W56 W57 W58
Display Data
20bits
0
W61
W66 W67 W68
0
W71
0
0
DD
2 bits
0
1
DD
2 bits
W36 W37 W38
0 W41
W46 W47 W48
Control Data
50bits
Display Data
100bits
B0
FC2 FC3
Control Data
30bits
D330 D331 D332 D333 D334 D335 D336 D337 D338 D339 D340 0
Device Code
8bits
FC1
PG1 PG2 PG3 PG4 PG5 PG6 PG7 PG8 PG9 PF0 PF1 PF2 PF3 CT0 CT1 CT2 CT3
Display Data
120bits
B0
DT0 DT1 FC0
Control Data
30bits
D225 D226 D227 D228 D229 D230 D231 D232 D233 D234 D235 D236 D237 D238 D239 D240
Device Code
8bits
DR
1
0
DD
2 bits
W76 W77 W78
0
W81
W86 W87 W88
0
W91
W96 W97 W98
Control Data
130bits
1
1
DD
2 bits
Figure 10. 3-SPI Data Transfer Format
Device code ························· “45H”
KM0 to KM2 ························· Key Scan output pin / Segment output pin switching control data
D1 to D360 ·························· Display data
P0 to P3 ······························ Segment / PWM / General-purpose output pin switching control data
FL ······································ Line Inversion or Frame Inversion switching control data
DR ····································· 1/3 Bias drive or 1/2 Bias drive switching control data
DT0 to DT1 ·························· 1/5 Duty drive, 1/4 Duty drive, 1/3 Duty drive or Static drive switching control data
FC0 to FC3 ·························· Common / Segment output waveform frame frequency switching control data
OC ····································· Internal oscillator operating mode / External clock operating mode switching control data
SC ····································· Segment on/off switching control data
BU0 to BU2 ························· Normal mode/power-saving mode switching control data
PG1 to PG9 ························· PWM/ General-purpose output switching control data
PF0 to PF3 ·························· PWM output waveform frame frequency switching control data
CT0 to CT3 ·························· LCD display contrast switching control data
W11 to W18, W21 to W28, W31 to W38, W41 to W48, W51 to W58, W61 to W68, W71 to W78, W81 to W88, W91 to W98
······································ PWM output duty switching control data
DD ····································· Direction data
When it is coincident with device code, BU97530KVT capture display data and control data at falling edge of SCE.
So, please transfer the bit number of send display data and control data as specified number in the above figure.
Specified number of bits is 160bit (Device code: 8bit, Display data and Control data: 150bit, DD: 2bit).
www.rohm.com
© 2014 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
11/56
TSZ02201-0P4P0D300570-1-2
02.Aug.2019 Rev.006
BU97530KVT
Serial Data Transfer Formats – continued
3. 1/3 Duty
(1) When SCL is stopped at the low level
1/5 ,1/4,1/3,は同じ波形（HとLも）
SCE
SCL
SDI
1
0
1
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
D1
D2
D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 D120
Device Code
8bits
1
B0
0
B1
1
0
B1
1
0
0
0
1
0
B2
B3
A0
A1
A2
A3
D121
D122
1
0
B1
P1
P2
P3
FL
1
0
0
0
1
0
B2
B3
A0
A1
A2
A3
D241
D242
D225 D226 D227 D228 D229 D230 D231 D232 D233 D234 D235 D236 D237 D238 D239 D240
D265 D266 D267 D268 D269 D270
0
0
0
0
0
1
0
0
0
1
0
B3
A0
A1
A2
A3
0
0
0
0
OC
SC
BU0 BU1 BU2
0
0
0
0
0
0
0
0
0
W11
W16 W17 W18
PG1 PG2 PG3 PG4 PG5 PG6 PG7 PG8 PG9 PF0 PF1 PF2 PF3 CT0 CT1 CT2 CT3
W21
0
W26 W27 W28
0
W31
0
0
0
0
0
0
0 W51
W56 W57 W58
Device Code
8bits
0
W61
W66 W67 W68
0
W71
0
0
1
DD
2 bits
W36 W37 W38
0 W41
W46 W47 W48
1
0
DD
2 bits
Control Data
120bits
0
0
DD
2 bits
Control Data
30bits
Display Data
30bits
B2
DR DT0 DT1 FC0 FC1 FC2 FC3
Control Data
30bits
Display Data
120bits
Device Code
8bits
B0
KM0 KM1 KM2 P0
Display Data
120bits
Device Code
8bits
B0
0
0
W76 W77 W78
Control Data
150bits
0
W81
W86 W87 W88
0
W91
W96 W97 W98
1
1
DD
2 bits
Figure 11. 3-SPI Data Transfer Format
www.rohm.com
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BU97530KVT
Serial Data Transfer Formats – continued
(2)When SCL is stopped at the high level
1/5 ,1/4,1/3,は同じ波形（HとLも）
SCE
SCL
SDI
1
0
1
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
D1
D2
D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 D120
0
B1
KM0 KM1 KM2 P0
P1
P2
P3
FL
1
0
0
0
1
0
B2
B3
A0
A1
A2
A3
D121
D122
D225 D226 D227 D228 D229 D230 D231 D232 D233 D234 D235 D236 D237 D238 D239 D240
Device Code
8bits
0
0
0
0
0
1
0
1
0
0
0
1
0
B1
B2
B3
A0
A1
A2
A3
D241
D242
Device Code
8bits
D265 D266 D267 D268 D269 D270 0
0
1
0
0
0
1
B0
B1
B2
B3
A0
A1
A2 A3
0
0
0
0
FC1
FC2 FC3
OC
SC
BU0 BU1 BU2
0
0
0
0
0
0
0
0
W11
W16 W17 W18
0
W21
W26 W27 W28
0
W31
0
0
0
0
0
0
0
0 W51
W56 W57 W58
0
W61
W66 W67 W68
0
W71
W36 W37 W38
0 W41
W46 W47 W48
0
1
1
0
DD
2 bits
W76 W77 W78
0
W81
W86 W87 W88
0
W91
W96 W97 W98
Control Data
150bits
Device Code
8bits
0
DD
2 bits
Control Data
120bits
0
0
DD
2 bits
Control Data
30bits
Display Data
30bits
1
DT0 DT1 FC0
PG1 PG2 PG3 PG4 PG5 PG6 PG7 PG8 PG9 PF0 PF1 PF2 PF3 CT0 CT1 CT2 CT3
Display Data
120bits
B0
DR
Control Data
30bits
Display Data
120bits
Device Code
8bits
1
B0
0
0
1
1
DD
2 bits
Figure 12. 3-SPI Data Transfer Format
Device code ························· “45H”
KM0 to KM2 ························· Key Scan output pin / Segment output pin switching control data
D1 to D270 ·························· Display data
P0 to P3 ······························ Segment / PWM / General-purpose output pin switching control data
FL ······································ Line Inversion or Frame Inversion switching control data
DR ····································· 1/3 Bias drive or 1/2 Bias drive switching control data
DT0 to DT1 ·························· 1/5 Duty drive, 1/4 Duty drive, 1/3 Duty drive or Static drive switching control data
FC0 to FC3 ·························· Common / Segment output waveform frame frequency switching control data
OC ····································· Internal oscillator operating mode / External clock operating mode switching control data
SC ····································· Segment on/off switching control data
BU0 to BU2 ························· Normal mode / power-saving mode switching control data
PG1 to PG9 ························· PWM / General-purpose output switching control data
PF0 to PF3 ·························· PWM output waveform frame frequency switching control data
CT0 to CT3 ·························· LCD display contrast switching control data
W11 to W18, W21 to W28, W31 to W38, W41 to W48, W51 to W58, W61 to W68, W71 to W78, W81 to W88, W91 to W98
······································ PWM output duty switching control data
DD ····································· Direction data
When it is coincident with device code, BU97530KVT capture display data and control data at falling edge of SCE.
So, please transfer the bit number of send display data and control data as specified number in the above figure.
Specified number of bits is 160bit (Device code: 8bit, Display data and Control data: 150bit, DD: 2bit).
www.rohm.com
© 2014 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
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TSZ02201-0P4P0D300570-1-2
02.Aug.2019 Rev.006
BU97530KVT
Serial Data Transfer Formats – continued
4. Static
(1)When SCL is stopped at the low level
SCE
SCL
SDI
1
0
1
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
D1
D2
D81 D82 D83 D84 D85 D86
Device Code
8bits
1
B0
0
B1
D87 D88 D89 D90
0
0
0
0
0
0
1
0
B1
1
0
0
0
1
0
B2
B3
A0
A1
A2
A3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
B1
0
0
0
0
0
P1
P2
P3
FL
DR DT0 DT1 FC0 FC1 FC2
FC3 OC
SC
BU0 BU1 BU2
1
0
0
0
1
0
B2
B3
A0
A1
A2
A3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W16 W17 W18
W11
1
0
0
0
1
0
B3
A0
A1
A2
A3
0
0
0
0
0
0
0
0
0
0
0
0
W55 W56 W57 W58
Device Code
8bits
0
W61
0
DD
2 bits
PG1 PG2 PG3 PG4 PG5 PG6 PG7 PG8 PG9 PF0 PF1 PF2 PF3 CT0 CT1 CT2 CT3
0
1
DD
2 bits
0
W21
W26 W27 W28
0
W31
W36 W37 W38
0 W41
W46 W47 W48
Control Data
150bits
B2
0
Control Data
60bits
Control Data
150bits
Device Code
8bits
B0
KM0 KM1 KM2 P0
Display Data
90bits
Device Code
8bits
B0
0
0
1
0
DD
2 bits
W66 W67 W68
0
W71
W76 W77 W78
Control Data
150bits
0
W81
W86 W87 W88
0
W91
W96 W97 W98
1
1
DD
2 bits
Figure 13. 3-SPI Data Transfer Format
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02.Aug.2019 Rev.006
BU97530KVT
Serial Data Transfer Formats – continued
(2)When SCL is stopped at the high level
SCE
SCL
SDI
1
0
1
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
D1
D2
D81 D82 D83 D84 D85 D86 D87 D88 D89 D90
1
0
B1
0
0
0
1
0
B1
1
0
0
0
1
0
B2
B3
A0
A1
A2
A3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
B1
KM0 KM1 KM2 P0
P1
P2
P3
FL
DR
DT0 DT1 FC0 FC1 FC2 FC3
OC
SC
1
0
0
0
1
0
B2
B3
A0
A1
A2
A3
0
0
0
0
0
0
0
0
0
PG1 PG2 PG3 PG4 PG5 PG6 PG7 PG8 PG9 PF0 PF1 PF2 PF3 CT0 CT1 CT2 CT3
0
0
0
0
0
0
0
0
0
0
0
0
W16 W17 W18
W11
1
0
0
0
1
0
B3
A0
A1
A2
A3
0
0
0
0
0
0
0
0
0
0
0
0 W51
W56 W57 W58
0
W61
0
1
DD
2 bits
0
W21
W26 W27 W28
0
W31
W36 W37 W38
0 W41
W46 W47 W48
1
0
DD
2 bits
W66 W67 W68
0
W71
W76 W77 W78
0
W81
W86 W87 W88
0
W91
W96 W97 W98
Control Data
150bits
Device Code
8bits
0
DD
2 bits
Control Data
150bits
B2
0
BU0 BU1 BU2
Control Data
150bits
Device Code
8bits
B0
0
Control Data
60bits
Device Code
8bits
B0
0
0
0
Display Data
90bits
Device Code
8bits
B0
0
1
1
DD
2 bits
Figure 14. 3-SPI Data Transfer Format
Device code ························· “45H”
KM0 to KM2 ························· Key Scan output pin / Segment output pin switching control data
D1 to D90 ···························· Display data
P0 to P3 ······························ Segment / PWM / General-purpose output pin switching control data
FL ······································ Line Inversion or Frame Inversion switching control data
DR ····································· 1/3 Bias drive or 1/2 Bias drive switching control data
DT0 to DT1 ·························· 1/5 Duty drive, 1/4 Duty drive, 1/3 Duty drive or Static drive switching control data
FC0 to FC3 ·························· Common / Segment output waveform frame frequency switching control data
OC ····································· Internal oscillator operating mode / External clock operating mode switching control data
SC ····································· Segment on/off switching control data
BU0 to BU2 ························· Normal mode / power-saving mode switching control data
PG1 to PG9 ························· PWM / General-purpose output switching control data
PF0 to PF3 ·························· PWM output waveform frame frequency switching control data.
CT0 to CT3 ·························· LCD display contrast switching control data.
W11 to W18, W21 to W28, W31 to W38, W41 to W48, W51 to W58, W61 to W68, W71 to W78, W81 to W88, W91 to W98
······································ PWM output duty switching control data.
DD ····································· Direction data
When it is coincident with device code, BU97530KVT capture display data and control data at falling edge of SCE.
So, please transfer the bit number of send display data and control data as specified number in the above figure.
Specified number of bits is 160bit (Device code: 8bit, Display data and Control data: 150bit, DD: 2bit).
www.rohm.com
© 2014 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
15/56
TSZ02201-0P4P0D300570-1-2
02.Aug.2019 Rev.006
BU97530KVT
Control Data Functions
1. KM0,KM1 and KM2: Key Scan output pin / Segment output pin switching control data
These control data bits switch the functions of the KS1/S79 to KS6/S84 output pins between key scan output and segment
output.
Output Pin State
Maximum
Reset
KM0 KM1 KM2
Number of
Condition
KS1/S79
KS2/S80
KS3/S81
KS4/S82
KS5/S83
KS6/S84
Input Keys
0
0
0
KS1
KS2
KS3
KS4
KS5
KS6
30
0
0
1
S79
KS2
KS3
KS4
KS5
KS6
25
0
1
0
S79
S80
KS3
KS4
KS5
KS6
20
0
1
1
S79
S80
S81
KS4
KS5
KS6
15
1
0
0
S79
S80
S81
S82
KS5
KS6
10
1
0
1
S79
S80
S81
S82
S83
KS6
5
1
1
0
S79
S80
S81
S82
S83
S84
0
1
1
1
S79
S80
S81
S82
S83
S84
0
○
2. P0,P1,P2 and P3: Segment / PWM / General-purpose output pin switching control data
These control data bits are used to select the function of the S1/P1/G1 to S9/P9/G9 output pins (Segment Output Pins or
PWM Output Pins or General-purpose Output Pins).
Reset
P0 P1 P2 P3 S1/P1/G1 S2/P2/G2 S3/P3/G3 S4/P4/G4 S5/P5/G5 S6/P6/G6 S7/P7/G7 S8/P8/G8 S9/P9/G9
Condition
0 0 0 0
S1
S2
S3
S4
S5
S6
S7
S8
S9
○
0 0 0 1
P1/G1
S2
S3
S4
S5
S6
S7
S8
S9
0 0 1 0
P1/G1
P2/G2
S3
S4
S5
S6
S7
S8
S9
0 0 1 1
P1/G1
P2/G2
P3/G3
S4
S5
S6
S7
S8
S9
0 1 0 0
P1/G1
P2/G2
P3/G3
P4/G4
S5
S6
S7
S8
S9
0 1 0 1
P1/G1
P2/G2
P3/G3
P4/G4
P5/G5
S6
S7
S8
S9
0 1 1 0
P1/G1
P2/G2
P3/G3
P4/G4
P5/G5
P6/G6
S7
S8
S9
0 1 1 1
P1/G1
P2/G2
P3/G3
P4/G4
P5/G5
P6/G6
P7/G7
S8
S9
1 0 0 0
P1/G1
P2/G2
P3/G3
P4/G4
P5/G5
P6/G6
P7/G7
P8/G8
S9
1 0 0 1
P1/G1
P2/G2
P3/G3
P4/G4
P5/G5
P6/G6
P7/G7
P8/G8
P9/S9
1 0 1 0
S1
S2
S3
S4
S5
S6
S7
S8
S9
1 0 1 1
S1
S2
S3
S4
S5
S6
S7
S8
S9
1 1 0 0
S1
S2
S3
S4
S5
S6
S7
S8
S9
1 1 0 1
S1
S2
S3
S4
S5
S6
S7
S8
S9
1 1 1 0
S1
S2
S3
S4
S5
S6
S7
S8
S9
1 1 1 1
S1
S2
S3
S4
S5
S6
S7
S8
S9
PWM output or General-purpose output pin is selected by PGx(x=1 to 9) control data bit.
When the General-purpose Output Pin Function is selected, the correspondence between the output pins and the
respective display data is given in the table below.
Corresponding Display Data
Output Pins
1/5 Duty Mode
1/4 Duty Mode
1/3 Duty Mode
Static Mode
S1/P1/G1
D1
D1
D1
D1
S2/P2/G2
D6
D5
D4
D2
S3/P3/G3
D11
D9
D7
D3
S4/P4/G4
D16
D13
D10
D4
S5/P5/G5
D21
D17
D13
D4
S6/P6/G6
D26
D21
D16
D5
S7/P7/G7
D31
D25
D19
D7
S8/P8/G8
D36
D29
D22
D8
S9/P9/G9
D41
D33
D25
D9
When the General-purpose Output Pin Function is selected, the respective output pin outputs a “HIGH” level when its
corresponding display data is set to “1”. Likewise, it will output a “LOW” level, if its corresponding display data is set to “0”.
For example, S4/P4/G4 is used as a General-purpose Output Pin in case of 1/4 Duty, if its corresponding display data – D13
is set to “1”, then S4/P4/G4 will output “HIGH(VDD)” level. Likewise, if D13 is set to “0”, then S4/P4/G4 will output
“LOW(VSS)” level.
3. FL: Line Inversion or Frame Inversion switching control data
This control data bit selects either line inversion mode or frame inversion mode.
FL
Inversion Mode
Reset Condition
0
Line Inversion
○
1
Frame Inversion
Typically, when driving large capacitance LCD, Line inversion will increase the influence of crosstalk.
Regarding driving waveform, refer to LCD Driving Waveforms.
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Control Data Functions – continued
4. DR: 1/3 Bias drive or 1/2 Bias drive switching control data
This control data bit selects either 1/3 Bias drive or 1/2 Bias drive.
DR
Bias Drive Scheme
0
1/3 Bias drive
1
1/2 Bias drive
Reset Condition
○
-
5. DT: 1/5 Duty drive, 1/4 Duty drive, 1/3 Duty drive or Static drive switching control data
These control data bits select either 1/5 Duty drive, 1/4 Duty drive, 1/3 Duty drive or Static drive
DT0
DT1
Duty Drive Scheme
Reset Condition
0
0
Static drive
○
0
1
1/3 Duty drive
1
0
1/4 Duty drive
1
1
1/5 Duty drive
6. FC0, FC1, FC2 and FC3: Common / Segment output waveform frame frequency switching control data
These control data bits set the display frame frequency.
Display Frame Frequency
FC0
FC1
FC2
FC3
Reset Condition
fo(Hz)
fOSC(Note) / 12288
0
0
0
0
○
0
0
0
1
fOSC / 10752
0
0
1
0
fOSC / 9216
0
0
1
1
fOSC / 7680
0
1
0
0
fOSC / 6144
0
1
0
1
fOSC / 4608
0
1
1
0
fOSC / 3840
0
1
1
1
fOSC / 3072
1
0
0
0
fOSC / 2880
1
0
0
1
fOSC / 2688
1
0
1
0
fOSC / 2496
1
0
1
1
fOSC / 2304
1
1
0
0
fOSC / 2112
1
1
0
1
fOSC / 1920
1
1
1
0
fOSC / 1728
1
1
1
1
fOSC / 1536
(Note) fOSC: Internal oscillation frequency (600 kHz Typ)
7. OC: Internal oscillator operating mode / External clock operating mode switching control data
OC
Operating Mode
In/Out Pin(OSC/S90) Status
Reset Condition
0
Internal oscillator
S90 (segment output)
○
1
External Clock
OSC (clock input)
OC=1: OSC/S90 pin can be used as input clock pin when External Clock is set by the control data.
Internal oscillation / external clock select signal behavior is below.
Please input external clock after serial data sending.
SCE
SCL
SDI
1
0
1
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
D1
D2
OC
Display Data/
Control Data
Dev ice Code
8bits
SC
BU0
BU1
BU2
0
0
DD
2 bits
Internal oscillation・Extarnal Clock
Select signal(Internal signal)
Internal oscillation
(Internal signal)
Extarnal Clock
(OSC)
8. SC: Segment on/off switching control data
This control data bit controls the on/off state of the segments.
SC
Display State
Reset Condition
0
On
1
Off
○
Note that when the segments are turned off by setting SC to “1”, the segments are turned off by outputting segment off
waveforms from the segment output pins.
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Control Data Functions – continued
9. BU0,BU1 and BU2: Normal mode / Power-saving mode switching control data
These control data bits select either normal mode or power-saving mode.
Output Pin States During Key Scan
Segment Outputs
OSC
Standby
BU0 BU1 BU2
Mode
Oscillator
Common Outputs KS1
KS2
KS3
KS4
KS5
KS6
0
0
0
Normal Operating
Operating
H
H
H
H
H
H
0
0
1
L
L
L
L
L
H
0
1
0
L
L
L
L
H
H
0
1
1
L
L
L
H
H
H
Power
1
0
0
Stopped
Low(VSS)
L
L
H
H
H
H
-saving
1
0
1
L
H
H
H
H
H
1
1
0
H
H
H
H
H
H
1
1
1
H
H
H
H
H
H
Power-saving mode status: S1/P1/G1 to S9/P9/G9 = active only General-purpose output
S10 to OSC/S90 = low (VSS)
COM1 to COM5 = low (VSS)
Stop the LCD drive bias voltage generation circuit
Stop the Internal oscillation circuit
However, serial data transfer is possible when at Power-saving mode.
Reset
Condition
○
10. PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8 and PG9: PWM / General-purpose output switching control data
This control data bit select either PWM output or General-purpose output of Sx/Px/Gx pins. (x=1 to 9)
PGx(x=1 to 9)
Mode
Reset Condition
0
PWM output
○
1
General-purpose output
Normal behavior of changing GPO to PWM is below.
- PWM operation is started by command import timing of DD:01 during GPO PWM change.
- Please take care of reflect timing of new duty setting of DD:10 and DD:11 is from the next PWM.
SCE
DD:01
DD:00
DD:11
DD:10
GPO---> PWM change
New duty decided timing
PWM/GPO output
Start of PWM operation
Next PWM cycle
(PWM waveform in immediate duty)
(PWM waveform in new duty)
In order to avoid this operation, please input commands in reverse as below.
DD:10
DD:11
DD:01
DD:00
SCE
New duty decided timing
GPO--＞PWM change
PWM/GPO output
Start of PWM operation
(PWM waveform on new duty)
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Control Data Functions – continued
11. PF0, PF1, PF2, and PF3: PWM output waveform frame frequency switching control data
These control data bits set the frame frequency for PWM output waveforms.
PF0
PF1
PF2
PF3 PWM Output Frame Frequency fp(Hz)
Reset Condition
0
0
0
0
fOSC/4096
○
0
0
0
1
fOSC/3840
0
0
1
0
fOSC/3584
0
0
1
1
fOSC/3328
0
1
0
0
fOSC/3072
0
1
0
1
fOSC/2816
0
1
1
0
fOSC/2560
0
1
1
1
fOSC/2304
1
0
0
0
fOSC/2048
1
0
0
1
fOSC/1792
1
0
1
0
fOSC/1536
1
0
1
1
fOSC/1280
1
1
0
0
fOSC/1024
1
1
0
1
fOSC/768
1
1
1
0
fOSC/512
1
1
1
1
fOSC/256
12. CT0, CT1, CT2 and CT3: LCD display contrast switching control data
These control data bits set display contrast
LCD Drive Bias Voltage
CT0
CT1
CT2
CT3
for VLCD Level
0
0
0
0
1.000*VDD
0
0
0
1
0.975*VDD(Note)
0
0
1
0
0.950*VDD(Note)
0
0
1
1
0.925*VDD(Note)
0
1
0
0
0.900*VDD
0
1
0
1
0.875*VDD
0
1
1
0
0.850*VDD
0
1
1
1
0.825*VDD
1
0
0
0
0.800*VDD
1
0
0
1
0.775*VDD
1
0
1
0
0.750*VDD
1
0
1
1
0.725*VDD
1
1
0
0
0.700*VDD
1
1
0
1
0.675*VDD
1
1
1
0
0.650*VDD
1
1
1
1
0.625*VDD
This control data bit set VLCD maximum voltage for LCD drive voltage.
Reset Condition
○
-
(Note) [CT0,CT1,CT2,CT3] = [0,0,0,1], [0,0,1,0], [0,0,1,1] are disabled settings.
Avoid setting VLCD voltage under 2.5V.
And ensure “VDD - VLCD > 0.6” condition is satisfied.
Unstable IC output voltage may result if the above conditions are not satisfied.
The relationship of LCD display contrast setting and VLCD voltage
CT Setting
Formula
VDD= 6.000 VDD= 5.500 VDD= 5.000
0
VDD
VLCD= 6.000 VLCD= 5.500 VLCD= 5.000
1
0.975*VDD VLCD= 5.850 VLCD= 5.363 VLCD= 4.875
2
0.950*VDD VLCD= 5.700 VLCD= 5.225 VLCD= 4.750
3
0.925*VDD VLCD= 5.550 VLCD= 5.088 VLCD= 4.625
4
0.900*VDD VLCD= 5.400 VLCD= 4.950 VLCD= 4.500
5
0.875*VDD VLCD= 5.250 VLCD= 4.813 VLCD= 4.375
6
0.850*VDD VLCD= 5.100 VLCD= 4.675 VLCD= 4.250
7
0.825*VDD VLCD= 4.950 VLCD= 4.538 VLCD= 4.125
8
0.800*VDD VLCD= 4.800 VLCD= 4.400 VLCD= 4.000
9
0.775*VDD VLCD= 4.650 VLCD= 4.263 VLCD= 3.875
10
0.750*VDD VLCD= 4.500 VLCD= 4.125 VLCD= 3.750
11
0.725*VDD VLCD= 4.350 VLCD= 3.988 VLCD= 3.625
12
0.700*VDD VLCD= 4.200 VLCD= 3.850 VLCD= 3.500
13
0.675*VDD VLCD= 4.050 VLCD= 3.713 VLCD= 3.375
14
0.650*VDD VLCD= 3.900 VLCD= 3.575 VLCD= 3.250
15
0.625*VDD VLCD= 3.750 VLCD= 3.438 VLCD= 3.125
VDD= 4.500
VLCD= 4.500
VLCD= 4.388
VLCD= 4.275
VLCD= 4.163
VLCD= 4.050
VLCD= 3.938
VLCD= 3.825
VLCD= 3.713
VLCD= 3.600
VLCD= 3.488
VLCD= 3.375
VLCD= 3.263
VLCD= 3.150
VLCD= 3.038
VLCD= 2.925
VLCD= 2.813
VDD= 4.000
VLCD= 4.000
VLCD= 3.900
VLCD= 3.800
VLCD= 3.700
VLCD= 3.600
VLCD= 3.500
VLCD= 3.400
VLCD= 3.300
VLCD= 3.200
VLCD= 3.100
VLCD= 3.000
VLCD= 2.900
VLCD= 2.800
VLCD= 2.700
VLCD= 2.600
VLCD= 2.500
VDD= 3.000 Unit
VLCD= 3.000 V
VLCD= 2.925 V
VLCD= 2.850 V
VLCD= 2.775 V
VLCD= 2.700 V
VLCD= 2.625 V
VLCD= 2.550 V
VLCD= 2.475 V
VLCD= 2.400 V
VLCD= 2.325 V
VLCD= 2.250 V
VLCD= 2.175 V
VLCD= 2.100 V
VLCD= 2.025 V
VLCD= 1.950 V
VLCD= 1.875 V
Disabled
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Control Data Functions – continued
13. W11 to W18(Note), W21 to W28, W31 to W38, W41 to W48, W51 to W58, W61 to W68, W71 to W78, W81 to W88 and W91
to W98: PWM output waveform duty setting control data.
These control data bits set the high level pulse width (duty) for PWM output waveforms.
N = 1 to 9 , Tp = 1/fp
Wn1
Wn2
Wn3
Wn4
Wn5
Wn6
Wn7
Wn8
PWM Duty
Reset Condition
0
0
0
0
0
0
0
0
(0/256) x Tp
○
0
0
0
0
0
0
0
1
(1/256) x Tp
0
0
0
0
0
0
1
0
(2/256) x Tp
0
0
0
0
0
0
1
1
(3/256) x Tp
0
0
0
0
0
1
0
0
(4/256) x Tp
0
0
0
0
0
1
0
1
(5/256) x Tp
0
0
0
0
0
1
1
0
(6/256) x Tp
0
0
0
0
0
1
1
1
(7/256) x Tp
0
0
0
0
1
0
0
0
(8/256) x Tp
0
0
0
0
1
0
0
1
(9/256) x Tp
0
0
0
0
1
0
1
0
(10/256) x Tp
0
0
0
0
1
0
1
1
(11/256) x Tp
0
0
0
0
1
1
0
0
(12/256) x Tp
0
0
0
0
1
1
0
1
(13/256) x Tp
0
0
0
0
1
1
1
0
(14/256) x Tp
0
0
0
0
1
1
1
1
(15/256) x Tp
0
0
0
1
0
0
0
0
(16/256) x Tp
0
0
0
1
0
0
0
1
(17/256) x Tp
0
0
0
1
0
0
1
0
(18/256) x Tp
0
0
0
1
0
0
1
1
(19/256) x Tp
0
0
0
1
0
1
0
0
(20/256) x Tp
…
…
…
…
…
…
…
…
…
…
1
1
1
0
1
0
1
1
(235/256) x Tp
1
1
1
0
1
1
0
0
(236/256) x Tp
1
1
1
0
1
1
0
1
(237/256) x Tp
1
1
1
0
1
1
1
0
(238/256) x Tp
1
1
1
0
1
1
1
1
(239/256) x Tp
1
1
1
1
0
0
0
0
(240/256) x Tp
1
1
1
1
0
0
0
1
(241/256) x Tp
1
1
1
1
0
0
1
0
(242/256) x Tp
1
1
1
1
0
0
1
1
(243/256) x Tp
1
1
1
1
0
1
0
0
(244/256) x Tp
1
1
1
1
0
1
0
1
(245/256) x Tp
1
1
1
1
0
1
1
0
(246/256) x Tp
1
1
1
1
0
1
1
1
(247/256) x Tp
1
1
1
1
1
0
0
0
(248/256) x Tp
1
1
1
1
1
0
0
1
(249/256) x Tp
1
1
1
1
1
0
1
0
(250/256) x Tp
1
1
1
1
1
0
1
1
(251/256) x Tp
1
1
1
1
1
1
0
0
(252/256) x Tp
1
1
1
1
1
1
0
1
(253/256) x Tp
1
1
1
1
1
1
1
0
(254/256) x Tp
1
1
1
1
1
1
1
1
(255/256) x Tp
(Note) W11 to W18:S1/P1/G1 pwm duty data
W21 to W28:S2/P2/G2 pwm duty data
W31 to W38:S3/P3/G3 pwm duty data
W41 to W48:S4/P4/G4 pwm duty data
W51 to W58:S5/P5/G5 pwm duty data
W61 to W68:S6/P6/G6 pwm duty data
W71 to W78:S7/P7/G7 pwm duty data
W81 to W88:S8/P8/G8 pwm duty data
W91 to W98:S9/P9/G9 pwm duty data
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Display Data and Output Pin Correspondence
1. 1/5 Duty
Output Pin(Note)
S1/P1/G1
S2/P2/G2
S3/P3/G3
S4/P4/G4
S5/P5/G5
S6/P6/G6
S7/P7/G7
S8/P8/G8
S9/P9/G9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
S46
S47
S48
S49
S50
S51
S52
S53
S54
S55
S56
S57
S58
S59
S60
S61
S62
S63
COM1
D1
D6
D11
D16
D21
D26
D31
D36
D41
D46
D51
D56
D61
D66
D71
D76
D81
D86
D91
D96
D101
D106
D111
D116
D121
D126
D131
D136
D141
D146
D151
D156
D161
D166
D171
D176
D181
D186
D191
D196
D201
D206
D211
D216
D221
D226
D231
D236
D241
D246
D251
D256
D261
D266
D271
D276
D281
D286
D291
D296
D301
D306
D311
COM2
D2
D7
D12
D17
D22
D27
D32
D37
D42
D47
D52
D57
D62
D67
D72
D77
D82
D87
D92
D97
D102
D107
D112
D117
D122
D127
D132
D137
D142
D147
D152
D157
D162
D167
D172
D177
D182
D187
D192
D197
D202
D207
D212
D217
D222
D227
D232
D237
D242
D247
D252
D257
D262
D267
D272
D277
D282
D287
D292
D297
D302
D307
D312
COM3
D3
D8
D13
D18
D23
D28
D33
D38
D43
D48
D53
D58
D63
D68
D73
D78
D83
D88
D93
D98
D103
D108
D113
D118
D123
D128
D133
D138
D143
D148
D153
D158
D163
D168
D173
D178
D183
D188
D193
D198
D203
D208
D213
D218
D223
D228
D233
D238
D243
D248
D253
D258
D263
D268
D273
D278
D283
D288
D293
D298
D303
D308
D313
COM4
D4
D9
D14
D19
D24
D29
D34
D39
D44
D49
D54
D59
D64
D69
D74
D79
D84
D89
D94
D99
D104
D109
D114
D119
D124
D129
D134
D139
D144
D149
D154
D159
D164
D169
D174
D179
D184
D189
D194
D199
D204
D209
D214
D219
D224
D229
D234
D239
D244
D249
D254
D259
D264
D269
D274
D279
D284
D289
D294
D299
D304
D309
D314
COM5
D5
D10
D15
D20
D25
D30
D35
D40
D45
D50
D55
D60
D65
D70
D75
D80
D85
D90
D95
D100
D105
D110
D115
D120
D125
D130
D135
D140
D145
D150
D155
D160
D165
D170
D175
D180
D185
D190
D195
D200
D205
D210
D215
D220
D225
D230
D235
D240
D245
D250
D255
D260
D265
D270
D275
D280
D285
D290
D295
D300
D305
D310
D315
(Note) The Segment Output Pin function is assumed to be selected for the output pins – S1/P1/G1 to S9/P9/G9, KS1/S79 to KS6/S84,
KI1/S85 to KI5/S89, OSC/S90. Also, COM5/S78 pin is used as Common output.
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TSZ22111 • 15 • 001
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BU97530KVT
Display Data and Output Pin Correspondence – continued
Output Pin(Note)
S64
S65
S66
S67
S68
S69
S70
S71
S72
S73
S74
S75
S76
S77
KS1/S79
KS2/S80
KS3/S81
KS4/S82
KS5/S83
KS6/S84
KI1/S85
KI2/S86
KI3/S87
KI4/S88
KI5/S89
OSC/S90
COM1
D316
D321
D326
D331
D336
D341
D346
D351
D356
D361
D366
D371
D376
D381
D386
D391
D396
D401
D406
D411
D416
D421
D426
D431
D436
D441
COM2
D317
D322
D327
D332
D337
D342
D347
D352
D357
D362
D367
D372
D377
D382
D387
D392
D397
D402
D407
D412
D417
D422
D427
D432
D437
D442
COM3
D318
D323
D328
D333
D338
D343
D348
D353
D358
D363
D368
D373
D378
D383
D388
D393
D398
D403
D408
D413
D418
D423
D428
D433
D438
D443
COM4
D319
D324
D329
D334
D339
D344
D349
D354
D359
D364
D369
D374
D379
D384
D389
D394
D399
D404
D409
D414
D419
D424
D429
D434
D439
D444
COM5
D320
D325
D330
D335
D340
D345
D350
D355
D360
D365
D370
D375
D380
D385
D390
D395
D400
D405
D410
D415
D420
D425
D430
D435
D440
D445
(Note) The Segment Output Pin function is assumed to be selected for the output pins – S1/P1/G1 to S9/P9/G9, KS1/S79 to KS6/S84,
KI1/S85 to KI5/S89, OSC/S90. Also, COM5/S78 pin is used as Common output.
To illustrate further, the states of the S21 output pin is given in the table below.
Display Data
State of S21 Output Pin
D101 D102 D103 D104 D105
0
0
0
0
0
LCD Segments corresponding to COM1 to COM5 are OFF.
0
0
0
0
1
LCD Segment corresponding to COM5 is ON.
0
0
0
1
0
LCD Segment corresponding to COM4 is ON.
0
0
0
1
1
LCD Segments corresponding to COM4 and COM5 are ON.
0
0
1
0
0
LCD Segment corresponding to COM3 is ON.
0
0
1
0
1
LCD Segments corresponding to COM3 and COM5 are ON.
0
0
1
1
0
LCD Segments corresponding to COM3 and COM4 are ON.
0
0
1
1
1
LCD Segments corresponding to COM3, COM4 and COM5 are ON.
0
1
0
0
0
LCD Segment corresponding to COM2 is ON.
0
1
0
0
1
LCD Segments corresponding to COM2 and COM5 are ON.
0
1
0
1
0
LCD Segments corresponding to COM2 and COM4 are ON.
0
1
0
1
1
LCD Segments corresponding to COM2, COM4 and COM5 are ON.
0
1
1
0
0
LCD Segments corresponding to COM2 and COM3 are ON.
0
1
1
0
1
LCD Segments corresponding to COM2, COM3, and COM5 are ON.
0
1
1
1
0
LCD Segments corresponding to COM2, COM3, and COM4 are ON.
0
1
1
1
1
LCD Segments corresponding to COM2, COM3, COM4 and COM5 are ON.
1
0
0
0
0
LCD Segment corresponding to COM1 is ON.
1
0
0
0
1
LCD Segments corresponding to COM1 and COM5 are ON.
1
0
0
1
0
LCD Segments corresponding to COM1 and COM4 are ON.
1
0
0
1
1
LCD Segments corresponding to COM1, COM4 and COM5 are ON.
1
0
1
0
0
LCD Segments corresponding to COM1 and COM3 are ON.
1
0
1
0
1
LCD Segments corresponding to COM1, COM3 and COM5 are ON.
1
0
1
1
0
LCD Segments corresponding to COM1, COM3 and COM4 are ON.
1
0
1
1
1
LCD Segments corresponding to COM1, COM3, COM4 and COM5 are ON.
1
1
0
0
0
LCD Segments corresponding to COM1 and COM2 are ON.
1
1
0
0
1
LCD Segments corresponding to COM1, COM2 and COM5 are ON.
1
1
0
1
0
LCD Segments corresponding to COM1, COM2 and COM4 are ON.
1
1
0
1
1
LCD Segments corresponding to COM1, COM2, COM4 and COM5 are ON.
1
1
1
0
0
LCD Segments corresponding to COM1, COM2 and COM3 are ON.
1
1
1
0
1
LCD Segments corresponding to COM1, COM2, COM3 and COM5 are ON.
1
1
1
1
0
LCD Segments corresponding to COM1, COM2, COM3 and COM4 are ON.
1
1
1
1
1
LCD Segments corresponding to COM1, COM2, COM3, COM4 and COM5 are ON.
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TSZ22111 • 15 • 001
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BU97530KVT
Display Data and Output Pin Correspondence – continued
2. 1/4 Duty
Output Pin(Note)
S1/P1/G1
S2/P2/G2
S3/P3/G3
S4/P4/G4
S5/P5/G5
S6/P6/G6
S7/P7/G7
S8/P8/G8
S9/P9/G9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
S46
S47
S48
S49
S50
S51
S52
S53
S54
S55
S56
S57
S58
S59
S60
S61
S62
S63
COM1
D1
D5
D9
D13
D17
D21
D25
D29
D33
D37
D41
D45
D49
D53
D57
D61
D65
D69
D73
D77
D81
D85
D89
D93
D97
D101
D105
D109
D113
D117
D121
D125
D129
D133
D137
D141
D145
D149
D153
D157
D161
D165
D169
D173
D177
D181
D185
D189
D193
D197
D201
D205
D209
D213
D217
D221
D225
D229
D233
D237
D241
D245
D249
COM2
D2
D6
D10
D14
D18
D22
D26
D30
D34
D38
D42
D46
D50
D54
D58
D62
D66
D70
D74
D78
D82
D86
D90
D94
D98
D102
D106
D110
D114
D118
D122
D126
D130
D134
D138
D142
D146
D150
D154
D158
D162
D166
D170
D174
D178
D182
D186
D190
D194
D198
D202
D206
D210
D214
D218
D222
D226
D230
D234
D238
D242
D246
D250
COM3
D3
D7
D11
D15
D19
D23
D27
D31
D35
D39
D43
D47
D51
D55
D59
D63
D67
D71
D75
D79
D83
D87
D91
D95
D99
D103
D107
D111
D115
D119
D123
D127
D131
D135
D139
D143
D147
D151
D155
D159
D163
D167
D171
D175
D179
D183
D187
D191
D195
D199
D203
D207
D211
D215
D219
D223
D227
D231
D235
D239
D243
D247
D251
COM4
D4
D8
D12
D16
D20
D24
D28
D32
D36
D40
D44
D48
D52
D56
D60
D64
D68
D72
D76
D80
D84
D88
D92
D96
D100
D104
D108
D112
D116
D120
D124
D128
D132
D136
D140
D144
D148
D152
D156
D160
D164
D168
D172
D176
D180
D184
D188
D192
D196
D200
D204
D208
D212
D216
D220
D224
D228
D232
D236
D240
D244
D248
D252
(Note) The Segment Output Pin function is assumed to be selected for the output pins – S1/P1/G1 to S9/P9/G9, COM5/S78, KS1/S79 to KS6/S84,
KI1/S85 to KI5/S89, OSC/S90.
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TSZ22111 • 15 • 001
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02.Aug.2019 Rev.006
BU97530KVT
Display Data and Output Pin Correspondence – continued
Output Pin(Note)
S64
S65
S66
S67
S68
S69
S70
S71
S72
S73
S74
S75
S76
S77
COM5/S78
KS1/S79
KS2/S80
KS3/S81
KS4/S82
KS5/S83
KS6/S84
KI1/S85
KI2/S86
KI3/S87
KI4/S88
KI5/S89
OSC/S90
COM1
D253
D257
D261
D265
D269
D273
D277
D281
D285
D289
D293
D297
D301
D305
D309
D313
D317
D321
D325
D329
D333
D337
D341
D345
D349
D353
D357
COM2
D254
D258
D262
D266
D270
D274
D278
D282
D286
D290
D294
D298
D302
D306
D310
D314
D318
D322
D326
D330
D334
D338
D342
D346
D350
D354
D358
COM3
D255
D259
D263
D267
D271
D275
D279
D283
D287
D291
D295
D299
D303
D307
D311
D315
D319
D323
D327
D331
D335
D339
D343
D347
D351
D355
D359
COM4
D256
D260
D264
D268
D272
D276
D280
D284
D288
D292
D296
D300
D304
D308
D312
D316
D320
D324
D328
D332
D336
D340
D344
D348
D352
D356
D360
(Note) The Segment Output Pin function is assumed to be selected for the output pins – S1/P1/G1 to S9/P9/G9, COM5/S78, KS1/S79 to KS6/S84,
KI1/S85 to KI5/S89, OSC/S90.
To illustrate further, the states of the S21 output pin is given in the table below.
Display Data
State of S21 Output Pin
D81
D82
D83
D84
0
0
0
0
LCD Segments corresponding to COM1 to COM4 are OFF.
0
0
0
1
LCD Segment corresponding to COM4 is ON.
0
0
1
0
LCD Segment corresponding to COM3 is ON.
0
0
1
1
LCD Segments corresponding to COM3 and COM4 are ON.
0
1
0
0
LCD Segment corresponding to COM2 is ON.
0
1
0
1
LCD Segments corresponding to COM2 and COM4 are ON.
0
1
1
0
LCD Segments corresponding to COM2 and COM3 are ON.
0
1
1
1
LCD Segments corresponding to COM2, COM3 and COM4 are ON.
1
0
0
0
LCD Segment corresponding to COM1 is ON.
1
0
0
1
LCD Segments corresponding to COM1 and COM4 are ON.
1
0
1
0
LCD Segments corresponding to COM1 and COM3 are ON.
1
0
1
1
LCD Segments corresponding to COM1, COM3 and COM4 are ON.
1
1
0
0
LCD Segments corresponding to COM1 and COM2 are ON.
1
1
0
1
LCD Segments corresponding to COM1, COM2, and COM4 are ON.
1
1
1
0
LCD Segments corresponding to COM1, COM2, and COM3 are ON.
1
1
1
1
LCD Segments corresponding to COM1, COM2, COM3 and COM4 are ON.
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TSZ22111 • 15 • 001
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TSZ02201-0P4P0D300570-1-2
02.Aug.2019 Rev.006
BU97530KVT
Display Data and Output Pin Correspondence – continued
3. 1/3 Duty
Output Pin(Note)
S1/P1/G1
S2/P2/G2
S3/P3/G3
S4/P4/G4
S5/P5/G5
S6/P6/G6
S7/P7/G7
S8/P8/G8
S9/P9/G9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
S46
S47
S48
S49
S50
S51
S52
S53
S54
S55
S56
S57
S58
S59
S60
S61
S62
S63
COM1
D1
D4
D7
D10
D13
D16
D19
D22
D25
D28
D31
D34
D37
D40
D43
D46
D49
D52
D55
D58
D61
D64
D67
D70
D73
D76
D79
D82
D85
D88
D91
D94
D97
D100
D103
D106
D109
D112
D115
D118
D121
D124
D127
D130
D133
D136
D139
D142
D145
D148
D151
D154
D157
D160
D163
D166
D169
D172
D175
D178
D181
D184
D187
COM2
D2
D5
D8
D11
D14
D17
D20
D23
D26
D29
D32
D35
D38
D41
D44
D47
D50
D53
D56
D59
D62
D65
D68
D71
D74
D77
D80
D83
D85
D89
D92
D95
D98
D101
D104
D107
D110
D113
D116
D119
D122
D125
D128
D131
D134
D137
D140
D143
D146
D149
D152
D155
D158
D161
D164
D167
D170
D173
D176
D179
D182
D185
D188
COM3
D3
D6
D9
D12
D15
D18
D21
D24
D27
D30
D33
D36
D39
D42
D45
D48
D51
D54
D57
D60
D63
D66
D69
D72
D75
D78
D81
D84
D87
D90
D93
D96
D99
D102
D105
D108
D111
D114
D117
D120
D123
D126
D129
D132
D135
D138
D141
D144
D147
D150
D153
D156
D159
D162
D165
D168
D171
D174
D177
D180
D183
D186
D189
(Note) The Segment Output Pin function is assumed to be selected for the output pins – S1/P1/G1 to S9/P9/G9, COM5/S78, KS1/S79 to KS6/S84,
KI1/S85 to KI5/S89, OSC/S90
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TSZ22111 • 15 • 001
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TSZ02201-0P4P0D300570-1-2
02.Aug.2019 Rev.006
BU97530KVT
Display Data and Output Pin Correspondence – continued
Output Pin(Note)
S64
S65
S66
S67
S68
S69
S70
S71
S72
S73
S74
S75
S76
S77
COM5/S78
KS1/S79
KS2/S80
KS3/S81
KS4/S82
KS5/S83
KS6/S84
KI1/S85
KI2/S86
KI3/S87
KI4/S88
KI5/S89
OSC/S90
COM1
D190
D193
D196
D199
D202
D205
D208
D211
D214
D217
D220
D223
D226
D229
D232
D235
D238
D241
D244
D247
D250
D253
D256
D259
D262
D265
D268
COM2
D191
D194
D197
D200
D203
D206
D209
D212
D215
D218
D221
D224
D227
D230
D233
D236
D239
D242
D245
D248
D251
D254
D257
D260
D263
D266
D269
COM3
D192
D195
D198
D201
D204
D207
D210
D213
D216
D219
D222
D225
D228
D231
D234
D237
D240
D243
D246
D249
D252
D255
D258
D261
D264
D267
D270
(Note) The Segment Output Pin function is assumed to be selected for the output pins – S1/P1/G1 to S9/P9/G9, COM5/S78, KS1/S79 to KS6/S84,
KI1/S85 to KI5/S89, OSC/S90
To illustrate further, the states of the S21 output pin is given in the table below.
Display data
State of S21 Output Pin
D61
D62
D63
0
0
0
LCD Segments corresponding to COM1 to COM3 are OFF.
0
0
1
LCD Segment corresponding to COM3 is ON.
0
1
0
LCD Segment corresponding to COM2 is ON.
0
1
1
LCD Segments corresponding to COM2 and COM3 are ON.
1
0
0
LCD Segment corresponding to COM1 is ON.
1
0
1
LCD Segments corresponding to COM1 and COM3 are ON.
1
1
0
LCD Segments corresponding to COM1 and COM2 are ON.
1
1
1
LCD Segments corresponding to COM1, COM2 and COM3 are ON.
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Display Data and Output Pin Correspondence – continued
4. Static
Output Pin(Note)
S1/P1/G1
S2/P2/G2
S3/P3/G3
S4/P4/G4
S5/P5/G5
S6/P6/G6
S7/P7/G7
S8/P8/G8
S9/P9/G9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
S46
S47
S48
S49
S50
S51
S52
S53
S54
S55
S56
S57
S58
S59
S60
S61
S62
S63
COM1
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
(Note) The Segment Output Pin function is assumed to be selected for the output pins – S1/P1/G1 to S9/P9/G9, COM5/S78, KS1/S79 to KS6/S84,
KI1/S85 to KI5/S89, OSC/S90.
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Display Data and Output Pin Correspondence – continued
Output Pin(Note)
S64
S65
S66
S67
S68
S69
S70
S71
S72
S73
S74
S75
S76
S77
COM5/S78
KS1/S79
KS2/S80
KS3/S81
KS4/S82
KS5/S83
KS6/S84
KI1/S85
KI2/S86
KI3/S87
KI4/S88
KI5/S89
OSC/S90
COM1
D64
D65
D66
D67
D68
D69
D70
D71
D72
D73
D74
D75
D76
D77
D78
D79
D80
D81
D82
D83
D84
D85
D86
D87
D88
D89
D90
(Note) The Segment Output Pin function is assumed to be selected for the output pins – S1/P1/G1 to S9/P9/G9, COM5/S78, KS1/S79 to KS6/S84,
KI1/S85 to KI5/S89, OSC/S90.
To illustrate further, the states of the S21 output pin is given in the table below.
Display Data
State of S21 Output Pin
D21
0
LCD Segment corresponding to COM1 is OFF.
LCD Segment corresponding to COM1 is ON.
1
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Serial Data Output
1. When SCL is stopped at the low level(Note 1)
SCE
SCL
SDI
1
1
0
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
SDO
X
KD1
KD2
KD27 KD28 KD29 KD30
PA
Output Data
Figure 15. Serial Data Output Format
(Note 1)
1. X=Don’t care
2. B0 to B3, A0 to A3: Serial Interface address
3. Serial Interface address: 43H
4. KD1 to KD30: Key data
5. PA: Power-saving acknowledge data
6. If a key data read operation is executed when SDO is high, the read key data (KD1 to KD30) and power-saving acknowledge data (PA) will be invalid.
2. When SCL is stopped at the high level(Note 2)
SCE
SCL
SDI
1
1
0
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
SDO
KD1
KD2 KD3
KD28 KD29 KD30
PA
X
Output Data
Figure 16. Serial Data Output Format
(Note 2)
1. X=Don’t care
2. B0 to B3, A0 to A3: Serial Interface address
3. Serial Interface address: 43H
4. KD1 to KD30: Key data
5. PA: Power-saving acknowledge data
6. If a key data read operation is executed when SDO is high, the read key data (KD1 to KD30) and power-saving acknowledge data (PA) will be invalid.
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Output Data
1. KD1 to KD30: Key Data
When a key matrix of up to 30 keys is formed from the KS1 to KS6 output pins and the KI1 to KI5 input pins and one of
those keys are pressed, the key output data corresponding to that key will be set to 1. The table shows the relationship
between those pins and the key data bits.
Item
KS1
KS2
KS3
KS4
KS5
KS6
KI1
KD1
KD6
KD11
KD16
KD21
KD26
KI2
KD2
KD7
KD12
KD17
KD22
KD27
KI3
KD3
KD8
KD13
KD18
KD23
KD28
KI4
KD4
KD9
KD14
KD19
KD24
KD29
KI5
KD5
KD10
KD15
KD20
KD25
KD30
2. PA: Power-saving Acknowledge Data
This output data is set to the state when the key is pressed. In that case SDO will go to the low level. If serial data is
input during this period and the mode is set (normal mode or power-saving mode), the IC will be set to that mode. PA is set
to 1 in the power-saving mode and to 0 in the normal mode.
Power-saving Mode
Power-saving mode is set up by setting at least one of control data BU0, BU1 or BU2 set to 1. The segment outputs will all
go low and the common outputs will also go low, and the oscillator on the OSC pin will stop (it will be started by a key press).
This reduces power dissipation. This mode is cleared by sending control data with all the BU0 BU1 and BU2 set to 0.
However, note that the S1/P1/G1 to S9/P9/G9 outputs can be used as General-purpose output pins according to the state
of the P0 to P3 control data bits, even in power-saving mode. (See the Control Data Functions.)
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Key Scan Operation Function
1. Key Scan Timing
The key scan period is 4608T(s). To reliably determine the on/off state of the keys, the BU97530KVT scans the keys twice
and determines that a key has been pressed when the key data agrees. It outputs a key data read request (a low level on
SDO) 9840T(s) after starting a key scan. If the key data does not agree and a key was pressed at that point, it scans the keys
again. Thus the BU97530KVT cannot detect a key press shorter than 9840T(s).
KS1
*
KS2
*
KS3
*
KS4
*
KS5
*
1
1
2
*
2
3
*
3
*
4
4
*
5
5
*
6
KS6
6
9216T(s)
T=
1
fOSC
Figure 17. Key Scan Timing(Note)
(Note) In power-saving mode the high/low state of these pins is determined by the BU0 to BU2 bits in the control data. Key scan output signals are not output
from pins that are set “L”.
2. In Normal Mode
The pins KS1 to KS6 are set “H”.
When a key is pressed a key scan is started and the keys are scanned until all keys are released. Multiple key presses are
recognized by determining whether multiple key data bits are set.
If a key is pressed for longer than 9840T(s) (Where T=1/f OSC ) the BU97530KVT outputs a key data read request (a low level
on SDO) to the controller. The controller acknowledges this request and reads the key data. However, if SCE is high during a
serial data transfer, SDO will be set “H”.
After the controller reads the key data, the key data read request is cleared (SDO is set high) and the BU97530KVT performs
another key scan. Also note that SDO, being an open-drain output, requires a pull-up resistor (between 1 kΩ and 10kΩ)
Key Input 1
Key Input 2
Key scan
9840T(s)
9840T(s)
9840T(s)
SCE
Serial data transf er
Serial data transf er
Key address(43H)
Serial data transf er
Key address
Key address
SDI
SDO
Key data read
Key data read
Key data read request
Key data read request
Key data read
Key data read request
1
T=
f OSC
Figure 18. Key Scan Operation in Normal Mode
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Key Scan Operation Function – continued
3. In Power-saving Mode
The pins KS1 to KS6 are set to high or low by the BU0 to BU2 bits in the control data. (See the Control Data Functions for
details.)
If a key on one of the lines corresponding to a KS1 to KS6 pin which is set high is pressed, the oscillation is started and a key
scan is performed. Keys are scanned until all keys are released. Multiple key presses are recognized by
determining whether multiple key data bits are set.
If a key is pressed for longer than 9840T(s)(Where T=1/fOSC) the BU97530KVT outputs a key data read request (a low
level on SDO) to the controller. The controller acknowledges this request and reads the key data. However, if SCE is high
during a serial data transfer, SDO will be set high.
After the controller reads the key data, the key data read request is cleared (SDO is set high) and the BU97530KVT
performs another key scan. However, this does not clear power-saving mode. Also note that SDO, being an open-drain
output, requires a pull-up resistor (between 1kΩ and 10kΩ).
Power-saving mode key scan example
Example: BU0=0, BU1=0, BU2=1 (only KS6 high level output)
(L)KS1
(L)KS2
(L)KS3
When any one of these keys is pressed,
the oscillation is started and the keys are scanned.
(L)KS4
(L)KS5
(H)KS6
(Note)
Kl1
Kl2
Kl3
Kl4
Kl5
(Note) These diodes are required to reliable recognize multiple key presses on the KS6 line when power-saving mode state with only KS6 high, as in the above
example. That is, these diodes prevent incorrect operations due to sneak currents in the KS6 key scan output signal when keys on the KS1 to KS5 lines
are pressed at the same time.
Key Input 2
(KS6 line)
Key scan
9840T(s)
9840T(s)
SCE
Serial data transf er
Serial data transf er
Key address(43H)
Serial data transf er
Key address
SDI
SDO
Key data read
Key data read
Key data read request
Key data read request
T=
1
f OSC
Figure 19. Key Scan Operation in Power-saving Mode
Multiple Key Presses
Although the BU97530KVT is capable of key scanning without inserting diodes for dual key presses, triple key presses on the
KI1 to KI5 input pin lines or multiple key presses on the KS1 to KS6 output pin lines, multiple key presses other than these
cases may result in keys that were not pressed recognized as having been pressed. Therefore, a diode must be inserted in
series with each key. If applications do not recognize multiple key presses of three or more keys, they should ignore the key
data when it has three or more “1” bit.
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Controller Key Data Read Technique
When the controller receives a key data read request from BU97530KVT, it performs a key data read acquisition operation
using either the Timer Based Key Data Acquisition or the Interrupt Based Key Data Acquisition.
1.Timer Based Key Data Acquisition Technique
Under the Timer Based Key Data Acquisition Technique, the controller uses a timer to determine the states of the keys
(on or off) and read the key data. Please refer to the flowchart below.
SCE =「L」
NO
SDO =「L」
YES
Key data read
processing
Key data read processing: Refer to “Serial Data Output”
Figure 20. Flowchart
In this technique, the controller uses a timer to determine key on/off states and read the key data. The controller must check
the SDO state when SCE is low every t7 period without fail. If SDO is low, the controller recognizes that a key has been
pressed and executes the key data read operation.
The period t7 in this technique must satisfy the following condition.
t7>t4+t5+t6
If a key data read operation is executed when SDO is high, the read key data (KD1 to KD30) and power-saving acknowledge
data (PA) will be invalid.
Key on
Key on
Key Input 1
Key scan
t3
t3
t4
t3
SCE
t6
t6
t6
SDI
t5
t5
t5
Key data read
SDO
Key data read request
t7
Controller determination
(key on)
t7
t7
t7
Controller determination
(key on)
Controller determination
(key on)
Controller determination
(key on)
Controller determination
(key on)
t3: Key scan execution time when the key data agreed for two key scans. (9840T(s))
t4: Key scan execution time when the key data did not agree for two key scans and the key scan was executed again.
(19680T(s)) T = 1 / fOSC
t5: Key address (43H) transfer time
t6: Key data read time
Figure 21. Timer based key data read operation
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Controller Key Data Read Technique – continued
2. Interrupt Based Key Data Acquisition Technique
Under the Interrupt Based Key Data Acquisition Technique, the controller uses interrupts to determine the state of the
keys (on or off) and read the key data. Please refer to the flow chart diagram below.
SCE =「L」
SDO =「L」
NO
YES
Key data read
processing
Wait for at
least t8
NO
SDO =「H」
YES
Key off
Key data read processing: Refer to “Serial Data Output”
Figure 22. Flowchart
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Controller Key Data Read Technique – continued
In this technique, the controller uses interrupts to determine key on/off states and read the key data. The controller must
check the SDO state when SCE is low. If SDO is low, the controller recognizes that a key has been pressed and executes the
key data read operation. After that the next key on/off determination is performed after the time t8 has elapsed by checking
the SDO state when SCE is low and reading the key data. The period t8 in this technique must satisfy t8 > t4.
If a key data read operation is executed when SDO is high, the read key data (KD1 to KD30) and power-saving acknowledge
data (PA) will be invalid.
Key on
Key on
Key Input 1
Key scan
t3
t3
t4
t3
SCE
t6
t6
t6
t6
SDI
t5
t5
t5
t5
Key data read
SDO
Key data read request
Controller
determination
(key on)
Controller
determination
(key on)
t8
t8
t8
t8
Controller
determination
(key on)
Controller
determination
(key on)
Controller
determination
(key on)
Controller
determination
(key on)
t3: Key scan execution time when the key data agreed for two key scans. (9840T[s])
t4: Key scan execution time when the key data did not agree for two key scans and the key scan was executed again.
(19680T[s]) T = 1 / fOSC
t5: Key address (43H) transfer time
t6: Key data read time
Figure 23. Interrupt Based Key Data Read Operation
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LCD Driving Waveforms
1. Line Inversion 1/5 Duty 1/3 Bias Drive Scheme
fo[Hz]
VLCD
VLCD1
VLCD2
COM1
0V
VLCD
VLCD1
VLCD2
COM2
0V
VLCD
VLCD1
VLCD2
COM3
0V
VLCD
VLCD1
VLCD2
COM4
0V
VLCD
VLCD1
VLCD2
COM5
0V
VLCD
LCD driver output w hen all LCD
VLCD1
segments corresponding to COM1,
VLCD2
COM2, COM3, COM4 and COM5 are off
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1
corresponding to COM1 is on
VLCD2
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1
corresponding to COM2 is on
VLCD2
0V
VLCD
LCD driver output w hen LCD segments
VLCD1
corresponding to COM1 and COM2 are on
VLCD2
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1
corresponding to COM3 is on
VLCD2
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1
corresponding to COM4 is on
VLCD2
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1
corresponding to COM5 is on
VLCD2
0V
VLCD
LCD driver output w hen LCD segments
VLCD1
corresponding to COM1, COM2 and COM3 are on
VLCD2
0V
VLCD
LCD driver output w hen LCD segments
VLCD1
corresponding to COM1, COM2, COM3
VLCD2
and COM4 are on
0V
VLCD
LCD driver output w hen all LCD
VLCD1
segments corresponding to COM1,
VLCD2
COM2, COM3, COM4 and COM5 are on
0V
Figure 24. LCD Waveform (Line Inversion, 1/5 Duty, 1/3 Bias)
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LCD Driving Waveforms – continued
2. Line Inversion 1/5 Duty 1/2 Bias Drive Scheme
fo[Hz]
VLCD
VLCD1, VLCD2
COM1
0V
VLCD
VLCD1, VLCD2
COM2
0V
VLCD
VLCD1, VLCD2
COM3
0V
VLCD
VLCD1, VLCD2
COM4
0V
VLCD
VLCD1, VLCD2
COM5
0V
LCD driver output w hen all LCD
VLCD
segments corresponding to COM1,
VLCD1, VLCD2
COM2, COM3, COM4 and COM5 are off
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1, VLCD2
corresponding to COM1 is on
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1, VLCD2
corresponding to COM2 is on
0V
VLCD
LCD driver output w hen LCD segments
VLCD1, VLCD2
corresponding to COM1 and COM2 are on
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1, VLCD2
corresponding to COM3 is on.
0V
VLCD
LCD driver output w hen LCD segments
VLCD1, VLCD2
corresponding to COM1 and COM3 are on
0V
VLCD
LCD driver output w hen LCD segments
VLCD1, VLCD2
corresponding to COM2 and COM3 are on
0V
VLCD
LCD driver output w hen LCD segments
VLCD1, VLCD2
corresponding to COM1, COM2 and COM3 are on
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1, VLCD2
corresponding to COM4 is on
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1, VLCD2
corresponding to COM5 is on
0V
VLCD
LCD driver output w hen LCD segments
VLCD1, VLCD2
corresponding to COM1, COM2, COM3
0V
and COM4 are on
VLCD
VLCD1, VLCD2
0V
LCD driver output w hen all LCD
segments corresponding to COM1,
COM2, COM3, COM4 and COM5 are on
Figure 25. LCD Waveform (Line Inversion, 1/5 Duty, 1/2 Bias)
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LCD Driving Waveforms – continued
3. Line Inversion 1/4 Duty 1/3 Bias Drive Scheme
fo[Hz]
VLCD
VLCD1
VLCD2
COM1
0V
VLCD
VLCD1
VLCD2
COM2
0V
VLCD
VLCD1
VLCD2
COM3
0V
VLCD
VLCD1
VLCD2
COM4
0V
VLCD
LCD driver output w hen all LCD
VLCD1
segments corresponding to COM1,
VLCD2
COM2, COM3 and COM4 are off
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1
corresponding to COM1 is on
VLCD2
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1
corresponding to COM2 is on
VLCD2
0V
VLCD
LCD driver output w hen LCD segments
VLCD1
corresponding to COM1 and COM2 are on
VLCD2
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1
corresponding to COM3 is on
VLCD2
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1
corresponding to COM4 is on
VLCD2
0V
VLCD
LCD driver output w hen LCD segments
VLCD1
corresponding to COM2 and COM3 are on
VLCD2
0V
VLCD
LCD driver output w hen all LCD
VLCD1
segments corresponding to COM1,
VLCD2
COM2, COM3 and COM4 are on
0V
Figure 26. LCD Waveform (Line Inversion, 1/4 Duty, 1/3 Bias)
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LCD Driving Waveforms – continued
4. Line Inversion 1/4 Duty 1/2 Bias Drive Scheme
fo[Hz]
VLCD
VLCD1, VLCD2
COM1
0V
VLCD
VLCD1, VLCD2
COM2
0V
VLCD
VLCD1, VLCD2
COM3
0V
VLCD
VLCD1, VLCD2
COM4
0V
LCD driver output w hen all LCD
VLCD
segments corresponding to COM1,
VLCD1, VLCD2
COM2, COM3 and COM4 are off
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1, VLCD2
corresponding to COM1 is on
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1, VLCD2
corresponding to COM2 is on
0V
VLCD
LCD driver output w hen LCD segments
VLCD1, VLCD2
corresponding to COM1 and COM2 are on
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1, VLCD2
corresponding to COM3 is on
0V
VLCD
LCD driver output w hen LCD segments
VLCD1, VLCD2
corresponding to COM1 and COM3 are on
0V
VLCD
LCD driver output w hen LCD segments
VLCD1, VLCD2
corresponding to COM2 and COM3 are on
0V
VLCD
LCD driver output w hen LCD segments
VLCD1, VLCD2
corresponding to COM1, COM2 and COM3 are on
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1, VLCD2
corresponding to COM4 is on
0V
VLCD
LCD driver output w hen LCD segments
VLCD1, VLCD2
corresponding to COM2 and COM4 are on
0V
VLCD
LCD driver output w hen all LCD
VLCD1, VLCD2
segments corresponding to COM1,
0V
COM2, COM3 and COM4 are on
Figure 27. LCD Waveform (Line Inversion, 1/4 Duty, 1/2 Bias)
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LCD Driving Waveforms – continued
5. Line Inversion 1/3 Duty 1/3 Bias Drive Scheme
fo[Hz]
VLCD
VLCD1
VLCD2
COM1
0V
VLCD
VLCD1
VLCD2
COM2
0V
VLCD
VLCD1
VLCD2
COM3
0V
VLCD
LCD driver output w hen all LCD
VLCD1
segments corresponding to COM1,
VLCD2
COM2 and COM3 are off
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1
corresponding to COM1 is on
VLCD2
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1
corresponding to COM2 is on
VLCD2
0V
VLCD
LCD driver output w hen LCD segments
VLCD1
corresponding to COM1 and COM2 are on
VLCD2
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1
corresponding to COM3 is on
VLCD2
0V
VLCD
LCD driver output w hen LCD segments
VLCD1
corresponding to COM1 and COM3 are on
VLCD2
0V
VLCD
LCD driver output w hen LCD segments
VLCD1
corresponding to COM2 and COM3 are on
VLCD2
0V
VLCD
LCD driver output w hen all LCD
VLCD1
segments corresponding to COM1,
VLCD2
COM2 and COM3 are on
0V
Figure 28. LCD Waveform (Line Inversion, 1/3 Duty, 1/3 Bias) (Note)
(Note) COM4 function is same as COM1 at 1/3 duty.
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LCD Driving Waveforms – continued
6. Line Inversion 1/3 Duty 1/2 Bias Drive Scheme
fo[Hz]
VLCD
VLCD1, VLCD2
COM1
0V
VLCD
VLCD1, VLCD2
COM2
0V
VLCD
VLCD1, VLCD2
COM3
0V
LCD driver output w hen all LCD
VLCD
segments corresponding to COM1,
VLCD1, VLCD2
COM2 and COM3 are off
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1, VLCD2
corresponding to COM1 is on
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1, VLCD2
corresponding to COM2 is on
0V
VLCD
LCD driver output w hen LCD segments
VLCD1, VLCD2
corresponding to COM1 and COM2 are on
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1, VLCD2
corresponding to COM3 is on
0V
VLCD
LCD driver output w hen LCD segments
VLCD1, VLCD2
corresponding to COM1 and COM3 are on
0V
VLCD
LCD driver output w hen LCD segments
VLCD1, VLCD2
corresponding to COM2 and COM3 are on
0V
VLCD
LCD driver output w hen all LCD
VLCD1, VLCD2
segments corresponding to COM1,
0V
COM2 and COM3 are on
Figure 29. LCD Waveform (Line Inversion, 1/3 Duty, 1/2Bias) (Note)
(Note) COM4 function is same as COM1 at 1/3 duty.
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LCD Driving Waveforms – continued
7. Line Inversion Static Drive Scheme
fo[Hz]
VLCD
COM1
0V
VLCD
LCD driver output w hen LCD
segment corresponding to COM1 is off
0V
VLCD
LCD driver output w hen LCD
segment corresponding to COM1 is on
0V
Figure 30. LCD Waveform (Line Inversion, Static)
(Note)
(Note) COM2, COM3 and COM4 function are same as COM1 at Static.
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LCD Driving Waveforms – continued
8. Frame Inversion 1/5 Duty 1/3 Bias Drive Scheme
fo[Hz]
VLCD
VLCD1
VLCD2
COM1
0V
VLCD
VLCD1
VLCD2
COM2
0V
VLCD
VLCD1
VLCD2
COM3
0V
VLCD
VLCD1
VLCD2
COM4
0V
VLCD
VLCD1
VLCD2
COM5
0V
VLCD
LCD driver output w hen all LCD
VLCD1
segments corresponding to COM1,
VLCD2
COM2, COM3, COM4 and COM5 are off
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1
corresponding to COM1 is on
VLCD2
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1
corresponding to COM2 is on
VLCD2
0V
VLCD
LCD driver output w hen LCD segments
VLCD1
corresponding to COM1 and COM2 are on
VLCD2
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1
corresponding to COM3 is on
VLCD2
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1
corresponding to COM4 is on
VLCD2
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1
corresponding to COM5 is on
VLCD2
0V
VLCD
LCD driver output w hen LCD segments
VLCD1
corresponding to COM1, COM2 and COM3 are on
VLCD2
0V
VLCD
LCD driver output w hen LCD segments
VLCD1
corresponding to COM1, COM2, COM3
VLCD2
and COM4 are on
0V
VLCD
LCD driver output w hen all LCD
VLCD1
segments corresponding to COM1,
VLCD2
COM2, COM3, COM4 and COM5 are on
0V
Figure 31. LCD Waveform (Frame Inversion, 1/5 Duty, 1/3Bias)
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LCD Driving Waveforms – continued
9. Frame Inversion 1/5 Duty 1/2 Bias Drive Scheme
fo[Hz]
VLCD
VLCD1, VLCD2
COM1
0V
VLCD
VLCD1, VLCD2
COM2
0V
VLCD
VLCD1, VLCD2
COM3
0V
VLCD
VLCD1, VLCD2
COM4
0V
VLCD
VLCD1, VLCD2
COM5
0V
LCD driver output w hen all LCD
VLCD
segments corresponding to COM1,
VLCD1, VLCD2
COM2, COM3, COM4 and COM5 are off
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1, VLCD2
corresponding to COM1 is on
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1, VLCD2
corresponding to COM2 is on
0V
VLCD
LCD driver output w hen LCD segments
VLCD1, VLCD2
corresponding to COM1 and COM2 are on
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1, VLCD2
corresponding to COM3 is on
0V
VLCD
LCD driver output w hen LCD segments
VLCD1, VLCD2
corresponding to COM1 and COM3 are on
0V
VLCD
LCD driver output w hen LCD segments
VLCD1, VLCD2
corresponding to COM2 and COM3 are on
0V
VLCD
LCD driver output w hen LCD segments
VLCD1, VLCD2
corresponding to COM1, COM2 and COM3 are on
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1, VLCD2
corresponding to COM4 is on
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1, VLCD2
corresponding to COM5 is on
0V
VLCD
LCD driver output w hen LCD segments
VLCD1, VLCD2
corresponding to COM1, COM2, COM3
0V
and COM4 are on
VLCD
VLCD1, VLCD2
0V
LCD driver output w hen LCD segments
corresponding to COM1, COM2, COM3,
COM4 and COM5 are on
Figure 32. LCD Waveform (Frame Inversion, 1/5 Duty, 1/2Bias)
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LCD Driving Waveforms – continued
10. Frame Inversion 1/4 Duty 1/3 Bias Drive Scheme
fo[Hz]
VLCD
VLCD1
VLCD2
COM1
0V
VLCD
VLCD1
VLCD2
COM2
0V
VLCD
VLCD1
VLCD2
COM3
0V
VLCD
VLCD1
VLCD2
COM4
0V
VLCD
LCD driver output w hen all LCD
VLCD1
segments corresponding to COM1,
VLCD2
COM2, COM3 and COM4 are off
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1
corresponding to COM1 is on
VLCD2
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1
corresponding to COM2 is on
VLCD2
0V
VLCD
LCD driver output w hen LCD segments
VLCD1
corresponding to COM1 and COM2 are on
VLCD2
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1
corresponding to COM3 is on
VLCD2
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1
corresponding to COM4 is on
VLCD2
0V
VLCD
LCD driver output w hen LCD segments
VLCD1
corresponding to COM2 and COM3 are on
VLCD2
0V
VLCD
LCD driver output w hen all LCD
VLCD1
segments corresponding to COM1,
VLCD2
COM2, COM3 and COM4 are on
0V
Figure 33. LCD Waveform (Frame Inversion, 1/4 Duty, 1/3Bias)
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LCD Driving Waveforms – continued
11. Frame Inversion 1/4 Duty 1/2 Bias Drive Scheme
fo[Hz]
VLCD
VLCD1, VLCD2
COM1
0V
VLCD
VLCD1, VLCD2
COM2
0V
VLCD
VLCD1, VLCD2
COM3
0V
VLCD
VLCD1, VLCD2
COM4
0V
LCD driver output w hen all LCD
VLCD
segments corresponding to COM1,
VLCD1, VLCD2
COM2, COM3 and COM4 are off
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1, VLCD2
corresponding to COM1 is on
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1, VLCD2
corresponding to COM2 is on
0V
VLCD
LCD driver output w hen LCD segments
VLCD1, VLCD2
corresponding to COM1 and COM2 are on
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1, VLCD2
corresponding to COM3 is on
0V
VLCD
LCD driver output w hen LCD segments
VLCD1, VLCD2
corresponding to COM1 and COM3 are on
0V
VLCD
LCD driver output w hen LCD segments
VLCD1, VLCD2
corresponding to COM2 and COM3 are on
0V
VLCD
LCD driver output w hen LCD segments
VLCD1, VLCD2
corresponding to COM1, COM2 and COM3 are on
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1, VLCD2
corresponding to COM4 is on
0V
VLCD
LCD driver output w hen LCD segments
VLCD1, VLCD2
corresponding to COM2 and COM4 are on
0V
VLCD
LCD driver output w hen all LCD
VLCD1, VLCD2
segments corresponding to COM1,
0V
COM2, COM3 and COM4 are on
Figure 34. LCD Waveform (Frame Inversion, 1/4 Duty, 1/2Bias)
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LCD Driving Waveforms – continued
12. Frame Inversion 1/3 Duty 1/3 Bias Drive Scheme
fo[Hz]
VLCD
VLCD1
VLCD2
COM1
0V
VLCD
VLCD1
VLCD2
COM2
0V
VLCD
VLCD1
VLCD2
COM3
0V
VLCD
LCD driver output w hen all LCD
VLCD1
segments corresponding to COM1,
VLCD2
COM2 and COM3 are off
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1
corresponding to COM1 is on
VLCD2
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1
corresponding to COM2 is on
VLCD2
0V
VLCD
LCD driver output w hen LCD segments
VLCD1
corresponding to COM1 and COM2 are on
VLCD2
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1
corresponding to COM3 is on
VLCD2
0V
VLCD
LCD driver output w hen LCD segments
VLCD1
corresponding to COM1 and COM3 are on
VLCD2
0V
VLCD
LCD driver output w hen LCD segments
VLCD1
corresponding to COM2 and COM3 are on
VLCD2
0V
VLCD
LCD driver output w hen all LCD
VLCD1
segments corresponding to COM1,
VLCD2
COM2 and COM3 are on
0V
Figure 35. LCD Waveform (Frame Inversion, 1/3 Duty, 1/3Bias) (Note)
(Note) COM4 function is same as COM1 at 1/3 duty.
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LCD Driving Waveforms – continued
13. Frame Inversion 1/3 Duty 1/2 Bias Drive Scheme
fo[Hz]
VLCD
VLCD1, VLCD2
COM1
0V
VLCD
VLCD1, VLCD2
COM2
0V
VLCD
VLCD1, VLCD2
COM3
0V
LCD driver output w hen all LCD
VLCD
segments corresponding to COM1,
VLCD1, VLCD2
COM2 and COM3 are off
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1, VLCD2
corresponding to COM1 is on
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1, VLCD2
corresponding to COM2 is on
0V
VLCD
LCD driver output w hen LCD segments
VLCD1, VLCD2
corresponding to COM1 and COM2 are on
0V
VLCD
LCD driver output w hen only LCD segment
VLCD1, VLCD2
corresponding to COM3 is on
0V
VLCD
LCD driver output w hen LCD segments
VLCD1, VLCD2
corresponding to COM1 and COM3 are on
0V
VLCD
LCD driver output w hen LCD segments
VLCD1, VLCD2
corresponding to COM2 and COM3 are on
0V
VLCD
LCD driver output w hen all LCD
VLCD1, VLCD2
segments corresponding to COM1,
0V
COM2 and COM3 are on
Figure 36. LCD Waveform (Frame Inversion, 1/3 Duty, 1/2 Bias) (Note)
(Note) COM4 function is same as COM1 at 1/3 duty.
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LCD Driving Waveforms – continued
14. Frame Inversion Static
fo[Hz]
V LCD
COM1
0V
V LCD
LCD driver output when LCD
segment corresponding to COM1 is off
0V
V LCD
LCD driver output when LCD
segment corresponding to COM1 is on
0V
Figure 37. LCD Waveform (Frame Inversion, Static) (Note)
(Note) COM2, COM3 and COM4 function are same as COM1 at Static.
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Oscillation Stabilization Time
It must be noted that the oscillation of the internal oscillation circuit is unstable for a maximum of 100μs (oscillation
stabilization time) after oscillation has started.
Internal oscillation
circuit
Oscillation
stabilization time
(100µs Max)
Oscillation stopped
Oscillation operation
(under normal conditions)
when control data OC = "0" and BU0 to BU2 ="000"
Figure 38. Oscillation Stabilization Time
Power-saving Mode Operation in External Clock Mode
After receiving [BU0,BU1,BU2]=[1,1,1], BU97530KVT enter to power saving mode synchronized with frame then Segment and
Common pins output VSS level.
Therefore, in external clock mode, it is necessary to input the external clock based on each frame frequency setting after
sending [BU0,BU1,BU2]=[1,1,1].
For the required number of clock, refer to “6. FC0, FC1, FC2 and FC3: Common / Segment output waveform frame frequency
switching control data”.
For example, please input the external clock as below.
[FC0,FC1,FC2,FC3]=[0,0,0,0]: In case of fOSC/12288 setting, it needs over 12288clk,
[FC0,FC1,FC2,FC3]=[0,1,0,1]: In case of fOSC/4608 setting, it needs over 4608clk,
[FC0,FC1,FC2,FC3]=[1,1,1,1]: In case of fOSC/1536 setting, it needs over 1536clk
Please refer to the timing chart below.
SCE
SCL
SDI
1
0
1
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
Dev ice Code
8bits
D1
D2
OC
SC
BU0
Display Data/
Control Data
BU1
BU2
0
0
DD
2 bits
OSC
To input External clock at
least 1 f rame or more
SEG
VSS
COM1
VSS
COM2
VSS
COM3
VSS
COM4
VSS
Output at Power sav ing mode(VSS lev el)
Output at Normal mode
Power sav ing
Last Display f lame
of Sirial data
receiv ing
Figure 39. External Clock Stop Timing(1/4-Duty)
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Voltage Detection Type Reset Circuit (VDET)
The Voltage Detection Type Reset Circuit generates an output signal that resets the system when power is applied for
the first time and when the power supply voltage drops {that is, for example, the power supply voltage is less than or equal to
the power down detection voltage (VDET = 1.8V Typ)}. To ensure that this reset function works properly, it is recommended
that a capacitor be connected to the power supply line so that both the power supply voltage (VDD) rise time when power is
first applied and the power supply voltage (VDD) fall time when the voltage drops are at least 1ms.
To refrain from data transmission is strongly recommended while power supply is rising up or falling down to prevent from the
occurrence of disturbances on transmission and reception.
VDD
t1
t2
VDD Min
VDD Min
t3
VDD=1.0V
VSS
Figure 40. VDET Detection Timing
Power supply voltage VDD fall time: t1 ≥ 1ms
Power supply voltage VDD rise time: t2 ≥ 1ms
Internal reset power supply retain time: t3 ≥ 1ms
When it is difficult to keep above conditions, it is possibility to cause meaningless display due to no IC initialization.
Please execute the IC initialization as quickly as possible after Power-on to reduce such an affect.
See the IC initialization flow as below.
But since commands are not received when the power is OFF, the IC initialization flow is not the same function as POR.
Set [BU0,BU1,BU2]=[1,1,1](power-saving mode) and SC=1(Display Off) as quickly as possible after Power-on.
BU97530KVT can receive commands in 0ns after Power-on(VDD level is 90%).
Reset Condition
When BU97530KVT is initialized, the internal status after power supply has been reset as the following table.
Instruction
Key Scan Mode
S1/P1/G1 to S9/P9/G9 Pin
Bias Setting
Duty Setting
Line / Frame Inversion Mode
Display Frame Frequency
Display Clock Mode
LCD Display
Power Mode
PWM / GPO Output
PWM Frequency
PWM Duty
Display Contrast Setting
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TSZ22111 • 15 • 001
At Reset Condition
[KM0,KM1,KM2]=[1,1,1]:Keyscan no use
[P0,P1,P2,P3]=[0,0,0,0]:all segment output
DR=0:1/3 Bias
[DT0,DT1]=[1,0]:1/4 Duty
FL=0:Line Inversion
[FC0,FC1,FC2,FC3]=[0,0,0,0]:fOSC /12288
OC=0:Internal oscillator
SC=1:OFF
[BU0, BU1, BU2]=[1,1,1]:Power saving mode
PGx=0:PWM output(x=1 to 9)
[PF0,PF1,PF2,PF3]=[0,0,0,0]:fOSC /4096
[Wn1 to Wn8]=[0,0,0,0,0,0,0,0]:0/256)xTp
(n=1 to 9,Tp=1/fp)
[CT0,CT1,CT2,CT3]=[0,0,0,0]:
VLCD Level is 1.00*VDD
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Operational Notes
1.
Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power
supply pins.
2.
Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the
digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog
block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and
aging on the capacitance value when using electrolytic capacitors.
3.
Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.
4.
Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5.
Recommended Operating Conditions
The function and operation of the IC are guaranteed within the range specified by the recommended operating
conditions. The characteristic values are guaranteed only under the conditions of each item specified by the electrical
characteristics.
6.
Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may
flow instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power
supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring,
and routing of connections.
7.
Operation Under Strong Electromagnetic Field
Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction.
8.
Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may
subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply
should always be turned off completely before connecting or removing it from the test setup during the inspection
process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during
transport and storage.
9.
Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment)
and unintentional solder bridge deposited in between pins during assembly to name a few.
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Operational Notes – continued
10. Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small
charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and
cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the
power supply or ground line.
11. Regarding the Input Pin of the IC
In the construction of this IC, P-N junctions are inevitably formed creating parasitic diodes or transistors. The
operation of these parasitic elements can result in mutual interference among circuits, operational faults, or physical
damage. Therefore, conditions which cause these parasitic elements to operate, such as applying a voltage to an
input pin lower than the ground voltage should be avoided. Furthermore, do not apply a voltage to the input pins
when no power supply voltage is applied to the IC. Even if the power supply voltage is applied, make sure that the
input pins have voltages within the values specified in the electrical characteristics of this IC.
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Ordering Information
B
U
9
7
5
3
0
Part Number
K
V
T
Package
KVT : TQFP100V
-
E2
Product Rank
Packaging Specification
E2: Embossed tape and reel
(TQFP100V)
Marking Diagram
TQFP100V (TOP VIEW)
Part Number Marking
Lot Number Marking
BU97530KVT
1PIN MARK
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Physical Dimension and Packing Information
Package Name
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TQFP100V
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Version / Revision History
Version
001
002
003
004
005
006
date
description
21. Apr. 2014 New Release
Page.8-15 Modify 3-SPI Data Transfer Format Wn0 delete(fix to 0)
Page.40,41,47,48 Delete COM4 description
21. Oct. 2014
Page.51 Delete Wn0 description in RESET CONDITION Table
Page.54 Modify Ordering Information
Page.4 Add External Clock Duty.
Page.5 Modify Data Setup Time Min limit.
Page.5 Modify Data Hold Time Min limit.
Page.5 Modify SCE Wait Time Min limit.
Page.5 Modify SCE Setup Time Min limit.
Page.5 Modify SCE Hold Time Min limit.
Page.5 Modify High-level Clock Pulse Width Min limit.
Page.5 Modify Low-level Clock Pulse Width (Write) Min limit.
Page.5 Add Clock Cycle Time.
2. Mar. 2015
Page.5 Add Low-Level Clock Pulse Width (Read).
Page.5 Add RPU and CL explanation.
Page.5 Add SDO signal, tccyc and tclwr on Figure5 Serial Interface Timing.
Page.5 Modify tclww from tclw on Figure5 Serial Interface Timing.
Page.5 Modify reference level of tchw to VIH1,VIH2 from 50% on Figure5 Serial Interface Timing.
Page.5 Modify reference level of tclww to VIL1 from 50% on Figure5 Serial Interface Timing.
Page.5 Delete tcp on Figure5 Serial Interface Timing (1.When SCL is stopped at the low level) .
Page.5 Delete tcs on Figure5 Serial Interface Timing (2.When SCL is stopped at the high level).
Page.54,55 Add packing specification for tray.
18. Aug. 2015 Page.8-15 Modify 3-SPI Data Transfer Format added FC3
Page 3. Modify Temperature condition in Absolute Maximum Ratings.Ta=25˚C → Removed
Page 3. Modify Maximum Supply Voltage in Absolute Maximum Ratings. -0.3 to +6.5 → -0.3 to
+7.0.
Page 3. Modify Input Voltage in Absolute Maximum Ratings. -0.3 to +6.5 → -0.3 to +7.0.
Page 3. Add OSC in Absolute Maximum Ratings Input Voltage.
Page 3. Add Caution2 in Absolute Maximum Ratings condition. (Moved from Operational Notes)
Page 3. Add OSC pin in Electrical Characteristics table.
Page 4. Add External Clock Rise Time, External Clock Fall Time and External Clock Duty in
Oscillation Characteristics.
Page 6. Add KI1/S85 to KI5/S89 in Pin Description I/O and Handling when unused Input terminal
description.
11. Jan. 2019
Page 6. Add OSC/S90 in Pin Description I/O and Handling when unused Input terminal description
Page 16 to 20. Add Reset condition in Control Data Functions.
Page 16. Add 3. FL: Line Inversion or Frame Inversion control data explanation.
Page 17. Add External Clock input timing function in 7. OC: Internal oscillator operating mode /
External clock operating mode control data.
Page 19. Add Note and The relationship of LCD display contrast setting and VLCD voltage in
” 12. CT0, CT1, CT2 and CT3: LCD display contrast switching control data”.
Page 50. Add Power-saving mode operation in external clock mode.
Page 51. Add Voltage Detection Type Reset Circuit (VDET) explanation.
Change Note number.
Correction of errors.
02. Aug. 2019 Page. 9,11,13 and 15 Add Description
www.rohm.com
© 2014 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
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TSZ02201-0P4P0D300570-1-2
02.Aug.2019 Rev.006
Notice
Precaution on using ROHM Products
1.
Our Products are designed and manufactured for application in ordinary electronic equipment (such as AV equipment,
OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you
intend to use our Products in devices requiring extremely high reliability (such as medical equipment (Note 1), transport
equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car
accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or
serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.
Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any
damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific
Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅣ
CLASSⅢ
2.
ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3.
Our Products are designed and manufactured for use under standard conditions and not under any special or
extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any
special or extraordinary environments or conditions. If you intend to use our Products under any special or
extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of
product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used.
However, recommend sufficiently about the residue.) ; or Washing our Products by using water or water-soluble
cleaning agents for cleaning residue after soldering
[h] Use of the Products in places subject to dew condensation
4.
The Products are not subject to radiation-proof design.
5.
Please verify and confirm characteristics of the final or mounted products in using the Products.
6.
In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7.
De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in
the range that does not exceed the maximum junction temperature.
8.
Confirm that operation temperature is within the specified range described in the product specification.
9.
ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1.
When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2.
In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PGA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.004
Precautions Regarding Application Examples and External Circuits
1.
If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2.
You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1.
Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl 2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2.
Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3.
Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4.
Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
trade act, please consult with ROHM in case of export.
Precaution Regarding Intellectual Property Rights
1.
All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data.
2.
ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the
Products with other articles such as components, circuits, systems or external equipment (including software).
3.
No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM
will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to
manufacture or sell products containing the Products, subject to the terms and conditions herein.
Other Precaution
1.
This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2.
The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3.
In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4.
The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice-PGA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.004
Datasheet
General Precaution
1. Before you use our Products, you are requested to carefully read this document and fully understand its contents.
ROHM shall not be in any way responsible or liable for failure, malfunction or accident arising from the use of any
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this document is current as of the issuing date and subject to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the latest information with a ROHM sales
representative.
3.
The information contained in this document is provided on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate and/or error-free. ROHM shall not be in any way responsible or
liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccuracy or errors of or
concerning such information.
Notice – WE
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.001
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