BU97540KV-ME2

厂商：
ROHM(罗姆)
封装：
VQFP80_12X12MM
描述：
IC DRVR 335 SEGMENT 80VQFP

数据手册：

下载BU97540KV-ME2.pdf

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数据手册
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BU97540KV-ME2 数据手册

Datasheet LCD Segment Drivers Multi-function Segment Drivers BU97540KV-M MAX335 Segment(67segx5COM) General Description Key Specifications The BU97540KV-M is 1/5, 1/4, 1/3, or 1/1 duty  Supply Voltage Range: + +2.7V to +6.0V general-purpose LCD driver that can be used for  Operating Temperature Range: -40°C to +85°C frequency display in electronic tuners under the control of  Max Segments: 335 Segments a microcontroller. The BU97540KV-M can drive up to 335  Display Duty: 1/1,1/3,1/4,1/5 Selectable LCD Segments directly. The BU97540KV-M can also  Bias: 1/1,1/2,1/3,1/4 Selectable control up to 9 general-purpose output ports.  Interface: 3Wire Serial Interface These products also incorporate a key scan circuit that accepts input from up to 30 keys to reduce printed circuit board wiring Packages VQFP80 W(Typ) × D(Typ) × H(Max) Features (Note1)  AEC-Q100 Qualified  Key input function for up to 30 keys (A key scan is performed only when a key is pressed.)  Supports 1 chip(Master) mode and 2 chip(Master + Slave) mode  Either 1/5, 1/4, 1/3 or 1/1 duty (static) can be selected with the serial control data. 1 chip mode(only Master): 1/5 duty drive: Up to 335 segments can be driven 1/4 duty drive: Up to 272 segments can be driven 1/3 duty drive: Up to 204 segments can be driven VQFP80 1/1 duty drive: Up to 68 segments can be driven 14.00mm x 14.00mm x 1.60mm 2 chip mode(Master + Slave): 1/5 duty drive: Up to 680 segments can be driven 1/4 duty drive: Up to 548 segments can be driven 1/3 duty drive: Up to 411 segments can be driven 1/1 duty drive: Up to 137 segments can be driven  Serial data control of frame frequency for common and segment output waveforms.  Serial data control of switching between the segment output port , PWM output port and general-purpose output port functions.(Max 9 ports)  Built-in OSC circuit  Integrated Power-on Reset circuit  No external component  Low power consumption design  Supports Line and Frame Inversion (Note1) Grade 3 Applications  Car audio, Home electrical appliance, Meter equipment etc. ○Product structure：Silicon monolithic integrated circuit .www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・14・001 ○This product has no designed protection against radioactive rays 1/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M Typical Application Circuit Key Matrix P1/G1 P9/G9 KS1 / S53 KI1 / S59 KS6 / S58 KI5 / S63 (General Purpose/PWM Ports) (For control of backlight) COM1/S71 COM2/S70 COM3/S69 COM4/S68 COM5/S67 VDD +5V S1/P1/G1 *1 S9/P9/G9 LCD Panel (Up to 335 Segments) S10 SCE SCL SDI From Control To Control +5V S52 S64 S65 SDO S72 S66/TESTIN OSC_IN/S73 1Chip Mode(Master) P1/G1 P9/G9 (General Purpose/PWM Ports) (For control of backlight) Key Matrix P1/G1 P9/G9 KS1 / S53 KI1 / S59 KS6 / S58 KI5 / S63 (General Purpose/PWM Ports) (For control of backlight) COM1/S71 COM2/S70 COM3/S69 COM4/S68 COM5/S67 VDD +5V S1/P1/G1 *1 MS MASTER S9/P9/G9 S10 SCE From Control S52 SCL SDI SYNCIO/S64 CLKIO/S65 To Control SDO S72 OSC_IN/S73 S66/TESTIN +5V COM1/S71 COM2/S70 COM3/S69 LCD Panel (Up to 680 Segments) COM4/S68 (Note 2) COM5/S67 VDD +5V S1/P1/G1 *1 S9/P9/G9 S10 SCE SCL S52 SDI SYNCIO/S64 CLKIO/S65 SDO SLAVE +5V MS S66 S72 OSC_IN/S73 KS1 / S53 KS6 / S58 KI1 / S59 KI5 / S63 2 Chip Mode(Master with Slave) (Note2) Insert capacitors between VDD and VSS C≥0.1uF Figure 1. Typical Application Circuit www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 2/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 COMMON Driver ・・・・・・ S1/P1/G1 S10 S9/P9/G9 S65/CLKIO S64/SYNCIO S67/COM5 COM4 COM3 COM1 COM2 Block Diagram S66/TESTIN BU97540KV-M SEGMENT Driver/Latch MS Clock /Timing Generator OSC / S73 Control Register PWM Register SCE Shift Register SCL Serial Interface LCD voltage Generator SDI SDO KEY BUFFER VLCD VDD VLCD1 POR KEY SCAN VLCD2 VSS KS1/ S53 KS2/ S54 KS3/ S55 KS4/ S56 KS6/ S58 KS5/ S57 KI1 / S59 KI2 / S60 KI3 / S61 KI4 / S62 KI5 / S63 VSS Figure 2. Block Diagram 41 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 KS1 / S53 KS2 / S54 KS3 / S55 KS4 / S56 KS5 / S57 KS6 / S58 KI1 / S59 KI2 / S60 KI3 / S61 60 KI4 / S62 Pin Arrangement 61 40 KI5 / S63 S42 SYNCIO / S64 S41 CLKIO / S65 S40 S66 / TESTIN S39 COM5 / S67 S38 COM4 / S68 S37 COM3 / S69 S36 COM2 / S70 S35 COM1 / S71 S34 VDD S33 VSS S32 MS S31 SDO S30 S72 S29 OSC_IN / S73 S28 SCE S27 SCL S26 SDI S25 S1 / P1 / G1 S24 S2 / P2 / G2 S23 21 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 / P9 / G9 S8 / P8 / G8 S7 / P7 / G7 S6 / P6 / G6 S5 / P5 / G5 S4 / P4 / G4 S3 / P3 / G3 80 Figure 3. Pin Configuration (TOP VIEW) www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 3/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M Absolute Maximum Ratings (Ta = 25°C, VSS = 0V) Parameter Maximum Supply Voltage Input Voltage Symbol VDD max VIN1 VIN2 Pd Topr Tstg Allowable Loss Operating Temperature Storage Temperature Conditions Rating -0.3 to +7.0 -0.3 to +7.0 -0.3 to +7.0 (Note3) 1.2 -40 to +85 -55 to +125 VDD SCE, SCL, SDI KI1 to KI5 Unit V V V W °C °C (Note3) When use more than Ta=25°C, subtract 12mW per degree. (Using ROHM standard board) (Board size: 70mm×70mm×1.6mm material: FR4 board copper foil: land pattern only) Caution: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated over the absolute maximum ratings. Recommend Operating Conditions (Ta = -40°C to +85°C, VSS = 0V) Parameter Symbol Supply Voltage Conditions VDD Rating Typ 5.0 Min 2.7 Max 6.0 Unit V Electrical Characteristics for the Allowable Operating Ranges Parameter Hysteresis Power-on Detection Voltage “H” Level Input Voltage SCE, SCL, SDI KI1 to KI5 Min - Limit Typ 0.03 VDD 0.1 VDD Max - VDET VDD 1.3 1.8 2.2 V VIH1 SCE,SCL,SDI, SYNCIO,CLKIO SCE, SCL, SDI, SYNCIO,CLKIO KI1 to KI5 SCE, SCL, SDI KI1 to KI5 SYNCIO,CLKIO KI1 to KI5 KI1 to KI5 4.5V ≤ VDD ≤ 6.0V 0.4VDD - VDD V 0.8VDD - VDD 0.7VDD - VDD 0 - 0.2VDD V 50 100 0.05VDD 250 V KΩ SDO VO=6.0V - - 6.0 µA VI = 5.5V - - 5.0 µA -5.0 - - µA VDD-0.9 - - VDD-0.9 - - VDD-0.9 VDD-1.0 VDD-0.9 0.2 1/2 VDD -0.9 1/2 VDD -0.9 2/3 VDD -0.9 1/3 VDD -0.9 2/3 VDD -0.9 1/3 VDD -0.9 VDD-0.5 0.5 0.1 - VDD-0.2 0.9 0.9 0.9 1.5 0.5 0.9 1/2 VDD +0.9 1/2 VDD +0.9 2/3 VDD +0.9 1/3 VDD +0.9 2/3 VDD +0.9 1/3 VDD +0.9 Symbol VH1 VH2 VIH2 “L” Level Input Voltage Input Floating Voltage Pull-down Resistance Output Off Leakage Current “H” Level Input Current “L” Level Input Current “H” Level Output Voltage “L” Level Output Voltage Middle Level Output Voltage VIH3 VIL1 VIF RPD IOFFH Pin VOH1 SCE, SCL, SDI SYNCIO,CLKIO SCE, SCL, SDI SYNCIO,CLKIO S1 to S73 VOH2 COM1 to COM5 VOH3 VOH4 VOH5 VOL1 VOL2 VOL3 VOL4 VOL5 VOL6 VMID1 P1/G1 to P9/G9 KS1 to KS6 SYNCIO,CLKIO S1 to S70 COM1 to COM5 P1/G1 to P9/G9 KS1 to KS6 SDO SYNCIO,CLKIO S1 to S73 VMID2 COM1 to COM5 VMID3 S1 to S73 VMID4 S1 to S73 VMID5 COM1 to COM5 VMID6 COM1 to COM5 IIH1 IIL1 www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 Conditions 2.7V ≤ VDD < 4.5V VDD=5.0V VI = 0V IO = -20µA, VLCD=1.00*VDD IO = -100µA, VDD=1.00*VDD IO = -1mA IO = -500uA IO = -1mA IO = 20µA IO = 100µA IO = 1mA IO = 25uA IO = 1mA IO = 1mA 1/2 bias IO = ±20µA VLCD=1.00*VDD 1/2 bias IO = ±100µA VLCD=1.00*VDD 1/3 bias IO = ±20µA VLCD=1.00*VDD 1/3 bias IO = ±20µA VLCD=1.00*VDD 1/3 bias IO = ±100µA VLCD=1.00*VDD 1/3 bias IO = ±100µA VLCD=1.00*VDD 4/66 - Unit V V V V V TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M Electrical Characteristics – continued Parameter Current Consumption Pin Symbol IDD1 IDD2 Conditions VDD VDD IDD3 Power-saving mode 1chip mode VDD = 5.0V Output open, 1/2 bias Frame frequency=80Hz VLCD=1.00*VDD 1chip mode VDD = 5.0V Output open,1/3 bias Frame frequency=80Hz VLCD=1.00*VDD 2chip mode : Master VDD = 5.0V Output open,1/3 bias Frame frequency=80Hz VLCD=1.00*VDD 2chip mode : Slave VDD = 5.0V Output open,1/3 bias Frame frequency=80Hz VLCD=1.00*VDD VDD IDD4 VDD IDD5 VDD Min - Limit Typ - Max 15 - 105 220 µA - 130 270 µA - 195 370 µA - 105 220 µA Min 300 540 562 Limit Typ 600 625 Max 720 660 688 30 - 1000 kHz 30 50 70 % Unit µA Oscillation Characteristics (Ta = -40 to +85°C, VDD = 2.7V to 6.0V, VSS = 0.0V) Parameter Symbol Pin Oscillator Frequency 1 Oscillator Frequency 2 Oscillator Frequency 3 External Clock (Note4) Frequency fosc1 fosc2 fosc3 - fosc4 OSC_IN/S73 tdty OSC_IN/S73 External Clock Duty Conditions VDD = 2.7V to 6.0V VDD = 5.0V VDD = 6.0V External clock mode (OC=1) External clock mode (OC=1) Unit kHz kHz kHz (Note4) Frame frequency is decided external frequency and dividing ratio of FC0 to FC3 setting. 【Reference Data】 700 650 VDD = 6.0V fosc[kHz] 600 VDD = 5.0V VDD = 3.3V 550 VDD = 2.7V 500 450 400 350 300 -40 -20 0 20 40 60 80 Temperature[°C] Figure 4. Typical Temperature Characteristics www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 5/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M MPU Interface Characteristics (Ta=-40 to +85°C, VDD = 2.7V to 6.0V, VSS=0V) Parameter Symbol Data Setup Time Data Hold Time SCE Wait Time SCE Setup Time SCE Hold Time Clock Cycle Time High-level Clock Pulse Width Low-level Clock Pulse Width (Write) Low-level Clock Pulse Width (Read) Rise Time Fall Time SDO Output Delay Time Pin tds tdh tcp tcs tch tccyc tchw SCL, SDI SCL, SDI SCE, SCL SCE, SCL SCE, SCL SCL SCL tclww SCL tclwr SCL tr tf SDO Rise Time Conditions RPU=4.7KΩ (Note5) CL=10pf SCE, SCL, SDI SCE, SCL, SDI tdc SDO Tdr SDO RPU=4.7KΩ (Note5) CL=10pf RPU=4.7KΩ (Note5) CL=10pf Min 120 120 120 120 120 320 Limit Typ - Max - 120 - - ns 120 - - ns 1.6 - - us - 160 160 - ns ns - - 1.5 µs - - 1.5 µs Unit ns ns ns ns ns ns (Note5) Since SDO is an open-drain output, ”tdc” and “tdr” depend on the resistance of the pull-up resistor RPU and the load capacitance SCL. RPU: 1kΩ≤RPU≤10kΩ is recommended. CL: A parasitic capacitance to VSS in an application circuit. Any component is not necessary to be attached. Power supply for I/O level RPU SDO 1. Host CL When SCL is stopped at the low level VIH1, VIH2 SCE VIL1 tccyc tchw VIH1, VIH2 SCL tclww tclwr VIL1 tr tf tcs tch VIH1, VIH2 VIL1 SDI tds tdh SDO VOL5 tdc 2. tdr When SCL is stopped at the high level VIH1, VIH2 SCE VIL1 tccyc tchw tclww SCL tclwr VIH1,VIH2 VIL1 tf SDI tcp tr tch VIH1,VIH2 VIL1 tds tdh SDO VOL5 tdc tdr Figure 5.Serial Interface Timing www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 6/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M Pin Description Symbol Pin No. S1/P1/G1 to S9/P9/G9 79,80, 1 to 7 S10 to S52, S72 8 to 50, 74 KS1/S53 to KS6/S58 51 to 56 KI1/S59 to KI5/S63 57 to 61 SYNCIO/S64 62 CLKIO/S65 63 S66/TESTIN 64 COM5/S67 65 COM1 to COM4 69 to 66 MS 72 OSC_IN/S73 75 SCE SCL SDI SDO 76 77 78 73 VDD 70 VSS 71 Function Segment output for displaying the display data transferred by serial data input. The S1/P1/G1 to S6/P6/G6 pins can also be used as General –purpose outputs when so set up by the control data. Segment output for displaying the display data transferred by serial data input. Key scan outputs Although normal key scan timing lines require diodes to be inserted in the timing lines to prevent shorts, since these outputs are unbalanced CMOS transistor outputs, these outputs will not be damaged by shorting when these outputs are used to form a key matrix. The KS1/S53 to KS6/S58 pins can be used as segment outputs when so specified by the control data. Key scan inputs These pins have built-in pull-down resistors. The KI1/S59 to KI5/S63 pins can be used as segment outputs when so specified by the control data. Segment Output for Master without Slave application. SYNC output signal for Master with Slave application and SYNC input signal for Slave application. Segment Output for Master without Slave application. CLK output signal for Master with Slave application and CLK input signal for Slave application. TESTIN Input for Master Application. Segment Output for Slave Application. COMMON / SEGMENT output for LCD driving Assigned as COMMON output in1/5 Duty mode and SEGMENT output in 1/1 Duty, 1/3 Duty and 1/4 Duty modes Common driver output pins. The frame frequency is fo[Hz]. Master / Slave Control Switch L : Master, H : Slave Segment output for displaying the display data transferred by serial data input. The pin OSC_IN/S73 can be used as external frequency input pin when set up by the control data. Serial data transfer inputs. Must be connected to the controller. SCE: Chip enable SCL: Synchronization clock SDI: Transfer data Output data Power supply pin of the IC A power voltage of 2.7V to 6.0V must be applied to this pin. Power supply pin. Must be connected to ground. www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 7/66 Active I/O Handling when unused - O OPEN - O OPEN - O OPEN - I/O OPEN H ↑ - O O I O O I I O OPEN OPEN VDD OPEN - O OPEN - O - - I - - I/O OPEN H ↑ - I I I O OPEN - - - - - - TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M IO Equivalence Circuit Figure 6. I/O Equivalent Circuit www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 8/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M Serial Data Transfer Formats 1. 1/5 Duty (1) When SCL is stopped at the low level (a) Master SCE SCL SDI 1 1 1 0 0 0 1 0 D1 D2 D3 D4 Device Address 8 bits --- D94 D95 D96 0 0 0 0 0 0 0 0 0 0 --- 0 DR SS DT0 DT1 KM0 Display Data 96 bits KM1 KM2 P0 P1 P2 P3 FL FC0 FC1 FC2 FC3 OC SC BU0 BU1 BU2 0 0 0 DD 2 bits Control Data 54 bits SCE SCL SDI 1 1 1 0 0 0 1 0 D97 D98 D99 D100 --- D190 D191 D192 0 0 0 0 0 0 0 0 0 0 --- 0 0 SSC 0 PG1 PG2 Display Data 96 bits Device Address 8 bits PG3 PG4 PG5 PG6 PG7 PG8 PG9 PF0 PF1 PF2 PF3 PF4 CT0 CT1 CT2 CT3 0 0 1 DD 2 bits Control Data 54 bits SCE SCL SDI 1 1 1 0 0 0 1 0 D193 D194 D195 D196 --- D286 D287 D288 0 0 0 0 0 0 0 0 0 0 --- 0 0 WN10 WN11 --- WN17 WN18 WN20 WN21 Display Data 96 bits Device Address 8 bits --- WN27 WN28 WN30 WN31 --- WN37 WN38 WN40 WN41 --- WN47 WN48 0 1 0 DD 2 bits Control Data 54 bits SCE SCL SDI 1 1 1 0 0 0 1 0 D289 D230 --- D334 D335 0 --- 0 0 0 0 0 0 0 0 0 WN50 WN51 --- WN57 WN58 WN60 WN61 Display Data 47 bits Device Address 8 bits --- WN67 WN68 WN70 WN71 --- WN77 WN78 WN80 WN81 --- WN87 WN88 WN90 WN91 --- WN97 WN98 0 1 1 DD 2 bits Control Data 103 bits (Note6) (b) Slave SCE SCL SDI 0 0 0 1 0 0 1 0 D1 D2 D3 D4 Device Address 8 bits --- D94 D95 D96 0 0 0 0 0 0 0 0 0 0 --- 0 DR SS DT0 DT1 KM0 Display Data 96 bits KM1 KM2 P0 P1 P2 P3 FL FC0 FC1 FC2 FC3 OC SC BU0 BU1 BU2 0 0 0 DD 2 bits Control Data 54 bits SCE SCL SDI 0 0 0 1 0 0 1 0 D97 D98 D99 D100 --- D190 D191 D192 0 0 0 0 0 0 0 0 0 0 --- 0 0 SSC 0 PG1 PG2 Display Data 96 bits Device Address 8 bits PG3 PG4 PG5 PG6 PG7 PG8 PG9 PF0 PF1 PF2 PF3 PF4 CT0 CT1 CT2 CT3 0 0 1 DD 2 bits Control Data 54 bits SCE SCL SDI 0 0 0 1 0 0 1 0 D193 D194 D195 D196 --- D286 D287 D288 0 0 0 0 0 0 0 0 0 0 --- 0 0 WN10 WN11 --- WN17 WN18 WN20 WN21 Display Data 96 bits Device Address 8 bits --- WN27 WN28 WN30 WN31 --- WN37 WN38 WN40 WN41 --- WN47 WN48 0 1 0 DD 2 bits Control Data 54 bits SCE SCL SDI 0 0 0 1 0 0 1 0 D289 D230 Device Address 8 bits --- D354 D355 0 --- 0 0 0 0 0 0 0 0 0 WN50 WN51 --- Display Data 67 bits WN57 WN58 WN60 WN61 --- WN67 WN68 WN70 WN71 Control Data 83 bits --- WN77 WN78 WN80 WN81 --- WN87 WN88 WN90 WN91 --- WN97 WN98 0 1 1 DD 2 bits (Note6) Figure 7. 3-SPI Data Transfer Format (Note6) DD is direction data. www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 9/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M (2) When SCL is stopped at the high level (a) Master SCE SCL SDI 1 1 1 0 0 0 1 0 D1 D2 D3 D4 Device Address 8 bits --- D94 D95 D96 0 0 0 0 0 0 0 0 0 0 --- 0 DR SS DT0 DT1 KM0 Display Data 96 bits KM1 KM2 P0 P1 P2 P3 FL FC0 FC1 FC2 FC3 OC SC BU0 BU1 BU2 0 0 0 DD 2 bits Control Data 54 bits SCE SCL SDI 1 1 1 0 0 0 1 0 D97 D98 D99 D100 --- D190 D191 D192 0 0 0 0 0 0 0 0 0 0 --- 0 0 SSC 0 PG1 PG2 Display Data 96 bits Device Address 8 bits PG3 PG4 PG5 PG6 PG7 PG8 PG9 PF0 PF1 PF2 PF3 PF4 CT0 CT1 CT2 CT3 0 0 1 DD 2 bits Control Data 54 bits SCE SCL SDI 1 1 1 0 0 0 1 0 D193 D194 D195 D196 --- D286 D287 D288 0 0 0 0 0 0 0 0 0 0 --- 0 0 WN10 WN11 --- WN17 WN18 WN20 WN21 Display Data 96 bits Device Address 8 bits --- WN27 WN28 WN30 WN31 --- WN37 WN38 WN40 WN41 --- WN47 WN48 0 1 0 DD 2 bits Control Data 54 bits SCE SCL SDI 1 1 1 0 0 0 1 0 D289 D230 --- D334 D335 0 --- 0 0 0 0 0 0 0 0 0 WN50 WN51 --- WN57 WN58 WN60 WN61 Display Data 47 bits Device Address 8 bits --- WN67 WN68 WN70 WN71 --- WN77 WN78 WN80 WN81 --- WN87 WN88 WN90 WN91 --- WN97 WN98 0 1 1 DD 2 bits Control Data 103 bits (Note7) (b) Slave SCE SCL SDI 0 0 0 1 0 0 1 0 D1 D2 D3 D4 Device Address 8 bits --- D94 D95 D96 0 0 0 0 0 0 0 0 0 0 --- 0 DR SS DT0 DT1 KM0 Display Data 96 bits KM1 KM2 P0 P1 P2 P3 FL FC0 FC1 FC2 FC3 OC SC BU0 BU1 BU2 0 0 0 DD 2 bits Control Data 54 bits SCE SCL SDI 0 0 0 1 0 0 1 0 D97 D98 D99 D100 --- D190 D191 D192 0 0 0 0 0 0 0 0 0 0 --- 0 0 SSC 0 PG1 PG2 Display Data 96 bits Device Address 8 bits PG3 PG4 PG5 PG6 PG7 PG8 PG9 PF0 PF1 PF2 PF3 PF4 CT0 CT1 CT2 CT3 0 0 1 DD 2 bits Control Data 54 bits SCE SCL SDI 0 0 0 1 0 0 1 0 D193 D194 D195 D196 --- D286 D287 D288 0 0 0 0 0 0 0 0 0 0 --- 0 0 WN10 WN11 --- WN17 WN18 WN20 WN21 Display Data 96 bits Device Address 8 bits --- WN27 WN28 WN30 WN31 --- WN37 WN38 WN40 WN41 --- WN47 WN48 0 1 0 DD 2 bits Control Data 54 bits SCE SCL SDI 0 0 0 1 0 0 1 0 D289 D230 Device Address 8 bits --- D354 D355 0 --- 0 0 0 0 0 0 0 0 0 WN50 WN51 --- Display Data 67 bits WN57 WN58 WN60 WN61 --- WN67 WN68 WN70 WN71 Control Data 83 bits --- WN77 WN78 WN80 WN81 --- WN87 WN88 WN90 WN91 --- WN97 WN98 0 1 1 DD 2 bits (Note7) Figure 8. 3-SPI Data Transfer Format (Note7) DD is direction data. ・Device code････････････････････”47H” for Master , “48H” for Slave ・KM0 to KM2･････････････････････Key Scan output port/Segment output port switching control data ・D1 to D335･･････････････････････Display data for Master ・D1 to D355･･････････････････････Display data for Slave ・SS･････････････････････････････Master Clock and Sync output port/Segment output port switching control data ・SSC･･･････････････････････････SEG/COM output port switching control data ・P0 to P3････････････････････････Segment output port/general-purpose output port switching control data ・FL･････････････････････････････Line Inversion or Frame Inversion switching control data ・DR････････････････････････････1/3 bias driver or 1/2 bias driver switching control data ・DT0 to DT1･････････････････････1/5-duty drive, 1/4-duty drive, 1/3-duty drive or 1/1-duty(static) drive switching control data ・FC0 to FC3･････････････････････Common/segment output waveform frame frequency setting control data ・OC･･･････････････････････････ Internal oscillator operating mode/External clock operating mode switching control data ・SC････････････････････････････Segment on/off control data ・BU0 to BU2･････････････････････Normal mode/power-saving mode control data ・PG1 to PG9････････････････････ PWM/General Purpose output select data ・PF0 to PF4･････････････････････PWM output waveform frame frequency setting control data. ・CT0 to CT3･････････････････････LCD bias voltage VLCD setting control data. ・W10 to W18, W20 to W28, W30 to W38, W40 to W48, W50 to W58, W60 to W68, W70 to W78, W80 to W88, W90 to W98 ･･････････････････････････････････PWM output duty setting control data www.rohm.com © 2015 ROHM Co., Ltd. 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TSZ22111・15・001 10/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M 2. 1/4 Duty (1) When SCL is stopped at the low level (a) Master SCE SCL SDI 1 1 1 0 0 0 1 0 D1 D2 D3 D4 Device Address 8 bits --- D94 D95 D96 0 0 0 0 0 0 0 0 0 0 --- 0 DR SS DT0 DT1 KM0 Display Data 96 bits KM1 KM2 P0 P1 P2 P3 FL FC0 FC1 FC2 FC3 OC SC BU0 BU1 BU2 0 0 0 DD 2 bits Control Data 54 bits SCE SCL SDI 1 1 1 0 0 0 1 0 D97 D98 D99 D100 --- D190 D191 D192 0 0 0 0 0 0 0 0 0 0 --- 0 0 SSC 0 PG1 PG2 Display Data 96 bits Device Address 8 bits PG3 PG4 PG5 PG6 PG7 PG8 PG9 PF0 PF1 PF2 PF3 PF4 CT0 CT1 CT2 CT3 0 0 1 DD 2 bits Control Data 54 bits SCE SCL SDI 1 1 1 0 0 0 1 0 D193 D194 --- D271 D272 0 --- 0 0 0 0 0 0 0 0 0 0 0 --- 0 0 WN10 WN11 Display Data 80 bits Device Address 8 bits --- WN17 WN18 WN20 WN21 --- WN27 WN28 WN30 WN31 --- WN37 WN38 WN40 WN41 --- WN47 WN48 0 1 0 DD 2 bits Control Data 70 bits SCE SCL SDI 1 1 1 0 0 0 1 0 0 0 0 0 --- 0 0 0 0 0 0 0 0 0 0 0 WN50 WN51 --- WN57 WN58 WN60 WN61 Device Address 8 bits --- WN67 WN68 WN70 WN71 --- WN77 WN78 WN80 WN81 --- WN87 WN88 WN90 WN91 --- WN97 WN98 0 1 1 DD 2 bits Control Data 150 bits (Note8) (b) Slave SCE SCL SDI 0 0 0 1 0 0 1 0 D1 D2 D3 D4 Device Address 8 bits --- D94 D95 D96 0 0 0 0 0 0 0 0 0 0 --- 0 DR SS DT0 DT1 KM0 Display Data 96 bits KM1 KM2 P0 P1 P2 P3 FL FC0 FC1 FC2 FC3 OC SC BU0 BU1 BU2 0 0 0 DD 2 bits Control Data 54 bits SCE SCL SDI 0 0 0 1 0 0 1 0 D97 D98 D99 D100 --- D190 D191 D192 0 0 0 0 0 0 0 0 0 0 --- 0 0 SSC 0 PG1 PG2 Display Data 96 bits Device Address 8 bits PG3 PG4 PG5 PG6 PG7 PG8 PG9 PF0 PF1 PF2 PF3 PF4 CT0 CT1 CT2 CT3 0 0 1 DD 2 bits Control Data 54 bits SCE SCL SDI 0 0 0 1 0 0 1 0 D193 D194 --- D283 D284 0 --- 0 0 0 0 0 0 0 0 0 0 0 --- 0 0 WN10 WN11 Display Data 92 bits Device Address 8 bits --- WN17 WN18 WN20 WN21 --- WN27 WN28 WN30 WN31 --- WN37 WN38 WN40 WN41 --- WN47 WN48 0 1 0 DD 2 bits Control Data 58 bits SCE SCL SDI 0 0 0 1 0 0 1 0 0 0 0 0 --- 0 0 0 0 0 0 0 0 0 0 0 WN50 WN51 --- Device Address 8 bits WN57 WN58 WN60 WN61 --- WN67 WN68 WN70 WN71 Control Data 150 bits --- WN77 WN78 WN80 WN81 --- WN87 WN88 WN90 WN91 --- WN97 WN98 0 1 1 DD 2 bits (Note8) Figure 9. 3-SPI Data Transfer Format (Note8) DD is direction data. www.rohm.com © 2015 ROHM Co., Ltd. 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TSZ22111・15・001 11/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M (2) When SCL is stopped at the high level (a) Master SCE SCL SDI 1 1 1 0 0 0 1 0 D1 D2 D3 D4 Device Address 8 bits --- D94 D95 D96 0 0 0 0 0 0 0 0 0 0 --- 0 DR SS DT0 DT1 KM0 Display Data 96 bits KM1 KM2 P0 P1 P2 P3 FL FC0 FC1 FC2 FC3 OC SC BU0 BU1 BU2 0 0 0 DD 2 bits Control Data 54 bits SCE SCL SDI 1 1 1 0 0 0 1 0 D97 D98 D99 D100 --- D190 D191 D192 0 0 0 0 0 0 0 0 0 0 --- 0 0 SSC 0 PG1 PG2 Display Data 96 bits Device Address 8 bits PG3 PG4 PG5 PG6 PG7 PG8 PG9 PF0 PF1 PF2 PF3 PF4 CT0 CT1 CT2 CT3 0 0 1 DD 2 bits Control Data 54 bits SCE SCL SDI 1 1 1 0 0 0 1 0 D193 D194 --- D271 D272 0 --- 0 0 0 0 0 0 0 0 0 0 0 --- 0 0 WN10 WN11 Display Data 80 bits Device Address 8 bits --- WN17 WN18 WN20 WN21 --- WN27 WN28 WN30 WN31 --- WN37 WN38 WN40 WN41 --- WN47 WN48 0 1 0 DD 2 bits Control Data 70 bits SCE SCL SDI 1 1 1 0 0 0 1 0 0 0 0 0 --- 0 0 0 0 0 0 0 0 0 0 0 WN50 WN51 --- WN57 WN58 WN60 WN61 Device Address 8 bits --- WN67 WN68 WN70 WN71 --- WN77 WN78 WN80 WN81 --- WN87 WN88 WN90 WN91 --- WN97 WN98 0 1 1 DD 2 bits Control Data 150 bits (Note9) (b) Slave SCE SCL SDI 0 0 0 1 0 0 1 0 D1 D2 D3 D4 Device Address 8 bits --- D94 D95 D96 0 0 0 0 0 0 0 0 0 0 --- 0 DR SS DT0 DT1 KM0 Display Data 96 bits KM1 KM2 P0 P1 P2 P3 FL FC0 FC1 FC2 FC3 OC SC BU0 BU1 BU2 0 0 0 DD 2 bits Control Data 54 bits SCE SCL SDI 0 0 0 1 0 0 1 0 D97 D98 D99 D100 --- D190 D191 D192 0 0 0 0 0 0 0 0 0 0 --- 0 0 SSC 0 PG1 PG2 Display Data 96 bits Device Address 8 bits PG3 PG4 PG5 PG6 PG7 PG8 PG9 PF0 PF1 PF2 PF3 PF4 CT0 CT1 CT2 CT3 0 0 1 DD 2 bits Control Data 54 bits SCE SCL SDI 0 0 0 1 0 0 1 0 D193 D194 --- D283 D284 0 --- 0 0 0 0 0 0 0 0 0 0 0 --- 0 0 WN10 WN11 Display Data 92 bits Device Address 8 bits --- WN17 WN18 WN20 WN21 --- WN27 WN28 WN30 WN31 --- WN37 WN38 WN40 WN41 --- WN47 WN48 0 1 0 DD 2 bits Control Data 58 bits SCE SCL SDI 0 0 0 1 0 0 1 0 0 0 0 0 --- 0 0 0 0 0 0 0 0 0 0 0 WN50 WN51 --- Device Address 8 bits WN57 WN58 WN60 WN61 --- WN67 WN68 WN70 WN71 Control Data 150 bits --- WN77 WN78 WN80 WN81 --- WN87 WN88 WN90 WN91 --- WN97 WN98 0 1 1 DD 2 bits (Note9) Figure 10. 3-SPI Data Transfer Format (Note9) DD is direction data. ・Device code････････････････････”47H” for Master , “48H” for Slave ・KM0 to KM2･････････････････････Key Scan output port/Segment output port switching control data ・D1 to D272･････････････････････Display data for Master ・D1 to D284･････････････････････Display data for Slave ・SS･････････････････････････････Master Clock and Sync output port/Segment output port switching control data ・SSC･･･････････････････････････SEG/COM output port switching control data ・P0 to P3････････････････････････Segment output port/general-purpose output port switching control data ・FL･････････････････････････････Line Inversion or Frame Inversion switching control data ・DR････････････････････････････1/3 bias driver or 1/2 bias driver switching control data ・DT0 to DT1･････････････････････1/5-duty drive, 1/4-duty drive, 1/3-duty drive or 1/1-duty(static) drive switching control data ・FC0 to FC3･････････････････････Common/segment output waveform frame frequency setting control data ・OC･･･････････････････････････ Internal oscillator operating mode/External clock operating mode switching control data ・SC････････････････････････････Segment on/off control data ・BU0 to BU2･････････････････････Normal mode/power-saving mode control data ・PG1 to PG9････････････････････ PWM/General Purpose output select data ・PF0 to PF4･････････････････････PWM output waveform frame frequency setting control data. ・CT0 to CT3･････････････････････LCD bias voltage VLCD setting control data. ・W10 to W18, W20 to W28, W30 to W38, W40 to W48, W50 to W58, W60 to W68, W70 to W78, W80 to W88, W90 to W98 ･･････････････････････････････････PWM output duty setting control data www.rohm.com © 2015 ROHM Co., Ltd. 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TSZ22111・15・001 12/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M 3. 1/3 Duty (1) When SCL is stopped at the low level (a) Master SCE SCL SDI 1 1 1 0 0 0 1 0 D1 D2 D3 D4 Device Address 8 bits --- D94 D95 D96 0 0 0 0 0 0 0 0 0 0 --- 0 DR SS DT0 DT1 KM0 Display Data 96 bits KM1 KM2 P0 P1 P2 P3 FL FC0 FC1 FC2 FC3 OC SC BU0 BU1 BU2 0 0 0 DD 2 bits Control Data 54 bits SCE SCL SDI 1 1 1 0 0 0 1 0 D97 D98 D99 D100 --- D190 D191 D192 0 0 0 0 0 0 0 0 0 0 --- 0 RF SSC 0 PG1 PG2 Display Data 96 bits Device Address 8 bits PG3 PG4 PG5 PG6 PG7 PG8 PG9 PF0 PF1 PF2 PF3 PF4 CT0 CT1 CT2 CT3 0 0 1 DD 2 bits Control Data 54 bits SCE SCL SDI 1 1 1 0 0 0 1 0 D193 D194 --- D203 D204 0 --- 0 0 0 0 0 0 0 0 0 0 0 --- 0 0 WN10 WN11 Display Data 12 bits Device Address 8 bits --- WN17 WN18 WN20 WN21 --- WN27 WN28 WN30 WN31 --- WN37 WN38 WN40 WN41 --- WN47 WN48 0 1 0 DD 2 bits Control Data 138 bits SCE SCL SDI 1 1 1 0 0 0 1 0 0 0 0 0 --- 0 0 0 0 0 0 0 0 0 0 0 WN50 WN51 --- WN57 WN58 WN60 WN61 Device Address 8 bits --- WN67 WN68 WN70 WN71 --- WN77 WN78 WN80 WN81 --- WN87 WN88 WN90 WN91 --- WN97 WN98 0 1 1 DD 2 bits Control Data 150 bits (Note10) (b) Slave SCE SCL SDI 0 0 0 1 0 0 1 0 D1 D2 D3 D4 Device Address 8 bits --- D94 D95 D96 0 0 0 0 0 0 0 0 0 0 --- 0 DR SS DT0 DT1 KM0 Display Data 96 bits KM1 KM2 P0 P1 P2 P3 FL FC0 FC1 FC2 FC3 OC SC BU0 BU1 BU2 0 0 0 DD 2 bits Control Data 54 bits SCE SCL SDI 0 0 0 1 0 0 1 0 D97 D98 D99 D100 --- D190 D191 D192 0 0 0 0 0 0 0 0 0 0 --- 0 0 SSC 0 PG1 PG2 Display Data 96 bits Device Address 8 bits PG3 PG4 PG5 PG6 PG7 PG8 PG9 PF0 PF1 PF2 PF3 PF4 CT0 CT1 CT2 CT3 0 0 1 DD 2 bits Control Data 54 bits SCE SCL SDI 0 0 0 1 0 0 1 0 D193 D194 --- D212 D213 0 --- 0 0 0 0 0 0 0 0 0 0 0 --- 0 0 WN10 WN11 Display Data 21 bits Device Address 8 bits --- WN17 WN18 WN20 WN21 --- WN27 WN28 WN30 WN31 --- WN37 WN38 WN40 WN41 --- WN47 WN48 0 1 0 DD 2 bits Control Data 129 bits SCE SCL SDI 0 0 0 1 0 0 1 0 0 0 0 0 --- 0 0 0 0 0 0 0 0 0 0 0 WN50 WN51 --- Device Address 8 bits WN57 WN58 WN60 WN61 --- WN67 WN68 WN70 WN71 Control Data 150 bits --- WN77 WN78 WN80 WN81 --- WN87 WN88 WN90 WN91 --- WN97 WN98 0 1 1 DD 2 bits (Note10) Figure 11. 3-SPI Data Transfer Format (Note10) DD is direction data. www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 13/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M (2) When SCL is stopped at the high level (a) Master SCE SCL SDI 1 1 1 0 0 0 1 0 D1 D2 D3 D4 Device Address 8 bits --- D94 D95 D96 0 0 0 0 0 0 0 0 0 0 --- 0 DR SS DT0 DT1 KM0 Display Data 96 bits KM1 KM2 P0 P1 P2 P3 FL FC0 FC1 FC2 FC3 OC SC BU0 BU1 BU2 0 0 0 DD 2 bits Control Data 54 bits SCE SCL SDI 1 1 1 0 0 0 1 0 D97 D98 D99 D100 --- D190 D191 D192 0 0 0 0 0 0 0 0 0 0 --- 0 0 SSC 0 PG1 PG2 Display Data 96 bits Device Address 8 bits PG3 PG4 PG5 PG6 PG7 PG8 PG9 PF0 PF1 PF2 PF3 PF4 CT0 CT1 CT2 CT3 0 0 1 DD 2 bits Control Data 54 bits SCE SCL SDI 1 1 1 0 0 0 1 0 D193 D194 --- D203 D204 0 --- 0 0 0 0 0 0 0 0 0 0 0 --- 0 0 WN10 WN11 Display Data 12 bits Device Address 8 bits --- WN17 WN18 WN20 WN21 --- WN27 WN28 WN30 WN31 --- WN37 WN38 WN40 WN41 --- WN47 WN48 0 1 0 DD 2 bits Control Data 138 bits SCE SCL SDI 1 1 1 0 0 0 1 0 0 0 0 0 --- 0 0 0 0 0 0 0 0 0 0 0 WN50 WN51 --- WN57 WN58 WN60 WN61 Device Address 8 bits --- WN67 WN68 WN70 WN71 --- WN77 WN78 WN80 WN81 --- WN87 WN88 WN90 WN91 --- WN97 WN98 0 1 1 DD 2 bits Control Data 150 bits (Note11) (b) Slave SCE SCL SDI 0 0 0 1 0 0 1 0 D1 D2 D3 D4 Device Address 8 bits --- D94 D95 D96 0 0 0 0 0 0 0 0 0 0 --- 0 DR SS DT0 DT1 KM0 Display Data 96 bits KM1 KM2 P0 P1 P2 P3 FL FC0 FC1 FC2 FC3 OC SC BU0 BU1 BU2 0 0 0 DD 2 bits Control Data 54 bits SCE SCL SDI 0 0 0 1 0 0 1 0 D97 D98 D99 D100 --- D190 D191 D192 0 0 0 0 0 0 0 0 0 0 --- 0 0 SSC 0 PG1 PG2 Display Data 96 bits Device Address 8 bits PG3 PG4 PG5 PG6 PG7 PG8 PG9 PF0 PF1 PF2 PF3 PF4 CT0 CT1 CT2 CT3 0 0 1 DD 2 bits Control Data 54 bits SCE SCL SDI 0 0 0 1 0 0 1 0 D193 D194 --- D212 D213 0 --- 0 0 0 0 0 0 0 0 0 0 0 --- 0 0 WN10 WN11 Display Data 21 bits Device Address 8 bits --- WN17 WN18 WN20 WN21 --- WN27 WN28 WN30 WN31 --- WN37 WN38 WN40 WN41 --- WN47 WN48 0 1 0 DD 2 bits Control Data 129 bits SCE SCL SDI 0 0 0 1 0 0 1 0 0 0 0 0 --- 0 0 0 0 0 0 0 0 0 0 0 WN50 WN51 --- Device Address 8 bits WN57 WN58 WN60 WN61 --- WN67 WN68 WN70 WN71 Control Data 150 bits --- WN77 WN78 WN80 WN81 --- WN87 WN88 WN90 WN91 --- WN97 WN98 0 1 1 DD 2 bits (Note11) Figure 12. 3-SPI Data Transfer Format (Note11) DD is direction data. ・Device code････････････････････”47H” for Master , “48H” for Slave ・KM0 to KM2･････････････････････Key Scan output port/Segment output port switching control data ・D1 to D204･･････････････････････Display data for Master ・D1 to D213･･････････････････････Display data for Slave ・SS･････････････････････････････Master Clock and Sync output port/Segment output port switching control data ・SSC･･･････････････････････････SEG/COM output port switching control data ・P0 to P3････････････････････････Segment output port/general-purpose output port switching control data ・FL･････････････････････････････Line Inversion or Frame Inversion switching control data ・DR････････････････････････････1/3 bias driver or 1/2 bias driver switching control data ・DT0 to DT1･････････････････････1/5-duty drive, 1/4-duty drive, 1/3-duty drive or 1/1-duty(static) drive switching control data ・FC0 to FC3･････････････････････Common/segment output waveform frame frequency setting control data ・OC････････････････････････････Internal oscillator operating mode/External clock operating mode switching control data ・SC････････････････････････････Segment on/off control data ・BU0 to BU2･････････････････････Normal mode/power-saving mode control data ・PG1 to PG9････････････････････ PWM/General Purpose output select data ・PF0 to PF4･････････････････････PWM output waveform frame frequency setting control data. ・CT0 to CT3･････････････････････LCD bias voltage VLCD setting control data. ・W10 to W18, W20 to W28, W30 to W38, W40 to W48, W50 to W58, W60 to W68, W70 to W78, W80 to W88, W90 to W98 ･･････････････････････････････････PWM output duty setting control data www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 14/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M 4. 1/1 Duty (Static) (1) When SCL is stopped at the low level (a) Master SCE SCL SDI 1 1 1 0 0 0 1 0 D1 D2 D3 Device Address 8 bits D4 --- D66 D67 D68 0 0 0 0 0 0 0 0 0 0 --- 0 DR SS DT0 DT1 Display Data 68 bits KM0 KM1 KM2 P0 P1 P2 P3 FL FC0 FC1 FC2 FC3 OC SC BU0 BU1 BU2 0 0 0 DD 2 bits Control Data 82 bits SCE SCL SDI 1 1 1 0 0 0 1 0 0 0 0 0 --- 0 0 0 0 0 0 0 0 0 0 0 0 0 --- 0 Device Address 8 bits 0 SSC 0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PG8 PG9 PF0 PF1 PF2 PF3 PF4 CT0 CT1 CT2 CT3 0 0 1 DD 2 bits Control Data 150 bits SCE SCL SDI 1 1 1 0 0 0 1 0 0 0 0 0 --- 0 0 0 0 0 0 0 0 0 0 0 0 0 --- 0 Device Address 8 bits 0 WN10 WN11 --- WN17 WN18 WN20 WN21 --- WN27 WN28 WN30 WN31 --- WN37 WN38 WN40 WN41 --- WN47 WN48 0 1 0 DD 2 bits Control Data 150 bits SCE SCL SDI 1 1 1 0 0 0 1 0 0 0 0 0 --- 0 0 0 0 0 0 0 0 0 0 0 WN50 WN51 --- WN57 WN58 WN60 WN61 Device Address 8 bits --- WN67 WN68 WN70 WN71 --- WN77 WN78 WN80 WN81 --- WN87 WN88 WN90 WN91 --- WN97 WN98 0 1 1 DD 2 bits Control Data 150 bits (Note12) (b) Slave SCE SCL SDI 0 0 0 1 0 0 1 0 D1 D2 D3 Device Address 8 bits D4 --- D69 D70 D71 0 0 0 0 0 0 0 0 0 0 --- 0 DR SS DT0 DT1 Display Data 71 bits KM0 KM1 KM2 P0 P1 P2 P3 FL FC0 FC1 FC2 FC3 OC SC BU0 BU1 BU2 0 0 0 DD 2 bits Control Data 79 bits SCE SCL SDI 0 0 0 1 0 0 1 0 0 0 0 0 --- 0 0 0 0 0 0 0 0 0 0 0 0 0 --- 0 Device Address 8 bits 0 SSC 0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PG8 PG9 PF0 PF1 PF2 PF3 PF4 CT0 CT1 CT2 CT3 0 0 1 DD 2 bits Control Data 150 bits SCE SCL SDI 0 0 0 1 0 0 1 0 0 0 0 0 --- 0 0 0 0 0 0 0 0 0 0 0 0 0 --- Device Address 8 bits 0 0 WN10 WN11 --- WN17 WN18 WN20 WN21 --- WN27 WN28 WN30 WN31 --- WN37 WN38 WN40 WN41 --- WN47 WN48 0 1 0 DD 2 bits Control Data 150 bits SCE SCL SDI 0 0 0 1 0 0 1 0 0 0 0 0 --- 0 0 0 0 0 0 0 0 0 0 0 WN50 WN51 --- Device Address 8 bits WN57 WN58 WN60 WN61 --- WN67 WN68 WN70 WN71 Control Data 150 bits --- WN77 WN78 WN80 WN81 --- WN87 WN88 WN90 WN91 --- WN97 WN98 0 1 1 DD 2 bits (Note12) Figure 13. 3-SPI Data Transfer Format (Note12) DD is direction data. www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 15/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M (2) When SCL is stopped at the high level (a) Master SCE SCL SDI 1 1 1 0 0 0 1 0 D1 D2 D3 Device Address 8 bits D4 --- D66 D67 D68 0 0 0 0 0 0 0 0 0 0 --- 0 DR SS DT0 DT1 Display Data 68 bits KM0 KM1 KM2 P0 P1 P2 P3 FL FC0 FC1 FC2 FC3 OC SC BU0 BU1 BU2 0 0 0 DD 2 bits Control Data 82 bits SCE SCL SDI 1 1 1 0 0 0 1 0 0 0 0 0 --- 0 0 0 0 0 0 0 0 0 0 0 0 0 --- 0 Device Address 8 bits 0 SSC 0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PG8 PG9 PF0 PF1 PF2 PF3 PF4 CT0 CT1 CT2 CT3 0 0 1 DD 2 bits Control Data 150 bits SCE SCL SDI 1 1 1 0 0 0 1 0 0 0 0 0 --- 0 0 0 0 0 0 0 0 0 0 0 0 0 --- 0 Device Address 8 bits 0 WN10 WN11 --- WN17 WN18 WN20 WN21 --- WN27 WN28 WN30 WN31 --- WN37 WN38 WN40 WN41 --- WN47 WN48 0 1 0 DD 2 bits Control Data 150 bits SCE SCL SDI 1 1 1 0 0 0 1 0 0 0 0 0 --- 0 0 0 0 0 0 0 0 0 0 0 WN50 WN51 --- WN57 WN58 WN60 WN61 Device Address 8 bits --- WN67 WN68 WN70 WN71 --- WN77 WN78 WN80 WN81 --- WN87 WN88 WN90 WN91 --- WN97 WN98 0 1 1 DD 2 bits Control Data 150 bits (Note13) (b) Slave SCE SCL SDI 0 0 0 1 0 0 1 0 D1 D2 D3 Device Address 8 bits D4 --- D69 D70 D71 0 0 0 0 0 0 0 0 0 0 --- 0 DR SS DT0 DT1 Display Data 71 bits KM0 KM1 KM2 P0 P1 P2 P3 FL FC0 FC1 FC2 FC3 OC SC BU0 BU1 BU2 0 0 0 DD 2 bits Control Data 79 bits SCE SCL SDI 0 0 0 1 0 0 1 0 0 0 0 0 --- 0 0 0 0 0 0 0 0 0 0 0 0 0 --- 0 Device Address 8 bits 0 SSC 0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PG8 PG9 PF0 PF1 PF2 PF3 PF4 CT0 CT1 CT2 CT3 0 0 1 DD 2 bits Control Data 150 bits SCE SCL SDI 0 0 0 1 0 0 1 0 0 0 0 0 --- 0 0 0 0 0 0 0 0 0 0 0 0 0 --- Device Address 8 bits 0 0 WN10 WN11 --- WN17 WN18 WN20 WN21 --- WN27 WN28 WN30 WN31 --- WN37 WN38 WN40 WN41 --- WN47 WN48 0 1 0 DD 2 bits Control Data 150 bits SCE SCL SDI 0 0 0 1 0 0 1 0 0 0 0 0 --- 0 0 0 0 0 0 0 0 0 0 0 WN50 WN51 --- Device Address 8 bits WN57 WN58 WN60 WN61 --- WN67 WN68 WN70 WN71 Control Data 150 bits --- WN77 WN78 WN80 WN81 --- WN87 WN88 WN90 WN91 --- WN97 WN98 0 1 1 DD 2 bits (Note13) Figure 14. 3-SPI Data Transfer Format (Note13) DD is direction data. ・Device code････････････････････”47H” for Master , “48H” for Slave ・KM0 to KM2･････････････････････Key Scan output port/Segment output port switching control data ・D1 to D68･･･････････････････････Display data for Master ・D1 to D71･･･････････････････････Display data for Slave ・SS･････････････････････････････Master Clock and Sync output port/Segment output port switching control data ・SSC･･･････････････････････････SEG/COM output port switching control data ・P0 to P3････････････････････････Segment output port/general-purpose output port switching control data ・FL･････････････････････････････Line Inversion or Frame Inversion switching control data ・DR････････････････････････････1/3 bias driver or 1/2 bias driver switching control data ・DT0 to DT1･････････････････････1/5-duty drive, 1/4-duty drive, 1/3-duty drive or 1/1-duty(static) drive switching control data ・FC0 to FC3･････････････････････Common/segment output waveform frame frequency setting control data ・OC･･･････････････････････････ Internal oscillator operating mode/External clock operating mode switching control data ・SC････････････････････････････Segment on/off control data ・BU0 to BU2･････････････････････Normal mode/power-saving mode control data ・PG1 to PG9････････････････････ PWM/General Purpose output select data ・PF0 to PF4･････････････････････PWM output waveform frame frequency setting control data. ・CT0 to CT3･････････････････････LCD bias voltage VLCD setting control data. ・W10 to W18, W20 to W28, W30 to W38, W40 to W48, W50 to W58, W60 to W68, W70 to W78, W80 to W88, W90 to W98 ･･････････････････････････････････PWM output duty setting control data www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 16/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M Control Data Functions 1.KM0, KM1 and KM2 : Key Scan output port/Segment output port switching control data These control data bits switch the functions of the KS1/S53 to KS6/S58 output pins between key scan output and segment output. Output Pin State Maximum Number of Input keys KS1/S53 KS2/S54 KS3/S55 KS4/S56 KS5/S57 KS6/S58 0 0 0 KS1 KS2 KS3 KS4 KS5 KS6 30 0 0 1 S53 KS2 KS3 KS4 KS5 KS6 25 0 1 0 S53 S54 KS3 KS4 KS5 KS6 20 0 1 1 S53 S54 S55 KS4 KS5 KS6 15 1 0 0 S53 S54 S55 S56 KS5 KS6 10 1 0 1 S53 S54 S55 S56 S57 KS6 5 1 1 0 S53 S54 S55 S56 S57 S58 0 1 1 1 S53 S54 S55 S56 S57 S58 0 In Slave Mode, it is automatically set to all segment output and cannot be controlled by Serial Interface. KM0 KM1 KM2 2. P0, P1, P2, and P3: Segment / PWM / General Purpose output port switching control data These control bits are used to select the function of the S1/P1/G1 to S9/P9/G9 output pins (Segment Output Pins or PWM Output Pins or General Purpose Output Pins). P0 P1 P2 P3 S1/P1/G1 S2/P2/G2 S3/P3/G3 S4/P4/G4 S5/P5/G5 S6/P6/G6 0 0 0 0 S1 S2 S3 S4 S5 S6 0 0 0 1 P1/G1 S2 S3 S4 S5 S6 0 0 1 0 P1/G1 P2/G2 S3 S4 S5 S6 0 0 1 1 P1/G1 P2/G2 P3/G3 S4 S5 S6 0 1 0 0 P1/G1 P2/G2 P3/G3 P4/G4 S5 S6 0 1 0 1 P1/G1 P2/G2 P3/G3 P4/G4 P5/G5 S6 0 1 1 0 P1/G1 P2/G2 P3/G3 P4/G4 P5/G5 P6/G6 0 1 1 1 P1/G1 P2/G2 P3/G3 P4/G4 P5/G5 P6/G6 1 0 0 0 P1/G1 P2/G2 P3/G3 P4/G4 P5/G5 P6/G6 1 0 0 1 P1/G1 P2/G2 P3/G3 P4/G4 P5/G5 P6/G6 1 0 1 0 S1 S2 S3 S4 S5 S6 1 0 1 1 S1 S2 S3 S4 S5 S6 1 1 0 0 S1 S2 S3 S4 S5 S6 1 1 0 1 S1 S2 S3 S4 S5 S6 1 1 1 0 S1 S2 S3 S4 S5 S6 1 1 1 1 S1 S2 S3 S4 S5 S6 PWM output or General Purpose output is selected by PGx(x=1 to 9) control data bit. S7/P7/G7 S8/P8/G8 S9/P9/G9 S7 S7 S7 S7 S7 S7 S7 P7/G7 P7/G7 P7/G7 S7 S7 S7 S7 S7 S7 S8 S8 S8 S8 S8 S8 S8 S8 P8/G8 P8/G8 S8 S8 S8 S8 S8 S8 S9 S9 S9 S9 S9 S9 S9 S9 S9 P9/S9 S9 S9 S9 S9 S9 S9 When the General Purpose Output Port Function is selected, the correspondence between the output pins and the respective display data is given in the table below. Corresponding Display Data Output Pins 1/5 Duty mode 1/4 Duty mode 1/3 Duty mode 1/1 Duty (static) mode S1/P1/G1 D1 D1 D1 D1 S2/P2/G2 D6 D5 D4 D2 S3/P3/G3 D11 D9 D7 D3 S4/P4/G4 D16 D13 D10 D4 S5/P5/G5 D21 D17 D13 D4 S6/P6/G6 D26 D21 D16 D5 S7/P7/G7 D31 D25 D19 D7 S8/P8/G8 D36 D29 D22 D8 S9/P9/G9 D41 D33 D25 D9 When the General Purpose Output Port Function is selected, the respective output pin outputs a “HIGH” level when its corresponding display data is set to “1”. Likewise, it will output a “LOW” level, if its corresponding display data is set to “0”. For example, at 1/4 Duty mode, S4/P4/G4 is used as a General Purpose Output Port, if its corresponding display data D13 is set to “1”, then S4/P4/G4 will output “HIGH” level. Likewise, if D13 is set to “0”, then S4/P4/G4 will output “LOW” level. 3. FL: Line Inversion or Frame Inversion switching control data This control data bit selects either line inversion mode or frame inversion mode. FL Inversion mode 0 Line Inversion 1 Frame Inversion www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 17/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M 4. DR: 1/3 bias drive, 1/2 bias drive or 1/1 bias drive switching control data This control data bit selects either 1/3 bias drive or 1/2 bias drive. DR Bias drive scheme 0 1/3 Bias 1 1/2 Bias 5. SS: Master Clock and Sync output port/Segment output port switching control data This control data bit switches the functions of the CLKIO/S64 and SYNCIO/S65 output pins between master/slave output and segment output. Output Pin State SS CLKIO/S64 SYNCIO/S65 0 S64 S65 1 CLKIO SYNCIO In Slave Mode, it is automatically set to all segment output and cannot be controlled by Serial Interface. 6. DT: 1/5 duty drive, 1/4 duty drive, 1/3 duty drive or 1/1 duty switching control data These control data bits select either 1/5 duty drive, 1/4 duty drive, 1/3 duty drive or 1/1 duty (static) DT0 DT1 Duty drive scheme 0 0 1/1 duty (static) drive 0 0 1/3 duty drive 0 1 1/4 duty drive 1 1 1/5 duty drive 7. FC0, FC1, FC2 and FC3: Common/segment output waveform frame frequency setting control data These control data bits set the frame frequency for common and segment output waveforms. FC0 FC1 FC2 FC3 Frame Frequency fo(Hz) (Note14) 0 0 0 0 fosc / 12288 0 0 0 1 fosc / 10752 0 0 1 0 fosc / 9216 0 0 1 1 fosc / 7680 0 1 0 0 fosc / 6144 0 1 0 1 fosc / 4608 0 1 1 0 fosc / 3840 0 1 1 1 fosc / 3072 1 0 0 0 fosc / 2880 1 0 0 1 fosc / 2688 1 0 1 0 fosc / 2496 1 0 1 1 fosc / 2304 1 1 0 0 fosc / 2112 1 1 0 1 fosc / 1920 1 1 1 0 fosc / 1728 1 1 1 1 fosc / 1536 (Note14)fosc: Internal Oscillation Frequency (600 [kHz] Typ) 8. OC: Internal oscillator operating mode/External clock operating mode switching control data OC Operating mode In/Out pin(OSC_IN/S73) status 0 Internal oscillator S73 (segment output) 1 External Clock OSC_IN (clock input) 9. SC: Segment on/off control data This control data bit controls the on/off state of the segments. SC Display state 0 ON 1 OFF Note that when the segments are turned off by setting SC to “1”, the segments are turned off by outputting segment off waveforms from the segment output pins. www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 18/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M 10. BU0, BU1 and BU2 : Normal mode/power-saving mode control data These control data bits select either normal mode or power-saving mode. Segment outputs Output Pin States During Key Scan Standby BU0 BU1 BU2 Mode OSC Oscillator Common outputs KS1 KS2 KS3 KS4 KS5 KS6 0 0 0 Normal Operating Operating H H H H H H 0 0 1 L L L L L H 0 1 0 L L L L H H 0 1 1 L L L H H H Power1 0 0 Stopped Low(VSS) L L H H H H saving 1 0 1 L H H H H H 1 1 0 H H H H H H 1 1 1 H H H H H H Power-saving mode status: S1/P1/G1 to S9/P9/G9 = active only General Purpose output S10 to OSC_IN/S73 = low (VSS) COM1 to COM5 = low (VSS) Shut off current to the LCD drive bias voltage generation circuit Stop the Internal oscillation circuit However, serial data transfer is possible when at Power-saving mode. 11. SSC: SEG/COM output port switching control data This control data bit selects SEG or COM output for Slave. Output Pin State SSC COM5/S67 COM4/S68 COM3/S69 0 S67 S68 S69 1 COM5 COM4 COM3 This option is not available in Master mode. COM2/S70 S70 COM2 COM1/S71 S71 COM1 12. PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8 and PG9: PWM/General Purpose output control data This control data bit select either PWM output or General Purpose output of Sx/Px/Gx pins. (x=1 to 9) PGx(x=1 to 9) Mode 0 PWM Output 1 General Purpose Output Normal behavior of changing GPO to PWM is below. - PWM operation is started by command import timing of DD: 01 during GPO  PWM change. - Please take care of reflect timing of new duty setting of DD: 10 and DD: 11 are from the next PWM. SCE DD: 00 DD: 01 DD: 10 GPO ---> PWM change DD: 11 new duty decided timing PWM/GPO output start of PWM operation next PWM cycle (PWM waveform in immediate duty) (PWM waveform in new duty) In order to avoid this operation, please input commands in reverse as below. SCE DD:10 DD:11 new duty decided timing DD:01 DD:00 GPO --＞PWM change PWM/GPO output Start of PWM operation (PWM waveform on new duty) www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 19/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M 13. PF0, PF1, PF2, PF3 and PF4: PWM output waveform frame frequency setting control data These control data bits set the frame frequency for pwm output waveforms. PF0 PF1 PF2 PF3 PF4 PWM output Frame Frequency fp(Hz) 0 0 0 0 0 fosc / 4096 0 0 0 0 1 fosc / 3840 0 0 0 1 0 fosc / 3584 0 0 0 1 1 fosc / 3328 0 0 1 0 0 fosc / 3072 0 0 1 0 1 fosc / 2816 0 0 1 1 0 fosc / 2560 0 0 1 1 1 fosc / 2304 0 1 0 0 0 fosc / 2048 0 1 0 0 1 fosc / 1792 0 1 0 1 0 fosc / 1536 0 1 0 1 1 fosc / 1280 0 1 1 0 0 fosc / 1024 0 1 1 0 1 fosc / 768 0 1 1 1 0 fosc / 512 0 1 1 1 1 fosc / 256 1 0 0 0 0 fosc / 128 ・・・・・・・・・・・・・・・・・・ 1 1 1 1 1 fosc / 128 14. CT0, CT1, CT2 and CT3: Display Contrast setting control data These control data bits set display contrast CT0 CT1 CT2 CT3 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 20/66 LCD Drive bias voltage for VLCD Level 1.000*VDD 0.975*VDD 0.950*VDD 0.925*VDD 0.900*VDD 0.875*VDD 0.850*VDD 0.825*VDD 0.800*VDD 0.775*VDD 0.750*VDD 0.725*VDD 0.700*VDD 0.675*VDD 0.650*VDD 0.625*VDD TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M (Note15) 15. W10 to W18 , W20 to W28, W30 to W38, W40 to W48, W50 to W58, W60 to W68, W70 to W78, W80 to W88 and W90 to W98: PWM output waveform duty setting control data. These control data bits set the high level pulse width (duty) for pwm output waveforms. Table below shows PWM high level pulse width when PF0 to PF3 command setting is [PF0,PF1,PF2,PF3]=[0,x,x,x] n = 1 to 9 , Tp = 1/fp Wn0 Wn1 Wn2 Wn3 Wn4 Wn5 Wn6 Wn7 Wn8 PWM duty 0 0 0 0 0 0 0 0 0 (0/256) x Tp 0 0 0 0 0 0 0 0 1 (1/256) x Tp 0 0 0 0 0 0 0 1 0 (2/256) x Tp 0 0 0 0 0 0 0 1 1 (3/256) x Tp 0 0 0 0 0 0 1 0 0 (4/256) x Tp 0 0 0 0 0 0 1 0 1 (5/256) x Tp 0 0 0 0 0 0 1 1 0 (6/256) x Tp 0 0 0 0 0 0 1 1 1 (7/256) x Tp 0 0 0 0 0 1 0 0 0 (8/256) x Tp 0 0 0 0 0 1 0 0 1 (9/256) x Tp 0 0 0 0 0 1 0 1 0 (10/256) x Tp 0 0 0 0 0 1 0 1 1 (11/256) x Tp 0 0 0 0 0 1 1 0 0 (12/256) x Tp 0 0 0 0 0 1 1 0 1 (13/256) x Tp 0 0 0 0 0 1 1 1 0 (14/256) x Tp 0 0 0 0 0 1 1 1 1 (15/256) x Tp 0 0 0 0 1 0 0 0 0 (16/256) x Tp 0 0 0 0 1 0 0 0 1 (17/256) x Tp 0 0 0 0 1 0 0 1 0 (18/256) x Tp 0 0 0 0 1 0 0 1 1 (19/256) x Tp 0 0 0 0 1 0 1 0 0 (20/256) x Tp ・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・ 0 1 1 1 0 1 0 1 1 (235/256) x Tp 0 1 1 1 0 1 1 0 0 (236/256) x Tp 0 1 1 1 0 1 1 0 1 (237/256) x Tp 0 1 1 1 0 1 1 1 0 (238/256) x Tp 0 1 1 1 0 1 1 1 1 (239/256) x Tp 0 1 1 1 1 0 0 0 0 (240/256) x Tp 0 1 1 1 1 0 0 0 1 (241/256) x Tp 0 1 1 1 1 0 0 1 0 (242/256) x Tp 0 1 1 1 1 0 0 1 1 (243/256) x Tp 0 1 1 1 1 0 1 0 0 (244/256) x Tp 0 1 1 1 1 0 1 0 1 (245/256) x Tp 0 1 1 1 1 0 1 1 0 (246/256) x Tp 0 1 1 1 1 0 1 1 1 (247/256) x Tp 0 1 1 1 1 1 0 0 0 (248/256) x Tp 0 1 1 1 1 1 0 0 1 (249/256) x Tp 0 1 1 1 1 1 0 1 0 (250/256) x Tp 0 1 1 1 1 1 0 1 1 (251/256) x Tp 0 1 1 1 1 1 1 0 0 (252/256) x Tp 0 1 1 1 1 1 1 0 1 (253/256) x Tp 0 1 1 1 1 1 1 1 0 (254/256) x Tp 0 1 1 1 1 1 1 1 1 (255/256) x Tp 1 0 0 0 0 0 0 0 0 (256/256) x Tp 1 0 0 0 0 0 0 0 1 (256/256) x Tp 1 0 0 0 0 0 0 1 0 (256/256) x Tp 1 0 0 0 0 0 0 1 1 (256/256) x Tp ・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・ 1 1 1 1 1 1 1 0 0 (256/256) x Tp 1 1 1 1 1 1 1 0 1 (256/256) x Tp 1 1 1 1 1 1 1 1 0 (256/256) x Tp 1 1 1 1 1 1 1 1 1 (256/256) x Tp (Note15) W10 to W18:S1/P1/G1 pwm duty data W20 to W28:S2/P2/G2 pwm duty data W30 to W38:S3/P3/G3 pwm duty data W40 to W48:S4/P4/G4 pwm duty data W50 to W58:S5/P5/G5 pwm duty data W60 to W68:S6/P6/G6 pwm duty data W70 to W78:S7/P7/G7 pwm duty data W80 to W88:S8/P8/G8 pwm duty data W90 to W98:S9/P9/G9 pwm duty data www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 21/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M Table below shows PWM high level pulse width when PF0 to PF3 command setting is [PF0,PF1,PF2,PF3]=[1,x,x,x] n = 1 to 9 , Tp = 1/fp Wn0 Wn1 Wn2 Wn3 Wn4 Wn5 Wn6 Wn7 Wn8 PWM duty 0 0 0 0 0 0 0 0 0 (0/128) x Tp 0 0 0 0 0 0 0 0 1 (1/128) x Tp 0 0 0 0 0 0 0 1 0 (2/128) x Tp 0 0 0 0 0 0 0 1 1 (3/128) x Tp 0 0 0 0 0 0 1 0 0 (4/128) x Tp 0 0 0 0 0 0 1 0 1 (5/128) x Tp 0 0 0 0 0 0 1 1 0 (6/128) x Tp 0 0 0 0 0 0 1 1 1 (7/128) x Tp 0 0 0 0 0 1 0 0 0 (8/128) x Tp 0 0 0 0 0 1 0 0 1 (9/128) x Tp 0 0 0 0 0 1 0 1 0 (10/128) x Tp 0 0 0 0 0 1 0 1 1 (11/128) x Tp 0 0 0 0 0 1 1 0 0 (12/128) x Tp 0 0 0 0 0 1 1 0 1 (13/128) x Tp 0 0 0 0 0 1 1 1 0 (14/128) x Tp 0 0 0 0 0 1 1 1 1 (15/128) x Tp 0 0 0 0 1 0 0 0 0 (16/128) x Tp 0 0 0 0 1 0 0 0 1 (17/128) x Tp 0 0 0 0 1 0 0 1 0 (18/128) x Tp 0 0 0 0 1 0 0 1 1 (19/128) x Tp 0 0 0 0 1 0 1 0 0 (20/128) x Tp ・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・ 0 0 1 1 0 1 0 1 1 (107/128) x Tp 0 0 1 1 0 1 1 0 0 (108/128) x Tp 0 0 1 1 0 1 1 0 1 (109/128) x Tp 0 0 1 1 0 1 1 1 0 (110/128) x Tp 0 0 1 1 0 1 1 1 1 (111/128) x Tp 0 0 1 1 1 0 0 0 0 (112/128) x Tp 0 0 1 1 1 0 0 0 1 (113/128) x Tp 0 0 1 1 1 0 0 1 0 (114/128) x Tp 0 0 1 1 1 0 0 1 1 (115/128) x Tp 0 0 1 1 1 0 1 0 0 (116/128) x Tp 0 0 1 1 1 0 1 0 1 (117/128) x Tp 0 0 1 1 1 0 1 1 0 (118/128) x Tp 0 0 1 1 1 0 1 1 1 (119/128) x Tp 0 0 1 1 1 1 0 0 0 (120/128) x Tp 0 0 1 1 1 1 0 0 1 (121/128) x Tp 0 0 1 1 1 1 0 1 0 (122/128) x Tp 0 0 1 1 1 1 0 1 1 (123/128) x Tp 0 0 1 1 1 1 1 0 0 (124/128) x Tp 0 0 1 1 1 1 1 0 1 (125/128) x Tp 0 0 1 1 1 1 1 1 0 (126/128) x Tp 0 0 1 1 1 1 1 1 1 (127/128) x Tp 0 1 0 0 0 0 0 0 0 (128/128) x Tp 0 1 0 0 0 0 0 0 1 (128/128) x Tp 0 1 0 0 0 0 0 1 0 (128/128) x Tp 0 1 0 0 0 0 0 1 1 (128/128) x Tp ・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・ 1 1 1 1 1 1 1 0 0 (128/128) x Tp 1 1 1 1 1 1 1 0 1 (128/128) x Tp 1 1 1 1 1 1 1 1 0 (128/128) x Tp 1 1 1 1 1 1 1 1 1 (128/128) x Tp (Note15) W10 to W18:S1/P1/G1 pwm duty data W20 to W28:S2/P2/G2 pwm duty data W30 to W38:S3/P3/G3 pwm duty data W40 to W48:S4/P4/G4 pwm duty data W50 to W58:S5/P5/G5 pwm duty data W60 to W68:S6/P6/G6 pwm duty data W70 to W78:S7/P7/G7 pwm duty data W80 to W88:S8/P8/G8 pwm duty data W90 to W98:S9/P9/G9 pwm duty data www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 22/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M Display Data and Output Pin Correspondence 1.1/5 duty Master (Note16) Output Pin S1/P1/G1 S2/P2/G2 S3/P3/G3 S4/P4/G4 S5/P5/G5 S6/P6/G6 S7/P7/G7 S8/P8/G8 S9/P9/G9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 KS1/S53 KS2/S54 KS3/S55 KS4/S56 KS5/S57 KS6/S58 KI1/S59 KI2/S60 KI3/S61 KI4/S62 KI5/S63 COM1 D1 D6 D11 D16 D21 D26 D31 D36 D41 D46 D51 D56 D61 D66 D71 D76 D81 D86 D91 D96 D101 D106 D111 D116 D121 D126 D131 D136 D141 D146 D151 D156 D161 D166 D171 D176 D181 D186 D191 D196 D201 D206 D211 D216 D221 D226 D231 D236 D241 D246 D251 D256 D261 D266 D271 D276 D281 D286 D291 D296 D301 D306 D311 www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 COM2 D2 D7 D12 D17 D22 D27 D32 D37 D42 D47 D52 D57 D62 D67 D72 D77 D82 D87 D92 D97 D102 D107 D112 D117 D122 D127 D132 D137 D142 D147 D152 D157 D162 D167 D172 D177 D182 D187 D192 D197 D202 D207 D212 D217 D222 D227 D232 D237 D242 D247 D252 D257 D262 D267 D272 D277 D282 D287 D292 D297 D302 D307 D312 COM3 D3 D8 D13 D18 D23 D28 D33 D38 D43 D48 D53 D58 D63 D68 D73 D78 D83 D88 D93 D98 D103 D108 D113 D118 D123 D128 D133 D138 D143 D148 D153 D158 D163 D168 D173 D178 D183 D188 D193 D198 D203 D208 D213 D218 D223 D228 D233 D238 D243 D248 D253 D258 D263 D268 D273 D278 D283 D288 D293 D298 D303 D308 D313 23/66 COM4 D4 D9 D14 D19 D24 D29 D34 D39 D44 D49 D54 D59 D64 D69 D74 D79 D84 D89 D94 D99 D104 D109 D114 D119 D124 D129 D134 D139 D144 D149 D154 D159 D164 D169 D174 D179 D184 D189 D194 D199 D204 D209 D214 D219 D224 D229 D234 D239 D244 D249 D254 D259 D264 D269 D274 D279 D284 D289 D294 D299 D304 D309 D314 COM5 D5 D10 D15 D20 D25 D30 D35 D40 D45 D50 D55 D60 D65 D70 D75 D80 D85 D90 D95 D100 D105 D110 D115 D120 D125 D130 D135 D140 D145 D150 D155 D160 D165 D170 D175 D180 D185 D190 D195 D200 D205 D210 D215 D220 D225 D230 D235 D240 D245 D250 D255 D260 D265 D270 D275 D280 D285 D290 D295 D300 D305 D310 D315 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M (Note16) Output Pin CLKIO/S64 SYNCIO/S65 S66/TESTIN COM5/S67 COM4/S68 COM3/S69 COM2/S70 COM1/S71 S72 OSC_IN/S73 COM1 D316 D321 COM2 D317 D322 COM3 D318 D323 COM4 D319 D324 COM5 D320 D325 D326 D331 D327 D332 D328 D333 D329 D334 D330 D335 (Note 16) The Segment Output Port function is assumed to be selected for the output pins – S1/P1/G1 to S9/P9/G9, KS1/S53 to KS6/S58, KI1/S59 to KI5/S63, OSC_IN/S73. Also, COM5/S67 pin is used as Common output. During 1 chip mode, S66/TESTIN functions as TESTIN input. During 2 chip mode(Master with Slave), CLKIO/S64 and SYNCIO/S65 function as CLK and SYNC outputs. To illustrate further, the states of the S21 output pin is given in the table below. Display data State of S21 Output Pin D101 D102 D103 D104 D105 0 0 0 0 0 LCD Segments corresponding to COM1 to COM5 are OFF. 0 0 0 0 1 LCD Segment corresponding to COM5 is ON. 0 0 0 1 0 LCD Segment corresponding to COM4 is ON. 0 0 0 1 1 LCD Segments corresponding to COM4 and COM5 are ON. 0 0 1 0 0 LCD Segment corresponding to COM3 is ON. 0 0 1 0 1 LCD Segments corresponding to COM3 and COM5 are ON. 0 0 1 1 0 LCD Segments corresponding to COM3 and COM4 are ON. 0 0 1 1 1 LCD Segments corresponding to COM3, COM4 and COM5 are ON. 0 1 0 0 0 LCD Segment corresponding to COM2 is ON. 0 1 0 0 1 LCD Segments corresponding to COM2 and COM5 are ON. 0 1 0 1 0 LCD Segments corresponding to COM2 and COM4 are ON. 0 1 0 1 1 LCD Segments corresponding to COM2, COM4 and COM5 are ON. 0 1 1 0 0 LCD Segments corresponding to COM2 and COM3 are ON. 0 1 1 0 1 LCD Segments corresponding to COM2, COM3, and COM5 are ON. 0 1 1 1 0 LCD Segments corresponding to COM2, COM3, and COM4 are ON. 0 1 1 1 1 LCD Segments corresponding to COM2, COM3, COM4 and COM5 are ON. 1 0 0 0 0 LCD Segment corresponding to COM1 is ON. 1 0 0 0 1 LCD Segment corresponding to COM1 and COM5 are ON. 1 0 0 1 0 LCD Segment corresponding to COM1 and COM4 are ON. 1 0 0 1 1 LCD Segment corresponding to COM1, COM4 and COM5 are ON. 1 0 1 0 0 LCD Segment corresponding to COM1 and COM3 are ON. 1 0 1 0 1 LCD Segment corresponding to COM1, COM3 and COM5 are ON. 1 0 1 1 0 LCD Segment corresponding to COM1, COM3 and COM4 are ON. 1 0 1 1 1 LCD Segment corresponding to COM1, COM3, COM4 and COM5 are ON. 1 1 0 0 0 LCD Segment corresponding to COM1 and COM2 are ON. 1 1 0 0 1 LCD Segment corresponding to COM1, COM2 and COM5 are ON. 1 1 0 1 0 LCD Segment corresponding to COM1, COM2 and COM4 are ON. 1 1 0 1 1 LCD Segment corresponding to COM1, COM2, COM4 and COM5 are ON. 1 1 1 0 0 LCD Segment corresponding to COM1, COM2 and COM3 are ON. 1 1 1 0 1 LCD Segment corresponding to COM1, COM2, COM3 and COM5 are ON. 1 1 1 1 0 LCD Segment corresponding to COM1, COM2, COM3 and COM4 are ON. LCD Segment corresponding to COM1, COM2, COM3, COM4 and COM5 are ON. 1 1 1 1 1 www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 24/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M 2.1/5 duty Slave (Note17) Output Pin S1/P1/G1 S2/P2/G2 S3/P3/G3 S4/P4/G4 S5/P5/G5 S6/P6/G6 S7/P7/G7 S8/P8/G8 S9/P9/G9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 COM1 D1 D6 D11 D16 D21 D26 D31 D36 D41 D46 D51 D56 D61 D66 D71 D76 D81 D86 D91 D96 D101 D106 D111 D116 D121 D126 D131 D136 D141 D146 D151 D156 D161 D166 D171 D176 D181 D186 D191 D196 D201 D206 D211 D216 D221 D226 D231 D236 D241 D246 D251 D256 D261 D266 D271 D276 D281 D286 D291 D296 D301 D306 D311 www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 COM2 D2 D7 D12 D17 D22 D27 D32 D37 D42 D47 D52 D57 D62 D67 D72 D77 D82 D87 D92 D97 D102 D107 D112 D117 D122 D127 D132 D137 D142 D147 D152 D157 D162 D167 D172 D177 D182 D187 D192 D197 D202 D207 D212 D217 D222 D227 D232 D237 D242 D247 D252 D257 D262 D267 D272 D277 D282 D287 D292 D297 D302 D307 D312 COM3 D3 D8 D13 D18 D23 D28 D33 D38 D43 D48 D53 D58 D63 D68 D73 D78 D83 D88 D93 D98 D103 D108 D113 D118 D123 D128 D133 D138 D143 D148 D153 D158 D163 D168 D173 D178 D183 D188 D193 D198 D203 D208 D213 D218 D223 D228 D233 D238 D243 D248 D253 D258 D263 D268 D273 D278 D283 D288 D293 D298 D303 D308 D313 25/66 COM4 D4 D9 D14 D19 D24 D29 D34 D39 D44 D49 D54 D59 D64 D69 D74 D79 D84 D89 D94 D99 D104 D109 D114 D119 D124 D129 D134 D139 D144 D149 D154 D159 D164 D169 D174 D179 D184 D189 D194 D199 D204 D209 D214 D219 D224 D229 D234 D239 D244 D249 D254 D259 D264 D269 D274 D279 D284 D289 D294 D299 D304 D309 D314 COM5 D5 D10 D15 D20 D25 D30 D35 D40 D45 D50 D55 D60 D65 D70 D75 D80 D85 D90 D95 D100 D105 D110 D115 D120 D125 D130 D135 D140 D145 D150 D155 D160 D165 D170 D175 D180 D185 D190 D195 D200 D205 D210 D215 D220 D225 D230 D235 D240 D245 D250 D255 D260 D265 D270 D275 D280 D285 D290 D295 D300 D305 D310 D315 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M (Note17) Output Pin CLKIO/S64 SYNCIO/S65 S66/TESTIN COM5/S67 COM4/S68 COM3/S69 COM2/S70 COM1/S71 S72 OSC_IN/S73 COM1 COM2 COM3 COM4 COM5 D316 D321 D326 D331 D336 D341 D346 D351 D317 D322 D327 D332 D337 D342 D347 D352 D318 D323 D328 D333 D338 D343 D348 D353 D319 D324 D329 D334 D339 D344 D349 D354 D320 D325 D330 D335 D340 D345 D350 D355 (Note 17) The Segment Output Port function is assumed to be selected for the output pins – S1/P1/G1 to S9/P9/G9. Also, CLKIO/S64 and SYNCIO/S65 pins are used as SYNC and CLK inputs. To illustrate further, the states of the S21 output pin is given in the table below. Display data State of S21 Output Pin D101 D102 D103 D104 D105 0 0 0 0 0 LCD Segments corresponding to COM1 to COM5 are OFF. 0 0 0 0 1 LCD Segment corresponding to COM5 is ON. 0 0 0 1 0 LCD Segment corresponding to COM4 is ON. 0 0 0 1 1 LCD Segments corresponding to COM4 and COM5 are ON. 0 0 1 0 0 LCD Segment corresponding to COM3 is ON. 0 0 1 0 1 LCD Segments corresponding to COM3 and COM5 are ON. 0 0 1 1 0 LCD Segments corresponding to COM3 and COM4 are ON. 0 0 1 1 1 LCD Segments corresponding to COM3, COM4 and COM5 are ON. 0 1 0 0 0 LCD Segment corresponding to COM2 is ON. 0 1 0 0 1 LCD Segments corresponding to COM2 and COM5 are ON. 0 1 0 1 0 LCD Segments corresponding to COM2 and COM4 are ON. 0 1 0 1 1 LCD Segments corresponding to COM2, COM4 and COM5 are ON. 0 1 1 0 0 LCD Segments corresponding to COM2 and COM3 are ON. 0 1 1 0 1 LCD Segments corresponding to COM2, COM3, and COM5 are ON. 0 1 1 1 0 LCD Segments corresponding to COM2, COM3, and COM4 are ON. 0 1 1 1 1 LCD Segments corresponding to COM2, COM3, COM4 and COM5 are ON. 1 0 0 0 0 LCD Segment corresponding to COM1 is ON. 1 0 0 0 1 LCD Segment corresponding to COM1 and COM5 are ON. 1 0 0 1 0 LCD Segment corresponding to COM1 and COM4 are ON. 1 0 0 1 1 LCD Segment corresponding to COM1, COM4 and COM5 are ON. 1 0 1 0 0 LCD Segment corresponding to COM1 and COM3 are ON. 1 0 1 0 1 LCD Segment corresponding to COM1, COM3 and COM5 are ON. 1 0 1 1 0 LCD Segment corresponding to COM1, COM3 and COM4 are ON. 1 0 1 1 1 LCD Segment corresponding to COM1, COM3, COM4 and COM5 are ON. 1 1 0 0 0 LCD Segment corresponding to COM1 and COM2 are ON. 1 1 0 0 1 LCD Segment corresponding to COM1, COM2 and COM5 are ON. 1 1 0 1 0 LCD Segment corresponding to COM1, COM2 and COM4 are ON. 1 1 0 1 1 LCD Segment corresponding to COM1, COM2, COM4 and COM5 are ON. 1 1 1 0 0 LCD Segment corresponding to COM1, COM2 and COM3 are ON. 1 1 1 0 1 LCD Segment corresponding to COM1, COM2, COM3 and COM5 are ON. 1 1 1 1 0 LCD Segment corresponding to COM1, COM2, COM3 and COM4 are ON. LCD Segment corresponding to COM1, COM2, COM3, COM4 and COM5 are ON. 1 1 1 1 1 www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 26/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M 3.1/4 duty Master (Note18) Output Pin S1/P1/G1 S2/P2/G2 S3/P3/G3 S4/P4/G4 S5/P5/G5 S6/P6/G6 S7/P7/G7 S8/P8/G8 S9/P9/G9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 KS1/S53 KS2/S54 KS3/S55 KS4/S56 KS5/S57 KS6/S58 KI1/S59 KI2/S60 KI3/S61 KI4/S62 KI5/S63 COM1 D1 D5 D9 D13 D17 D21 D25 D29 D33 D37 D41 D45 D49 D53 D57 D61 D65 D69 D73 D77 D81 D85 D89 D93 D97 D101 D105 D109 D113 D117 D121 D125 D129 D133 D137 D141 D145 D149 D153 D157 D161 D165 D169 D173 D177 D181 D185 D189 D193 D197 D201 D205 D209 D213 D217 D221 D225 D229 D233 D237 D241 D245 D249 www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 COM2 D2 D6 D10 D14 D18 D22 D26 D30 D34 D38 D42 D46 D50 D54 D58 D62 D66 D70 D74 D78 D82 D86 D90 D94 D98 D102 D106 D110 D114 D118 D122 D126 D130 D134 D138 D142 D146 D150 D154 D158 D162 D166 D170 D174 D178 D182 D186 D190 D194 D198 D202 D206 D210 D214 D218 D222 D226 D230 D234 D238 D242 D246 D250 COM3 D3 D7 D11 D15 D19 D23 D27 D31 D35 D39 D43 D47 D51 D55 D59 D63 D67 D71 D75 D79 D83 D87 D91 D95 D99 D103 D107 D111 D115 D119 D123 D127 D131 D135 D139 D143 D147 D151 D155 D159 D163 D167 D171 D175 D179 D183 D187 D191 D195 D199 D203 D207 D211 D215 D219 D223 D227 D231 D235 D239 D243 D247 D251 27/66 COM4 D4 D8 D12 D16 D20 D24 D28 D32 D36 D40 D44 D48 D52 D56 D60 D64 D68 D72 D76 D80 D84 D88 D92 D96 D100 D104 D108 D112 D116 D120 D124 D128 D132 D136 D140 D144 D148 D152 D156 D160 D164 D168 D172 D176 D180 D184 D188 D192 D196 D200 D204 D208 D212 D216 D220 D224 D228 D232 D236 D240 D244 D248 D252 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M (Note18) Output Pin CLKIO/S64 SYNCIO/S65 S66/TESTIN COM5/S67 COM4/S68 COM3/S69 COM2/S70 COM1/S71 S72 OSC_IN/S73 COM1 D253 D257 COM2 D254 D258 COM3 D255 D259 COM4 D256 D260 D261 D262 D263 D264 D265 D269 D266 D270 D267 D271 D268 D272 (Note 18) The Segment Output Port function is assumed to be selected for the output pins – S1/P1/G1 to S9/P9/G9, KS1/S53 to KS6/S58, KI1/S59 to KI5/S63, OSC_IN/S73. During 1 chip mode, S66/TESTIN functions as TESTIN input. During 2 chip mode(Master with Slave), CLKIO/S64 and SYNCIO/S65 function as CLK and SYNC outputs. To illustrate further, the states of the S21 output pin is given in the table below. Display data State of S21 Output Pin D81 D82 D83 D84 0 0 0 0 LCD Segments corresponding to COM1 to COM4 are OFF. 0 0 0 1 LCD Segment corresponding to COM4 is ON. 0 0 1 0 LCD Segment corresponding to COM3 is ON. 0 0 1 1 LCD Segments corresponding to COM3 and COM4 are ON. 0 1 0 0 LCD Segment corresponding to COM2 is ON. 0 1 0 1 LCD Segments corresponding to COM2 and COM4 are ON. 0 1 1 0 LCD Segments corresponding to COM2 and COM3 are ON. 0 1 1 1 LCD Segments corresponding to COM2, COM3 and COM4 are ON. 1 0 0 0 LCD Segment corresponding to COM1 is ON. 1 0 0 1 LCD Segments corresponding to COM1 and COM4 are ON. 1 0 1 0 LCD Segments corresponding to COM1 and COM3 are ON. 1 0 1 1 LCD Segments corresponding to COM1, COM3 and COM4 are ON. 1 1 0 0 LCD Segments corresponding to COM1 and COM2 are ON. 1 1 0 1 LCD Segments corresponding to COM1, COM2, and COM4 are ON. 1 1 1 0 LCD Segments corresponding to COM1, COM2, and COM3 are ON. 1 1 1 1 LCD Segments corresponding to COM1, COM2, COM3 and COM4 are ON. www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 28/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M 4.1/4 duty Slave (Note19) Output Pin S1/P1/G1 S2/P2/G2 S3/P3/G3 S4/P4/G4 S5/P5/G5 S6/P6/G6 S7/P7/G7 S8/P8/G8 S9/P9/G9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 COM1 D1 D5 D9 D13 D17 D21 D25 D29 D33 D37 D41 D45 D49 D53 D57 D61 D65 D69 D73 D77 D81 D85 D89 D93 D97 D101 D105 D109 D113 D117 D121 D125 D129 D133 D137 D141 D145 D149 D153 D157 D161 D165 D169 D173 D177 D181 D185 D189 D193 D197 D201 D205 D209 D213 D217 D221 D225 D229 D233 D237 D241 D245 D249 www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 COM2 D2 D6 D10 D14 D18 D22 D26 D30 D34 D38 D42 D46 D50 D54 D58 D62 D66 D70 D74 D78 D82 D86 D90 D94 D98 D102 D106 D110 D114 D118 D122 D126 D130 D134 D138 D142 D146 D150 D154 D158 D162 D166 D170 D174 D178 D182 D186 D190 D194 D198 D202 D206 D210 D214 D218 D222 D226 D230 D234 D238 D242 D246 D250 COM3 D3 D7 D11 D15 D19 D23 D27 D31 D35 D39 D43 D47 D51 D55 D59 D63 D67 D71 D75 D79 D83 D87 D91 D95 D99 D103 D107 D111 D115 D119 D123 D127 D131 D135 D139 D143 D147 D151 D155 D159 D163 D167 D171 D175 D179 D183 D187 D191 D195 D199 D203 D207 D211 D215 D219 D223 D227 D231 D235 D239 D243 D247 D251 29/66 COM4 D4 D8 D12 D16 D20 D24 D28 D32 D36 D40 D44 D48 D52 D56 D60 D64 D68 D72 D76 D80 D84 D88 D92 D96 D100 D104 D108 D112 D116 D120 D124 D128 D132 D136 D140 D144 D148 D152 D156 D160 D164 D168 D172 D176 D180 D184 D188 D192 D196 D200 D204 D208 D212 D216 D220 D224 D228 D232 D236 D240 D244 D248 D252 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M (Note19) Output Pin CLKIO/S64 SYNCIO/S65 S66/TESTIN COM5/S67 COM4/S68 COM3/S69 COM2/S70 COM1/S71 S72 OSC_IN/S73 COM1 COM2 COM3 COM4 D253 D257 D261 D265 D269 D273 D277 D281 D254 D258 D262 D266 D270 D274 D278 D282 D255 D259 D263 D267 D271 D275 D279 D283 D256 D260 D264 D268 D272 D276 D280 D284 (Note 19) The Segment Output Port function is assumed to be selected for the output pins – S1/P1/G1 to S9/P9/G9. Also, CLKIO/S64 and SYNCIO/S65 pins are used as SYNC and CLK inputs. To illustrate further, the states of the S21 output pin is given in the table below. Display data State of S21 Output Pin D81 D82 D83 D84 0 0 0 0 LCD Segments corresponding to COM1 to COM4 are OFF. 0 0 0 1 LCD Segment corresponding to COM4 is ON. 0 0 1 0 LCD Segment corresponding to COM3 is ON. 0 0 1 1 LCD Segments corresponding to COM3 and COM4 are ON. 0 1 0 0 LCD Segment corresponding to COM2 is ON. 0 1 0 1 LCD Segments corresponding to COM2 and COM4 are ON. 0 1 1 0 LCD Segments corresponding to COM2 and COM3 are ON. 0 1 1 1 LCD Segments corresponding to COM2, COM3 and COM4 are ON. 1 0 0 0 LCD Segment corresponding to COM1 is ON. 1 0 0 1 LCD Segments corresponding to COM1 and COM4 are ON. 1 0 1 0 LCD Segments corresponding to COM1 and COM3 are ON. 1 0 1 1 LCD Segments corresponding to COM1, COM3 and COM4 are ON. 1 1 0 0 LCD Segments corresponding to COM1 and COM2 are ON. 1 1 0 1 LCD Segments corresponding to COM1, COM2, and COM4 are ON. 1 1 1 0 LCD Segments corresponding to COM1, COM2, and COM3 are ON. 1 1 1 1 LCD Segments corresponding to COM1, COM2, COM3 and COM4 are ON. www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 30/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M 5. 1/3 duty Master (Note20) Output Pin S1/P1/G1 S2/P2/G2 S3/P3/G3 S4/P4/G4 S5/P5/G5 S6/P6/G6 S7/P7/G7 S8/P8/G8 S9/P9/G9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 KS1/S53 KS2/S54 KS3/S55 KS4/S56 KS5/S57 KS6/S58 KI1/S59 KI2/S60 KI3/S61 KI4/S62 KI5/S63 COM1 D1 D4 D7 D10 D13 D16 D19 D22 D25 D28 D31 D34 D37 D40 D43 D46 D49 D52 D55 D58 D61 D64 D67 D70 D73 D76 D79 D82 D85 D88 D91 D94 D97 D100 D103 D106 D109 D112 D115 D118 D121 D124 D127 D130 D133 D136 D139 D142 D145 D148 D151 D154 D157 D160 D163 D166 D169 D172 D175 D178 D181 D184 D187 www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 COM2 D2 D5 D8 D11 D14 D17 D20 D23 D26 D29 D32 D35 D38 D41 D44 D47 D50 D53 D56 D59 D62 D65 D68 D71 D74 D77 D80 D83 D85 D89 D92 D95 D98 D101 D104 D107 D110 D113 D116 D119 D122 D125 D128 D131 D134 D137 D140 D143 D146 D149 D152 D155 D158 D161 D164 D167 D170 D173 D176 D179 D182 D185 D188 COM3 D3 D6 D9 D12 D15 D18 D21 D24 D27 D30 D33 D36 D39 D42 D45 D48 D51 D54 D57 D60 D63 D66 D69 D72 D75 D78 D81 D84 D87 D90 D93 D96 D99 D102 D105 D108 D111 D114 D117 D120 D123 D126 D129 D132 D135 D138 D141 D144 D147 D150 D153 D156 D159 D162 D165 D168 D171 D174 D177 D180 D183 D186 D189 31/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M (Note20) Output Pin CLKIO/S64 SYNCIO/S65 S66/TESTIN COM5/S67 COM4/S68 COM3/S69 COM2/S70 COM1/S71 S72 OSC_IN/S73 COM1 D190 D193 COM2 D191 D194 COM3 D192 D195 D196 D197 D198 D199 D202 D200 D203 D201 D204 (Note 20) The Segment Output Port function is assumed to be selected for the output pins – S1/P1/G1 to S9/P9/G9, KS1/S53 to KS6/S58, KI1/S59 to KI5/S63, OSC_IN/S73. During 1 chip mode, S66/TESTIN functions as TESTIN input. During 2 chip mode(Master with Slave), CLKIO/S64 and SYNCIO/S65 function as CLK and SYNC outputs. To illustrate further, the states of the S21 output pin is given in the table below. Display data State of S21 Output Pin D61 D62 D63 0 0 0 LCD Segments corresponding to COM1 to COM3 are OFF. 0 0 1 LCD Segment corresponding to COM3 is ON. 0 1 0 LCD Segment corresponding to COM2 is ON. 0 1 1 LCD Segments corresponding to COM2 and COM3 are ON. 1 0 0 LCD Segment corresponding to COM1 is ON. 1 0 1 LCD Segments corresponding to COM1 and COM3 are ON. 1 1 0 LCD Segments corresponding to COM1 and COM2 are ON. 1 1 1 LCD Segments corresponding to COM1, COM2 and COM3 are ON. www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 32/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M 6.1/3 duty Slave (Note21) Output Pin S1/P1/G1 S2/P2/G2 S3/P3/G3 S4/P4/G4 S5/P5/G5 S6/P6/G6 S7/P7/G7 S8/P8/G8 S9/P9/G9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 COM1 D1 D4 D7 D10 D13 D16 D19 D22 D25 D28 D31 D34 D37 D40 D43 D46 D49 D52 D55 D58 D61 D64 D67 D70 D73 D76 D79 D82 D85 D88 D91 D94 D97 D100 D103 D106 D109 D112 D115 D118 D121 D124 D127 D130 D133 D136 D139 D142 D145 D148 D151 D154 D157 D160 D163 D166 D169 D172 D175 D178 D181 D184 D187 www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 COM2 D2 D5 D8 D11 D14 D17 D20 D23 D26 D29 D32 D35 D38 D41 D44 D47 D50 D53 D56 D59 D62 D65 D68 D71 D74 D77 D80 D83 D85 D89 D92 D95 D98 D101 D104 D107 D110 D113 D116 D119 D122 D125 D128 D131 D134 D137 D140 D143 D146 D149 D152 D155 D158 D161 D164 D167 D170 D173 D176 D179 D182 D185 D188 COM3 D3 D6 D9 D12 D15 D18 D21 D24 D27 D30 D33 D36 D39 D42 D45 D48 D51 D54 D57 D60 D63 D66 D69 D72 D75 D78 D81 D84 D87 D90 D93 D96 D99 D102 D105 D108 D111 D114 D117 D120 D123 D126 D129 D132 D135 D138 D141 D144 D147 D150 D153 D156 D159 D162 D165 D168 D171 D174 D177 D180 D183 D186 D189 33/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M (Note21) Output Pin CLKIO/S64 SYNCIO/S65 S66/TESTIN COM5/S67 COM4/S68 COM3/S69 COM2/S70 COM1/S71 S72 OSC/S73 COM1 COM2 COM3 D190 D193 D196 D199 D202 D205 D208 D211 D191 D194 D197 D200 D203 D206 D209 D212 D192 D195 D198 D201 D204 D207 D210 D213 (Note 21) The Segment Output Port function is assumed to be selected for the output pins – S1/P1/G1 to S9/P9/G9. Also, CLKIO/S64 and SYNCIO/S65 pins are used as SYNC and CLK inputs. To illustrate further, the states of the S21 output pin is given in the table below. Display data State of S21 Output Pin D61 D62 D63 0 0 0 LCD Segments corresponding to COM1 to COM3 are OFF. 0 0 1 LCD Segment corresponding to COM3 is ON. 0 1 0 LCD Segment corresponding to COM2 is ON. 0 1 1 LCD Segments corresponding to COM2 and COM3 are ON. 1 0 0 LCD Segment corresponding to COM1 is ON. 1 0 1 LCD Segments corresponding to COM1 and COM3 are ON. 1 1 0 LCD Segments corresponding to COM1 and COM2 are ON. 1 1 1 LCD Segments corresponding to COM1, COM2 and COM3 are ON. www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 34/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M 7. 1/1 duty (Static) Master (Note22) Output Pin COM1 S1/P1/G1 D1 S2/P2/G2 D2 S3/P3/G3 D3 S4/P4/G4 D4 S5/P5/G5 D5 S6/P6/G6 D6 S7/P7/G7 D7 S8/P8/G8 D8 S9/P9/G9 D9 S10 D10 S11 D11 S12 D12 S13 D13 S14 D14 S15 D15 S16 D16 S17 D17 S18 D18 S19 D19 S20 D20 S21 D21 S22 D22 S23 D23 S24 D24 S25 D25 S26 D26 S27 D27 S28 D28 S29 D29 S30 D30 S31 D31 S32 D32 S33 D33 S34 D34 S35 D35 S36 D36 S37 D37 S38 D38 S39 D39 S40 D40 S41 D41 S42 D42 S43 D43 S44 D44 S45 D45 S46 D46 S47 D47 S48 D48 S49 D49 S50 D50 S51 D51 S52 D52 KS1/S53 D53 KS2/S54 D54 KS3/S55 D55 KS4/S56 D56 KS5/S57 D57 KS6/S58 D58 KI1/S59 D59 KI2/S60 D60 KI3/S61 D61 KI4/S62 D62 KI5/S63 D63 www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 35/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M (Note22) Output Pin CLKIO/S64 SYNCIO/S65 S66/TESTIN COM5/S67 COM4/S68 COM3/S69 COM2/S70 COM1/S71 S72 OSC_IN/S73 COM1 D64 D65 D66 D67 D68 (Note 22) The Segment Output Port function is assumed to be selected for the output pins – S1/P1/G1 to S9/P9/G9, KS1/S53 to KS6/S58, KI1/S59 to KI5/S63, OSC_IN/S73. During 1chip mode, S66/TESTIN functions as TESTIN input. During 2 chip mode(Master with Slave), CLKIO/S64 and SYNCIO/S65 function as CLK and SYNC outputs. To illustrate further, the states of the S21 output pin is given in the table below. Display Data State of S21Output Pin D21 0 LCD Segment corresponding to COM1 is OFF. LCD Segment corresponding to COM1 is ON. 1 www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 36/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M 8. 1/1 duty (Static) Slave (Note23) Output Pin S1/P1/G1 S2/P2/G2 S3/P3/G3 S4/P4/G4 S5/P5/G5 S6/P6/G6 S7/P7/G7 S8/P8/G8 S9/P9/G9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 COM1 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 37/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M (Note23) Output Pin CLKIO/S64 SYNCIO/S65 S66/TESTIN COM5/S67 COM4/S68 COM3/S69 COM2/S70 COM1/S71 S72 OSC_IN/S73 COM1 D64 D65 D66 D67 D68 D69 D70 D71 (Note 23) The Segment Output Port function is assumed to be selected for the output pins – S1/P1/G1 to S9/P9/G9. Also, CLKIO/S64 and SYNCIO/S65 pins are used as SYNC and CLK inputs. To illustrate further, the states of the S21 output pin is given in the table below. Display Data State of S21Output Pin D21 0 LCD Segment corresponding to COM1 is OFF. LCD Segment corresponding to COM1 is ON. 1 www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 38/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M Serial Data Output 1.When SCL is stopped at the low level (Note24) SCE SCL SDI 1 1 0 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 SDO X KD1 KD2 KD27 KD28 KD29 KD30 SA Output Data Figure 15. Serial Data Output Format (Note24) 1. X=Don’t care 2. B0 to B3, A0 to A3: Serial Interface address 2. When SCL is stopped at the high level (Note25) SCE SCL SDI 1 1 0 0 B0 B1 B2 B3 0 0 1 0 A0 A1 A2 A3 SDO KD1 KD2 KD3 KD28 KD29 KD30 SA X Output Data Figure 16. Serial Data Output Format (Note25) 1. X=Don’t care 2. B0 to B3, A0 to A3: Serial Interface address 3. Serial Interface address: 43H 4. KD1 to KD30: Key data 5. SA: Sleep acknowledge data 6. If a key data read operation is executed when SDO is high, the read key data (KD1 to KD30) and sleep acknowledge data (SA) will be invalid. www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 39/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M Output Data 1.KD1 TO KD30: KEY DATA When a key matrix of up to 30 keys is formed from the KS1 to KS6 output pins and the KI1 to KI5 input pins and one of those keys are pressed, the key output data corresponding to that key will be set to 1. The table shows the relationship between those pins and the key data bits. Item KS1 KS2 KS3 KS4 KS5 KS6 KI1 KD1 KD6 KD11 KD16 KD21 KD26 KI2 KD2 KD7 KD12 KD17 KD22 KD27 KI3 KD3 KD8 KD13 KD18 KD23 KD28 KI4 KD4 KD9 KD14 KD19 KD24 KD29 KI5 KD5 KD10 KD15 KD20 KD25 KD30 2.SA: Sleep Acknowledge Data This output data is set to the state when the key is pressed. In that case SDO will go to the low level. If serial data is input during this period and the mode is set (normal mode or sleep mode), the IC will be set to that mode. SA is set to 1 in the sleep mode and to 0 in the normal mode. Sleep Mode Sleep mode is set up by setting the BU0 to BU2 in the control data to 1. The segment outputs will all go low and the common outputs will also go low, and the oscillator on the OSC pin will stop (it will be started by a key press). This reduces power dissipation. This mode is cleared by sending control data with all the BU0 to BU2 set to 0. However, note that the S1/P1/G1 to S9/P9/G9 outputs can be used as general-purpose output ports according to the state of the P0 to P3 control data bits, even in sleep mode. (See Control Data Functions.) www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 40/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M Key Scan Operation Functions 1.Key Scan Timing The key scan period is 4608T(s). To reliably determine the on/off state of the keys, the BU97540KV-M scans the keys twice and determines that a key has been pressed when the key data agrees. It outputs a key data read request (a low level on SDO) 9840T(s) after starting a key scan. If the key data does not agree and a key was pressed at that point, it scans the keys again. Thus the BU97540KV-M cannot detect a key press shorter than 9840T(s). KS1 * KS2 * KS3 * KS4 * KS5 * KS6 * 1 1 2 * 2 3 * 3 4 * 4 5 * 5 * 6 6 9216T[S] T= * 1 fosc (Note26) Figure 17. Key Scan Timing (Note26) In sleep mode, the high/low state of these pins is determined by the BU0 to BU2 bits in the control data. Key scan output signals are not output from pins that are set “L”. 2.In Normal Mode The pins KS1 to KS6 are set “H”. When a key is pressed a key scan is started and the keys are scanned until all keys are released. Multiple key presses are recognized by determining whether multiple key data bits are set. If a key is pressed for longer than 9840T(s) (Where T=1/fosc ) the BU97540KV-M outputs a key data read request (a low level on SDO) to the controller. The controller acknowledges this request and reads the key data. However, if SCE is high during a serial data transfer, SDO will be set high. After the controller reads the key data, the key data read request is cleared (SDO is set high) and the BU97540KV-M performs another key scan. Also note that SDO, being an open-drain output, requires a pull-up resistor (between 1 and 10KΩ). Key Input 1 Key Input 2 Key scan 9840T[S] 9840T[S] 9840T[S] CE SCE Serial data transfer Serial data transfer Key address(43H) 43H) Serial data transfer Key address Key address SDI DI SDO D0 Key data read Key data read Key data read request Key data read request Key data read 1 Key data read request T= fosc Figure 18. Key scan operation in normal mode www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 41/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M 3.In Sleep Mode The pins KS1 to KS6 are set to high or low by the BU0 to BU2 bits in the control data. (See the control data description for details.) If a key on one of the lines corresponding to a KS1 to KS6 pin which is set high is pressed, the oscillator on the OSC pin is started and a key scan is performed. Keys are scanned until all keys are released. Multiple key presses are recognized by determining whether multiple key data bits are set. If a key is pressed for longer than 9840T(s)(Where T=1/fosc) the BU97540KV-M outputs a key data read request (a low level on SDO) to the controller. The controller acknowledges this request and reads the key data. However, if SCE is high during a serial data transfer, SDO will be set high. After the controller reads the key data, the key data read request is cleared (SDO is set high) and the BU97540KV-M performs another key scan. However, this does not clear sleep mode. Also note that SDO, being an open-drain output, requires a pull-up resistor (between 1 and 10KΩ). Sleep mode key scan example Example: BU0=0, BU1=0, BU2=1 (sleep with only KS6 high) (L)KS1 (L)KS2 (L)KS3 When any one of these keys is pressed, the oscillator on the OSC pin is started and the keys are scanned. (L)KS4 (L)KS5 (H) (L)KS6 (Note27) Kl1 Kl2 Kl3 Kl4 Kl5 (Note 27) These diodes are required to reliable recognize multiple key presses on the KS6 line when sleep mode state with only KS6 high, as in the above example. That is, these diodes prevent incorrect operations due to sneak currents in the KS6 key scan output signal when keys on the KS1 to KS5 lines are pressed at the same time. Key Input 2 (KS6 line) Key scan 9840T[S] 9840T[S] CE SCE Serial data transfer Serial data transfer 43H) Key address(43H) Serial data transfer Key address SDI DI SDO D0 Key data read Key data read request Key data read Key data read request T= 1 fosc Figure 19. Key scan operation in sleep mode Multiple Key Presses Although the BU97540KV-M is capable of key scanning without inserting diodes for dual key presses, triple key presses on the KI1 to KI5 input pin lines, or multiple key presses on the KS1 to KS6 output pin lines, multiple presses other than these cases may result in keys that were not pressed recognized as having been pressed. Therefore, a diode must be inserted in series with each key. Applications that do not recognize multiple key presses of three or more keys should check the key data for three or more 1 bit and ignore such data. www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 42/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M Controller Key Data Read Techniques When the controller receives a key data read request from BU97540KV-M, it performs a key data read acquisition operation using either the Timer Based Key Data Acquisition or the Interrupt Based Key Data Acquisition. Timer Based Key Data Acquisition Technique Under the Timer Based Key Data Acquisition Technique, the controller uses a timer to determine the states of the keys (ON or OFF) and read the key data. Please refer to the flowchart below. SCE ＝「L 」 NO SDO ＝「L 」 YES Key data read processing Key data read processing: Refer to “Serial Data Output” Figure 20. Flowchart In this technique, the controller uses a timer to determine key on/off states and read the key data. The controller must check the SDO state when SCE is low every t7 period without fail. If SDO is low, the controller recognizes that a key has been pressed and executes the key data read operation. The period t7 in this technique must satisfy the following condition. T7>t4+t5+t6 If a key data read operation is executed when SDO is high, the read key data (KD1 to KD20) and sleep acknowledge data (SA) will be invalid. Key on Key on Key Input Key scan t3 t4 t3 SCE t3 t6 t6 t6 SDI t5 t5 t5 Key data read SDO Key data read request t7 t7 t7 t7 Controller determination Controller determination Controller determination Controller determination Controller determination (key on) (key on) (key on) (key on) (key on) t3: Key scan execution time when the key data agreed for two key scans. (9904T(s)) t4: Key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (19808T(s)) T = 1 / fosc t5: Key address (43H) transfer time t6: Key data read time Figure 21. Timer based key data read operation www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 43/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M Interrupt Based Key Data Acquisition Technique Under the Interrupt Based Key Data Acquisition Technique, the controller uses interrupts to determine the state of the keys (ON or OFF) and read the key data. Please refer to the flow chart diagram below. CE ＝「L 」 SCE SDO D0 ＝「L 」 NO YES Key data read processing Wait for at least t8 NO SDO D0 ＝「H 」 YES Key off Key data read processing: Refer to “Serial Data Output” Figure 22. Flowchart www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 44/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M In this technique, the controller uses interrupts to determine key on/off states and read the key data. The controller must check the SDO state when SCE is low. If SDO is low, the controller recognizes that a key has been pressed and executes the key data read operation. After that the next key on/off determination is performed after the time t8 has elapsed by checking the SDO state when SCE is low and reading the key data. The period t8 in this technique must satisfy t8 > t4. If a key data read operation is executed when SDO is high, the read key data (KD1 to KD20) and sleep acknowledge data (SA) will be invalid. Key on Key on Key Input Key scan t3 t3 t4 SCE t3 t6 t6 t6 t6 SDI t5 t5 t5 t5 Key data read SDO Key data read request Controller Controller determination determination (key on) (key on) t8 t8 t8 t8 Controller determination (key on) Controller determination (key on) Controller determination (key on) Controller determination (key on) t3: Key scan execution time when the key data agreed for two key scans. (9904T(s)) t4: Key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (19808T(s)) T = 1 / fosc t5: Key address (43H) transfer time t6: Key data read time Figure 23. Interrupt Based Key Data Read Operation www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 45/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M LCD Driving Waveforms 1. Line Inversion 1/5-Duty 1/3-Bias Drive Scheme fo[Hz] V LCD V LCD1 V LCD2 COM1 0V V LCD V LCD1 V LCD2 COM2 0V V LCD V LCD1 V LCD2 COM3 0V V LCD V LCD1 V LCD2 COM4 0V V LCD V LCD1 V LCD2 COM5 0V V LCD LCD driver output w hen all LCD V LCD1 segment corresponding to COM1, V LCD2 COM2, COM3, COM4 and COM5 are off 0V V LCD LCD driver output w hen only LCD segments V LCD1 corresponding to COM1 are on V LCD2 0V V LCD LCD driver output w hen only LCD segments V LCD1 corresponding to COM2 are on. V LCD2 0V V LCD LCD driver output w hen only LCD segments V LCD1 corresponding to COM1 and COM2 are on. V LCD2 0V V LCD LCD driver output w hen only LCD segments V LCD1 corresponding to COM3 are on. V LCD2 0V V LCD LCD driver output w hen LCD segments V LCD1 corresponding to COM1 and COM3 are on V LCD2 0V V LCD LCD driver output w hen LCD segments V LCD1 corresponding to COM2 and COM3 are on V LCD2 0V V LCD LCD driver output w hen LCD segments V LCD1 corresponding to COM1, COM2 and COM3 are on V LCD2 0V V LCD LCD driver output w hen LCD segments V LCD1 corresponding to COM1, COM2, COM3 V LCD2 and COM4 are on 0V V LCD LCD driver output w hen LCD segments V LCD1 corresponding to COM1, COM2 ,COM3 V LCD2 COM4 and COM5 are on 0V Figure 24. LCD Waveform (Line Inversion, 1/5 DUTY, 1/3 BIAS) www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 46/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M 2. Line Inversion 1/5-Duty 1/2-Bias Drive Scheme fo[Hz] V LCD V LCD1, V LCD2 COM1 0V V LCD V LCD1, V LCD2 COM2 0V V LCD V LCD1, V LCD2 COM3 0V V LCD V LCD1, V LCD2 COM4 0V V LCD V LCD1, V LCD2 COM5 0V LCD driver output w hen all LCD V LCD segment corresponding to COM1, V LCD1, V LCD2 COM2, COM3, COM4 and COM5 are off 0V V LCD LCD driver output w hen only LCD segments V LCD1, V LCD2 corresponding to COM1 are on 0V V LCD LCD driver output w hen only LCD segments V LCD1, V LCD2 corresponding to COM2 are on. 0V V LCD LCD driver output w hen only LCD segments V LCD1, V LCD2 corresponding to COM1 and COM2 are on. 0V V LCD LCD driver output w hen only LCD segments V LCD1, V LCD2 corresponding to COM3 are on. 0V V LCD LCD driver output w hen LCD segments V LCD1, V LCD2 corresponding to COM1 and COM3 are on 0V V LCD LCD driver output w hen LCD segments V LCD1, V LCD2 corresponding to COM2 and COM3 are on 0V V LCD LCD driver output w hen LCD segments V LCD1, V LCD2 corresponding to COM1, COM2 and COM3 are on 0V V LCD LCD driver output w hen LCD segments V LCD1, V LCD2 corresponding to COM4 are on 0V V LCD LCD driver output w hen LCD segments V LCD1, V LCD2 corresponding to COM2 and COM4 are on 0V V LCD LCD driver output w hen LCD segments V LCD1, V LCD2 corresponding to COM1, COM2, COM3 0V and COM4 are on V LCD V LCD1, V LCD2 0V LCD driver output w hen LCD segments corresponding to COM1, COM2, COM3, COM4 and COM5 Figure 25. LCD Waveform (Line Inversion, 1/5 DUTY, 1/2 BIAS) www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 47/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M 3. Line Inversion 1/4-Duty 1/3-Bias Drive Scheme fo[Hz] V LCD V LCD1 V LCD2 COM1 0V V LCD V LCD1 V LCD2 COM2 0V V LCD V LCD1 V LCD2 COM3 0V V LCD V LCD1 V LCD2 COM4 0V V LCD LCD driver output w hen all LCD V LCD1 segment corresponding to COM1, V LCD2 COM2, COM3 and COM4 are off 0V V LCD LCD driver output w hen only LCD segments V LCD1 corresponding to COM1 are on V LCD2 0V V LCD LCD driver output w hen only LCD segments V LCD1 corresponding to COM2 are on. V LCD2 0V V LCD LCD driver output w hen only LCD segments V LCD1 corresponding to COM1 and COM2 are on. V LCD2 0V V LCD LCD driver output w hen only LCD segments V LCD1 corresponding to COM3 are on. V LCD2 0V V LCD LCD driver output w hen LCD segments V LCD1 corresponding to COM1 and COM3 are on V LCD2 0V V LCD LCD driver output w hen LCD segments V LCD1 corresponding to COM2 and COM3 are on V LCD2 0V V LCD LCD driver output w hen LCD segments V LCD1 corresponding to COM1, COM2 and COM3 are on V LCD2 0V V LCD LCD driver output w hen only LCD segments V LCD1 corresponding to COM4 are on. V LCD2 0V V LCD LCD driver output w hen LCD segments V LCD1 corresponding to COM2 and COM4 are on V LCD2 0V V LCD LCD driver output w hen LCD segments V LCD1 corresponding to COM1, COM2, V LCD2 COM3, COM4 are on 0V Figure 26. LCD Waveform (Line Inversion, 1/4 DUTY, 1/3 BIAS) www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 48/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M 4. Line Inversion 1/4-Duty 1/2-Bias Drive Scheme fo[Hz] V LCD V LCD1, V LCD2 COM1 0V V LCD V LCD1, V LCD2 COM2 0V V LCD V LCD1, V LCD2 COM3 0V V LCD V LCD1, V LCD2 COM4 0V LCD driver output w hen all LCD V LCD segment corresponding to COM1, V LCD1, V LCD2 COM2, COM3 and COM4 are off 0V V LCD LCD driver output w hen only LCD segments V LCD1, V LCD2 corresponding to COM1 are on 0V V LCD LCD driver output w hen only LCD segments V LCD1, V LCD2 corresponding to COM2 are on. 0V V LCD LCD driver output w hen only LCD segments V LCD1, V LCD2 corresponding to COM1 and COM2 are on. 0V V LCD LCD driver output w hen only LCD segments V LCD1, V LCD2 corresponding to COM3 are on. 0V V LCD LCD driver output w hen LCD segments V LCD1, V LCD2 corresponding to COM1 and COM3 are on 0V V LCD LCD driver output w hen LCD segments V LCD1, V LCD2 corresponding to COM2 and COM3 are on 0V V LCD LCD driver output w hen LCD segments V LCD1, V LCD2 corresponding to COM1, COM2 and COM3 are on 0V V LCD LCD driver output w hen LCD segments V LCD1, V LCD2 corresponding to COM4 are on 0V V LCD LCD driver output w hen LCD segments V LCD1, V LCD2 corresponding to COM2 and COM4 are on 0V V LCD LCD driver output w hen LCD segments V LCD1, V LCD2 corresponding to COM1, COM2, COM3 0V and COM4 are on Figure 27. LCD Waveform (Line Inversion, 1/4 DUTY, 1/2 BIAS) www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 49/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M 5. Line Inversion 1/3-Duty 1/3-Bias Drive Scheme fo[Hz] V LCD V LCD1 V LCD2 COM1 0V V LCD V LCD1 V LCD2 COM2 0V V LCD V LCD1 V LCD2 COM3 0V V LCD LCD driver output when all LCD V LCD1 segment corresponding to COM1, V LCD2 COM2, and COM3 are off 0V V LCD LCD driver output when only LCD segments V LCD1 corresponding to COM1 are on V LCD2 0V V LCD LCD driver output when only LCD segments V LCD1 corresponding to COM2 are on. V LCD2 0V V LCD LCD driver output when only LCD segments V LCD1 corresponding to COM1 and COM2 are on. V LCD2 0V V LCD LCD driver output when only LCD segments V LCD1 corresponding to COM3 are on. V LCD2 0V V LCD LCD driver output when LCD segments V LCD1 corresponding to COM1 and COM3 are on V LCD2 0V V LCD LCD driver output when LCD segments V LCD1 corresponding to COM2 and COM3 are on V LCD2 0V V LCD LCD driver output when LCD segments V LCD1 corresponding to COM1, COM2 and COM3 are on V LCD2 0V Figure 28. LCD Waveform (Line Inversion, 1/3 DUTY, 1/3 BIAS) (Note28) (Note28) COM4 function is same as COM1 at 1/3 duty. www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 50/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M 6. Line Inversion 1/3-Duty 1/2-Bias Drive Scheme fo[Hz] V LCD V LCD 1, VLCD 2 COM1 0V V LCD V LCD 1, VLCD 2 COM2 0V V LCD V LCD 1, VLCD 2 COM3 0V LCD driver output when all LCD V LCD segment corresponding to COM1, V LCD 1, VLCD 2 COM2, and COM3 are off 0V V LCD LCD driver output when only LCD segments V LCD 1, VLCD 2 corresponding to COM1 are on 0V V LCD LCD driver output when only LCD segments V LCD 1, VLCD 2 corresponding to COM2 are on. 0V V LCD LCD driver output when only LCD segments V LCD 1, VLCD 2 corresponding to COM1 and COM2 are on. 0V V LCD LCD driver output when only LCD segments V LCD 1, VLCD 2 corresponding to COM3 are on. 0V V LCD LCD driver output when LCD segments V LCD 1, VLCD 2 corresponding to COM1 and COM3 are on 0V V LCD LCD driver output when LCD segments V LCD 1, VLCD 2 corresponding to COM2 and COM3 are on 0V V LCD LCD driver output when LCD segments V LCD 1, VLCD 2 corresponding to COM1, COM2 and COM3 are on 0V Figure 29. LCD Waveform (Line Inversion, 1/3 DUTY, 1/2 BIAS) (Note29) (Note29) COM4 function is same as COM1 at 1/3 duty. www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 51/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M 7. Line Inversion 1/1-Duty [Static] Drive Scheme fo[Hz] V LCD COM1 0V V LCD LCD driver output w hen all LCD segments corresponding to COM1 are off 0V V LCD LCD driver output w hen all LCD segments corresponding to COM1 are on 0V Figure 30. LCD Waveform (Line Inversion, 1/1 DUTY) (Note30) (Note30) COM2, COM3 and COM4 function are same as COM1 at 1/1 duty. www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 52/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M 8. Frame Inversion 1/5-Duty 1/3-Bias Drive Scheme fo[Hz] V LCD V LCD1 V LCD2 COM1 0V V LCD V LCD1 V LCD2 COM2 0V V LCD V LCD1 V LCD2 COM3 0V V LCD V LCD1 V LCD2 COM4 0V V LCD V LCD1 V LCD2 COM5 0V V LCD LCD driver output w hen all LCD V LCD1 segment corresponding to COM1, V LCD2 COM2, COM3, COM4 and COM5 are off 0V V LCD LCD driver output w hen only LCD segments V LCD1 corresponding to COM1 are on V LCD2 0V V LCD LCD driver output w hen only LCD segments V LCD1 corresponding to COM2 are on. V LCD2 0V V LCD LCD driver output w hen only LCD segments V LCD1 corresponding to COM1 and COM2 are on. V LCD2 0V V LCD LCD driver output w hen only LCD segments V LCD1 corresponding to COM3 are on. V LCD2 0V V LCD LCD driver output w hen LCD segments V LCD1 corresponding to COM1 and COM3 are on V LCD2 0V V LCD LCD driver output w hen LCD segments V LCD1 corresponding to COM2 and COM3 are on V LCD2 0V V LCD LCD driver output w hen LCD segments V LCD1 corresponding to COM1, COM2 and COM3 are on V LCD2 0V V LCD LCD driver output w hen only LCD segments V LCD1 corresponding to COM4 are on. V LCD2 0V V LCD LCD driver output w hen only LCD segments V LCD1 corresponding to COM2 and COM4 are on. V LCD2 0V V LCD LCD driver output w hen LCD segments V LCD1 corresponding to COM1, COM2, COM3 V LCD2 and COM4 are on 0V V LCD LCD driver output w hen LCD segments V LCD1 corresponding to COM1, COM2, COM3, V LCD2 COM4 and COM5 are on 0V Figure 31. LCD Waveform (Frame Inversion, 1/5 DUTY, 1/3BIAS) www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 53/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M 9. Frame Inversion 1/5-Duty 1/2-Bias Drive Scheme fo[Hz] V LCD V LCD1, V LCD2 COM1 0V V LCD V LCD1, V LCD2 COM2 0V V LCD V LCD1, V LCD2 COM3 0V V LCD V LCD1, V LCD2 COM4 0V V LCD V LCD1, V LCD2 COM5 0V LCD driver output w hen all LCD V LCD segment corresponding to COM1, V LCD1, V LCD2 COM2, COM3, COM4 and COM5 are off 0V V LCD LCD driver output w hen only LCD segments V LCD1, V LCD2 corresponding to COM1 are on 0V V LCD LCD driver output w hen only LCD segments V LCD1, V LCD2 corresponding to COM2 are on. 0V V LCD LCD driver output w hen only LCD segments V LCD1, V LCD2 corresponding to COM1 and COM2 are on. 0V V LCD LCD driver output w hen only LCD segments V LCD1, V LCD2 corresponding to COM3 are on. 0V V LCD LCD driver output w hen LCD segments V LCD1, V LCD2 corresponding to COM1 and COM3 are on 0V V LCD LCD driver output w hen LCD segments V LCD1, V LCD2 corresponding to COM2 and COM3 are on 0V V LCD LCD driver output w hen LCD segments V LCD1, V LCD2 corresponding to COM1, COM2 and COM3 are on 0V V LCD LCD driver output w hen LCD segments V LCD1, V LCD2 corresponding to COM4 are on 0V V LCD LCD driver output w hen LCD segments V LCD1, V LCD2 corresponding to COM2 and COM4 are on 0V V LCD LCD driver output w hen LCD segments V LCD1, V LCD2 corresponding to COM1, COM2, COM3 0V and COM4 are on V LCD V LCD1, V LCD2 0V LCD driver output w hen LCD segments corresponding to COM1, COM2, COM3, COM4 and COM5 are on Figure 32. LCD Waveform (Frame Inversion, 1/5 DUTY, 1/2BIAS) www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 54/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M 10. Frame Inversion 1/4-Duty 1/3-Bias Drive Scheme fo[Hz] V LCD V LCD1 V LCD2 COM1 0V V LCD V LCD1 V LCD2 COM2 0V V LCD V LCD1 V LCD2 COM3 0V V LCD V LCD1 V LCD2 COM4 0V V LCD LCD driver output w hen all LCD V LCD1 segment corresponding to COM1, V LCD2 COM2, COM3 and COM4 are off 0V V LCD LCD driver output w hen only LCD segments V LCD1 corresponding to COM1 are on V LCD2 0V V LCD LCD driver output w hen only LCD segments V LCD1 corresponding to COM2 are on. V LCD2 0V V LCD LCD driver output w hen only LCD segments V LCD1 corresponding to COM1 and COM2 are on. V LCD2 0V V LCD LCD driver output w hen only LCD segments V LCD1 corresponding to COM3 are on. V LCD2 0V V LCD LCD driver output w hen LCD segments V LCD1 corresponding to COM1 and COM3 are on V LCD2 0V V LCD LCD driver output w hen LCD segments V LCD1 corresponding to COM2 and COM3 are on V LCD2 0V V LCD LCD driver output w hen LCD segments V LCD1 corresponding to COM1, COM2 and COM3 are on V LCD2 0V Figure 33. LCD Waveform (Frame Inversion, 1/4 DUTY, 1/3BIAS) www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 55/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M 11. Frame Inversion 1/4-Duty 1/2-Bias Drive Scheme fo[Hz] V LCD V LCD1, V LCD2 COM1 0V V LCD V LCD1, V LCD2 COM2 0V V LCD V LCD1, V LCD2 COM3 0V V LCD V LCD1, V LCD2 COM4 0V LCD driver output w hen all LCD V LCD segment corresponding to COM1, V LCD1, V LCD2 COM2, COM3 and COM4 are off 0V V LCD LCD driver output w hen only LCD segments V LCD1, V LCD2 corresponding to COM1 are on 0V V LCD LCD driver output w hen only LCD segments V LCD1, V LCD2 corresponding to COM2 are on. 0V V LCD LCD driver output w hen only LCD segments V LCD1, V LCD2 corresponding to COM1 and COM2 are on. 0V V LCD LCD driver output w hen only LCD segments V LCD1, V LCD2 corresponding to COM3 are on. 0V V LCD LCD driver output w hen LCD segments V LCD1, V LCD2 corresponding to COM1 and COM3 are on 0V V LCD LCD driver output w hen LCD segments V LCD1, V LCD2 corresponding to COM2 and COM3 are on 0V V LCD LCD driver output w hen LCD segments V LCD1, V LCD2 corresponding to COM1, COM2 and COM3 are on 0V V LCD LCD driver output w hen LCD segments V LCD1, V LCD2 corresponding to COM4 are on 0V V LCD LCD driver output w hen LCD segments V LCD1, V LCD2 corresponding to COM2 and COM4 are on 0V V LCD LCD driver output w hen LCD segments V LCD1, V LCD2 corresponding to COM1, COM2, COM3 0V and COM4 are on Figure 34. LCD Waveform (Frame Inversion, 1/4 DUTY, 1/2BIAS) www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 56/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M 12. Frame Inversion 1/3-Duty 1/3-Bias Drive Scheme fo[Hz] V LCD V LCD1 V LCD2 COM1 0V V LCD V LCD1 V LCD2 COM2 0V V LCD V LCD1 V LCD2 COM3 0V V LCD LCD driver output w hen all LCD V LCD1 segment corresponding to COM1, V LCD2 COM2, and COM3 are off 0V V LCD LCD driver output w hen only LCD segments V LCD1 corresponding to COM1 are on V LCD2 0V V LCD LCD driver output w hen only LCD segments V LCD1 corresponding to COM2 are on. V LCD2 0V V LCD LCD driver output w hen only LCD segments V LCD1 corresponding to COM1 and COM2 are on. V LCD2 0V V LCD LCD driver output w hen only LCD segments V LCD1 corresponding to COM3 are on. V LCD2 0V V LCD LCD driver output w hen LCD segments V LCD1 corresponding to COM1 and COM3 are on V LCD2 0V V LCD LCD driver output w hen LCD segments V LCD1 corresponding to COM2 and COM3 are on V LCD2 0V V LCD LCD driver output w hen LCD segments V LCD1 corresponding to COM1, COM2 and COM3 are on V LCD2 0V Figure 35. LCD Waveform (Frame Inversion, 1/3 DUTY, 1/3BIAS) (Note31) (Note31) COM4 function is same as COM1 at 1/3 duty. www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 57/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M 13. Frame Inversion 1/3-Duty 1/2-Bias Drive Scheme fo[Hz] V LCD V LCD1, V LCD2 COM1 0V V LCD V LCD1, V LCD2 COM2 0V V LCD V LCD1, V LCD2 COM3 0V LCD driver output w hen all LCD V LCD segment corresponding to COM1, V LCD1, V LCD2 COM2, and COM3 are off 0V V LCD LCD driver output w hen only LCD segments V LCD1, V LCD2 corresponding to COM1 are on 0V V LCD LCD driver output w hen only LCD segments V LCD1, V LCD2 corresponding to COM2 are on. 0V V LCD LCD driver output w hen only LCD segments V LCD1, V LCD2 corresponding to COM1 and COM2 are on. 0V V LCD LCD driver output w hen only LCD segments V LCD1, V LCD2 corresponding to COM3 are on. 0V V LCD LCD driver output w hen LCD segments V LCD1, V LCD2 corresponding to COM1 and COM3 are on 0V V LCD LCD driver output w hen LCD segments V LCD1, V LCD2 corresponding to COM2 and COM3 are on 0V V LCD LCD driver output w hen LCD segments V LCD1, V LCD2 corresponding to COM1, COM2 and COM3 are on 0V Figure 36. LCD Waveform (Frame Inversion, 1/3 DUTY, 1/2 BIAS) (Note32) (Note32) COM4 function is same as COM1 at 1/3 duty. www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 58/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M 14. Frame Inversion 1/1-Duty [Static] Drive Scheme) fo[Hz] V LCD COM1 0V V LCD LCD driver output w hen all LCD segments corresponding to COM1 are off 0V V LCD LCD driver output w hen all LCD segments corresponding to COM1 are on 0V Figure 37. LCD Waveform (Frame Inversion, 1/1 DUTY) (Note33) (Note33) COM2, COM3 and COM4 function are same as COM1 at 1/1 duty. www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 59/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M Oscillation Stabilization Time of the Internal Oscillation Circuit It must be noted that the oscillation of the internal oscillation circuit is unstable for a maximum of 100μs (oscillation stabilization time) after oscillation has started. Internal oscillation circuit Oscillation stopped Oscillation stabilization time (100 [us] max.) Oscillation operation (under normal conditions) 1.If the INHb pin status is switched from "L" to "H" when control data OC = "0" and BU0～ ="0" 2.If the contorol data BU is set from "1" to "0" when INHb = "H" and contorol data OC ="0" *Oscillation starts when control data OC = "0" and BU0~BU1= "000" Figure 38. Oscillation Stabilization Time www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 60/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M Voltage Detection Type Reset Circuit (VDET) The Voltage Detection Type Reset Circuit generates an output signal that resets the system when power is applied for the first time and when the power supply voltage drops (that is, for example, the power supply voltage is less than or equal to the power down detection voltage (VDET = 1.8V typ.). To ensure that this reset function works properly, it is recommended that a capacitor be connected to the power supply line so that both the power supply voltage (VDD) rise time when power is first applied and the power supply voltage (VDD) fall time when the voltage drops are at least 1ms. t1 VDD t2 VDD min VDD min t3 VDD = 1.0V Figure 39. VDET Detection Timing Power supply voltage VDD fall time: t1 > 1ms Power supply voltage VDD rise time: t2 > 1ms Internal reset power supply retain time: t3 > 1ms Reset Condition When BU97540KV-M is initialized, the internal status after power supply has been reset as the following table. Instruction Key Scan Mode S1/P1/G1 to S9/P9/G9 Pin Inversion Mode LCD Bias LCD Duty DISPLAY Frequency Display Clock Mode LCD Display Power Mode PWM/GPO Output PWM Frequency PWM Duty Display Contrast Setting www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 Control Data Reset Condition At Reset Condition [KM0,KM1,KM2]=[1,1,1]:Keyscan no use [P0,P1,P2,P3]=[0,0,0,0]:all segment output FL=0:Line Inversion DR=0:1/3 bias [DT0,DT1]=[0,1]:1/4 duty [FC0,FC1,FC2,FC3]=[0,0,0,0]:fosc/12288 OC=0:Internal oscillator SC=1:OFF [BU0, BU1, BU2]=[1,1,1]:Power saving mode PGx=0:PWM output(x=1～9) [PF0,PF1,PF2,PF3]=[0,0,0,0]: fosc /4096 [Wn0～Wn8]=[0,0,0,0,0,0,0,0,0]:0/256)xTp (n=1～9,Tp=1/fp) [CT0,CT1,CT2,CT3]=[0,0,0,0]:VLCD Level is 1.00*VDD 61/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M Operational Notes 1. Reverse Connection of Power Supply Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when connecting the power supply, such as mounting an external diode between the power supply and the IC’s power supply pins. 2. Power Supply Lines Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and aging on the capacitance value when using electrolytic capacitors. 3. Ground Voltage Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition. 4. Ground Wiring Pattern When using both small-signal and large-current ground traces, the two ground traces should be routed separately but connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal ground caused by large currents. Also ensure that the ground traces of external components do not cause variations on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance. 5. Thermal Consideration Should by any chance the power dissipation rating be exceeded the rise in temperature of the chip may result in deterioration of the properties of the chip. The absolute maximum rating of the Pd stated in this specification is when the IC is mounted on a 70mm x 70mm x 1.6mm glass epoxy board. In case of exceeding this absolute maximum rating, increase the board size and copper area to prevent exceeding the Pd rating. 6. Recommended Operating Conditions These conditions represent a range within which the expected characteristics of the IC can be approximately obtained. The electrical characteristics are guaranteed under the conditions of each parameter. 7. Inrush Current When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and routing of connections. 8. Operation Under Strong Electromagnetic Field Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction. 9. Testing on Application Boards When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply should always be turned off completely before connecting or removing it from the test setup during the inspection process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during transport and storage. 10. Inter-pin Short and Mounting Errors Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin. Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and unintentional solder bridge deposited in between pins during assembly to name a few. www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 62/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M Operational Notes – continued 11. Unused Input Pins Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the power supply or ground line. 12. Regarding the Input Pin of the IC In the construction of this IC, P-N junctions are inevitably formed creating parasitic diodes or transistors. The operation of these parasitic elements can result in mutual interference among circuits, operational faults, or physical damage. Therefore, conditions which cause these parasitic elements to operate, such as applying a voltage to an input pin lower than the ground voltage should be avoided. Furthermore, do not apply a voltage to the input pins when no power supply voltage is applied to the IC. Even if the power supply voltage is applied, make sure that the input pins have voltages within the values specified in the electrical characteristics of this IC. 13. Data transmission To refrain from data transmission is strongly recommended while power supply is rising up or falling down to prevent from the occurrence of disturbances on transmission and reception. www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 63/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M Ordering Information B U 9 7 5 4 0 Part Number K V Package KV : VQFP80 - ME2 Product Rank M: for Automotive Packaging Specification E2: Embossed tape and reel (VQFP80) Marking Diagram VQFP80 (TOP VIEW) Part Number Marking Lot Number Marking BU97540KV 1PIN MARK www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 64/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M Physical Dimension, Tape and Reel Information VQFP80 Package Name 1PIN MARK www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 65/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 BU97540KV-M Revision History Date Revision 02.Jun.2015 29.Jun.2015 001 002 Changes New Release Modified Typical Application Circuit in Page2. Modified S66/TESTIN Pin description(Handling when unused) in Page 7. Modified comment of figure.39 in Page 61. www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 66/66 TSZ02201-0P4P0D300970-1-2 29.Jun.2015 Rev.002 Datasheet Notice Precaution on using ROHM Products 1. If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment (Note 1), aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific Applications. (Note1) Medical Equipment Classification of the Specific Applications JAPAN USA EU CHINA CLASSⅢ CLASSⅡb CLASSⅢ CLASSⅢ CLASSⅣ CLASSⅢ 2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which a failure or malfunction of our Products may cause. The following are examples of safety measures: [a] Installation of protection circuits or other protective devices to improve system safety [b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure 3. Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our Products under any special or extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of product performance, reliability, etc, prior to use, must be necessary: [a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents [b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust [c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2 [d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves [e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items [f] Sealing or coating our Products with resin or other coating materials [g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning residue after soldering [h] Use of the Products in places subject to dew condensation 4. The Products are not subject to radiation-proof design. 5. Please verify and confirm characteristics of the final or mounted products in using the Products. 6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied, confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect product performance and reliability. 7. De-rate Power Dissipation (Pd) depending on Ambient temperature (Ta). When used in sealed area, confirm the actual ambient temperature. 8. Confirm that operation temperature is within the specified range described in the product specification. 9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in this document. Precaution for Mounting / Circuit board design 1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product performance and reliability. 2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products, please consult with the ROHM representative in advance. For details, please refer to ROHM Mounting specification Notice-PAA-E © 2015 ROHM Co., Ltd. All rights reserved. Rev.001 Datasheet Precautions Regarding Application Examples and External Circuits 1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the characteristics of the Products and external components, including transient characteristics, as well as static characteristics. 2. You agree that application notes, reference designs, and associated data and information contained in this document are presented only as guidance for Products use. Therefore, in case you use such information, you are solely responsible for it and you must exercise your own independent verification and judgment in the use of such information contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of such information. Precaution for Electrostatic This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron, isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control). Precaution for Storage / Transportation 1. Product performance and soldered connections may deteriorate if the Products are stored in the places where: [a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2 [b] the temperature or humidity exceeds those recommended by ROHM [c] the Products are exposed to direct sunshine or condensation [d] the Products are exposed to high Electrostatic 2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is exceeding the recommended storage time period. 3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads may occur due to excessive stress applied when dropping of a carton. 4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of which storage time is exceeding the recommended storage time period. Precaution for Product Label QR code printed on ROHM Products label is for ROHM’s internal use only. Precaution for Disposition When disposing Products please dispose them properly using an authorized industry waste company. Precaution for Foreign Exchange and Foreign Trade act Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign trade act, please consult with ROHM in case of export. Precaution Regarding Intellectual Property Rights 1. All information and data including but not limited to application example contained in this document is for reference only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any other rights of any third party regarding such information or data. 2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the Products with other articles such as components, circuits, systems or external equipment (including software). 3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to manufacture or sell products containing the Products, subject to the terms and conditions herein. Other Precaution 1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM. 2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written consent of ROHM. 3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the Products or this document for any military purposes, including but not limited to, the development of mass-destruction weapons. 4. The proper names of companies or products described in this document are trademarks or registered trademarks of ROHM, its affiliated companies or third parties. Notice-PAA-E © 2015 ROHM Co., Ltd. All rights reserved. Rev.001 Datasheet General Precaution 1. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents. ROHM shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny ROHM’s Products against warning, caution or note contained in this document. 2. All information contained in this docume nt is current as of the issuing date and subj ect to change without any prior notice. Before purchasing or using ROHM’s Products, please confirm the la test information with a ROHM sale s representative. 3. The information contained in this doc ument is provi ded on an “as is” basis and ROHM does not warrant that all information contained in this document is accurate an d/or error-free. ROHM shall not be in an y way responsible or liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccur acy or errors of or concerning such information. Notice – WE © 2015 ROHM Co., Ltd. All rights reserved. Rev.001

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