BU97550KV-ME2

Datasheet LCD Segment Drivers Multi-function LCD Segment Drivers BU97550KV-M MAX 528 Segment(66SEG x 8COM) General Description Key Specifications ■ ■ ■ ■ The BU97550KV-M is 1/8, 1/7, 1/5, 1/4, 1/3, or Static general-purpose LCD driver. The BU97550KV-M can drive up to 528 LCD Segments directly. The BU97550KV-M can also control up to 9 General-Purpose/PWM output ports. These products also incorporate a key scan circuit that accepts input from up to 30 keys to reduce printed circuit board wiring ■ ■ Features Supply Voltage Range: +2.7V to +6.0V Operating Temperature Range: -40°C to +85°C Max Segments: 528 Segments Display Duty Static, 1/3, 1/4, 1/5, 1/7, 1/8 Selectable Bias: 1/2, 1/3, 1/4 Selectable Interface: 3wire Serial Interface Applications  AEC-Q100 Qualified (Note)  Key Input Function for Up to 30 Keys (A key scan is performed only when a key is pressed.)  Either 1/8, 1/7, 1/5, 1/4, 1/3 or Static Can be Selected with The Serial Control Data. 1/8 duty drive: Up to 528 Segments can be driven 1/7 duty drive: Up to 469 Segments can be driven 1/5 duty drive: Up to 345 Segments can be driven 1/4 duty drive: Up to 280 Segments can be driven 1/3 duty drive: Up to 210 Segments can be driven Static drive: Up to 70 Segments can be driven  Serial Data Control of Frame Frequency for Common and Segment output Waveforms.  Serial Data Control of Switching Between The Segment output Port, PWM output Port and General-Purpose output Port Functions.(Max 9 ports)  Built-in Oscillation circuit  Integrated Voltage Detected Type Power on Reset(VDET) circuit  No External Component  Low Power Consumption Design  Supports Line and Frame Inversion  Car Audio, Home Electrical Appliance, Meter Equipment etc. Package W (Typ) x D (Typ) x H (Max) VQFP80 14.00mm x 14.00mm x 1.60mm (Note) Grade 3 Typical Application Circuit Key Matrix P1/G1 P9/G9 KS1 / S53 KI1 / S59 KS6 / S58 KI5 / S63 (General Purpose/PWM Ports) (For control of backlight) COM1 COM2 COM3 COM4 COM5/S67 VDD +5V COM6/S66 COM7/S65 COM8/S64 (Note2) From Control SCE SCL SDI S1/P1/G1 LCD Panel (Up to 528 Segments) S9/P9/G9 To Control SDO S10 S52 S68 S69 (Note2) Insert capacitors between VDD and VSS C≥0.1µF OSC_IN/S70 Figure 1. Typical Application Circuit 〇Product structure : Silicon monolithic integrated circuit www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 14 • 001 〇This product is not designed protection against radioactive rays. 1/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) COMMON Driver S1/P1/G1 S10 ・・・ SEGMENT Driver/Latch Clock /Timing Generator OSC_IN / S70 ・・・ S9/P9/G9 S65/COM8 S65/COM7 S66/COM6 S67/COM5 COM4 COM3 COM2 COM1 Block Diagram Control Register PWM Register SCE Shift Register SCL Serial Interface LCD voltage Generator SDI SDO KEY BUFFER VLCD VDD VLCD1 VDET VLCD2 KEY SCAN VLCD3 VSS KS1/ S53 KS2/ S54 KS3/ S55 KS4/ S56 KS6/ S58 KS5/ S57 KI1 / S59 KI2 / S60 KI3 / S61 KI4 / S62 KI5 / S63 VSS Figure 2. Block Diagram S43 41 S44 S45 S46 S47 S48 S49 S50 S51 S52 KS1 / S53 KS2 / S54 KS3 / S55 KS4 / S56 KS5 / S57 KS6 / S58 KI1 / S59 KI2 / S60 KI3 / S61 60 KI4 / S62 Pin Arrangement 61 40 KI5 / S63 S42 COM8 / S64 S41 COM7 / S65 S40 COM6 / S66 S39 COM5 / S67 S38 COM4 S37 COM3 S36 COM2 S35 COM1 S34 VDD S33 VSS S32 S68 S31 SDO S30 S69 S29 OSC_IN / S70 S28 SCE S27 SCL S26 SDI S25 S1 / P1 / G1 S24 S2 / P2 / G2 S23 21 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 / P9 / G9 S8 / P8 / G8 S7 / P7 / G7 S6 / P6 / G6 S5 / P5 / G5 S4 / P4 / G4 S3 / P3 / G3 80 Figure 3. Pin Configuration (TOP VIEW) www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 2/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Absolute Maximum Ratings (VSS = 0V) Parameter Maximum Supply Voltage Input Voltage Symbol VDD VIN1 VIN2 Pd Topr Tstg Allowable Loss Operating Temperature Storage Temperature Pin Rating -0.3 to +7.0 -0.3 to +7.0 -0.3 to +7.0 1.2 (Note3) -40 to +85 -55 to +125 VDD SCE, SCL, SDI KI1 to KI5 Unit V V V W °C °C (Note3) When use more than Ta=25°C, subtract 12mW per degree. (Using ROHM standard board) (Board size: 70mm×70mm×1.6mm material: FR4 board copper foil: land pattern only) Caution: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated over the absolute maximum ratings. Recommend Operating Conditions (Ta = -40°C to +85°C, VSS = 0V) Parameter Symbol Supply Voltage Conditions VDD Min 2.7 Rating Typ 5.0 Max 6.0 Limit Typ 0.03 VDD 0.1 VDD Max - Unit V Electrical Characteristics (Ta = -40 to +85°C, VDD = 2.7V to 6.0V, VSS = 0V) Parameter Hysteresis Power-on Detection Voltage “H” Level Input Voltage “L” Level Input Voltage Input Floating Voltage Pull-down Resistance Output Off Leakage Current “H” Level Input Current “L” Level Input Current “H” Level Output Voltage “L” Level Output Voltage Middle Level Output Voltage Symbol Pin Conditions Unit VH1 VH2 SCE, SCL, SDI KI1 to KI5 Min - VDET VDD 1.3 1.8 2.2 V VIH1 VIH2 VIH3 VIL1 4.5V ≤ VDD ≤ 6.0V 2.7V ≤ VDD < 4.5V 0.4VDD 0.8VDD 0.7VDD - VDD VDD VDD V 0 - 0.2VDD V VIF RPD SCE, SCL, SDI SCE, SCL, SDI KI1 to KI5 SCE, SCL, SDI KI1 to KI5 KI1 to KI5 KI1 to KI5 50 100 0.05VDD 250 V kΩ IOFFH SDO VO=6.0V - - 6.0 µA IIH1 IIL1 VOH1 SCE, SCL, SDI SCE, SCL, SDI S1 to S70 -5.0 - 5.0 - µA µA VDD-0.9 - - VOH2 COM1 to COM8 VDD-0.9 - - VOH3 VOH4 VOL1 VOL2 VOL3 VOL4 VOL5 VMID1 P1/G1 to P9/G9 KS1 to KS6 S1 to S70 COM1 to COM8 P1/G1 to P9/G9 KS1 to KS6 SDO S1 to S70 COM1 to COM8 VMID3 S1 to S70 VMID4 S1 to S70 VMID5 COM1 to COM8 VMID6 COM1 to COM8 VMID7 S1 to S70 VMID8 COM1 to COM8 VMID9 COM1 to COM8 VDD-0.9 VDD-1.0 0.2 1/2 VDD -0.9 1/2 VDD -0.9 2/3 VDD -0.9 1/3 VDD -0.9 2/3 VDD -0.9 1/3 VDD -0.9 1/2 VDD -0.9 3/4 VDD -0.9 1/4 VDD -0.9 VDD-0.5 0.5 0.1 VMID2 VI = 5.5V VI = 0V IO = -20µA, VLCD=1.00*VDD IO = -100µA, VDD=1.00*VDD IO = -1mA IO = -500µA IO = 20µA IO = 100µA IO = 1mA IO = 25µA IO = 1mA 1/2 bias IO = ±20µA VLCD=1.00*VDD 1/2 bias IO = ±100µA VLCD=1.00*VDD 1/3 bias IO = ±20µA VLCD=1.00*VDD 1/3 bias IO = ±20µA VLCD=1.00*VDD 1/3 bias IO = ±100µA VLCD=1.00*VDD 1/3 bias IO = ±100µA VLCD=1.00*VDD 1/4 bias IO = ±20µA VLCD=1.00*VDD 1/4 bias IO = ±100µA VLCD=1.00*VDD 1/4 bias IO = ±100µA VLCD=1.00*VDD VDD-0.2 0.9 0.9 0.9 1.5 0.5 1/2 VDD +0.9 1/2 VDD +0.9 2/3 VDD +0.9 1/3 VDD +0.9 2/3 VDD +0.9 1/3 VDD +0.9 1/2 VDD +0.9 3/4 VDD +0.9 1/4 VDD +0.9 www.rohm.com © 2015 ROHM Co., Ltd. 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TSZ22111 • 15 • 001 VDD=5.0V 3/72 - V V V V TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Electrical Characteristics – continued Parameter Current Consumption Symbol IDD1 IDD2 Pin Conditions VDD VDD IDD3 Power-saving mode VDD = 5.0V Output open, 1/2 bias Frame frequency=80Hz VLCD=1.00*VDD VDD = 5.0V Output open,1/3 bias Frame frequency=80Hz VLCD=1.00*VDD VDD = 5.0V Output open,1/4 bias Frame frequency=80Hz VLCD=1.00*VDD VDD IDD4 VDD Min - Limit Typ - Max 15 - 105 220 - 130 270 - 160 330 Min 300 540 562 Limit Typ 600 625 Max 720 660 688 30 - 1000 kHz 30 160 160 50 70 ns ns % Unit µA Oscillation Characteristics (Ta = -40 to +85°C, VDD = 2.7V to 6.0V, VSS = 0.0V) Parameter scillator Frequency 1 Oscillator Frequency 2 Oscillator Frequency 3 External Clock Frequency(Note4) External Clock Rise Time External Clock Fall Time External Clock Duty Symbol Pin Conditions fOSC1 fOSC2 fOSC3 - VDD = 2.7V to 6.0V VDD = 5.0V VDD = 6.0V OSC_IN/S70 External clock mode (OC=1) fOSC4 tr tf tDTY Unit kHz kHz kHz (Note4) Frame frequency is decided external frequency and dividing ratio of FC0 to FC3 setting. [Reference Data] 700 650 VDD = 6.0V fosc[kHz] 600 VDD = 5.0V VDD = 3.3V 550 VDD = 2.7V 500 450 400 350 300 -40 -20 0 20 40 60 80 Temperature[°C] Figure 4. Frame Frequency Typical Temperature Characteristics www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 4/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) MPU Interface Characteristics (Ta=-40 to +85°C, VDD = 2.7V to 6.0V, VSS=0V) Parameter Symbol Data Setup Time Data Hold Time SCE Wait Time SCE Setup Time SCE Hold Time Clock Cycle Time High-level Clock Pulse Width Low-level Clock Pulse Width (Write) Low-level Clock Pulse Width (Read) Rise Time Fall Time SDO Output Delay Time Pin tDS tDH tCP tCS tCH tCCYC tCHW SCL, SDI SCL, SDI SCE, SCL SCE, SCL SCE, SCL SCL SCL tCLWW SCL tCLWR SCL tr tf SDO Rise Time Conditions RPU=4.7kΩ CL=10pF(Note5) SCE, SCL, SDI SCE, SCL, SDI tDC SDO tDR SDO RPU=4.7kΩ CL=10pF(Note5) RPU=4.7kΩ CL=10pF(Note5) Min 120 120 120 120 120 320 Limit Typ - Max - 120 - - ns 120 - - ns 1.6 - - µs - 160 160 - ns ns - - 1.5 µs - - 1.5 µs Unit ns ns ns ns ns ns (Note5) Since SDO is an open-drain output, ”tDC” and “tDR” depend on the resistance of the pull-up resistor RPU and the load capacitance CL. RPU: 1kΩ≤RPU≤10kΩ is recommended. CL: A parasitic capacitance in an application circuit. Any component is not necessary to be attached. Power supply for I/O level RPU SDO Host CL 1. When SCL is stopped at the low level VIH1, VIH1 SCE VIL1 tCCYC tCHW SCL tCLWR tCLWW VIH1, VIH2 VIL1 tr SDI tf tCS tCH VIH1, VIH2 VIL1 tDS tDH SDO VOL5 tDC tDR 2. When SCL is stopped at the high level VIH1, VIH2 SCE VIL1 tCCYC tCHW tCLWW SCL tCLWR VIH1, VIH2 VIL1 SDI tCH tCP tr tf VIH1, VIH2 VIL1 tDS tDH SDO VOL5 tDC tDR Figure 5. Serial Interface Timing www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 5/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Pin Description Symbol Pin No. Function Active I/O S1/P1/G1 to S9/P9/G9 79,80, 1 to 7 - O S10 to S52 S68, S69 KS1/S53 to KS6/S58 8 to 50 72, 74 51 to 56 - O OPEN - O OPEN KI1/S59 to KI5/S63 57 to 61 - I/O OPEN COM1 to COM4 COM5/S67 COM6/S66 COM7/S65 COM8/S64 OSC_IN/S70 66 to 69 65 64 63 62 75 Segment output for displaying the display data transferred by serial data input. The S1/P1/G1 to S9/P9/G9 pins can also be used as General-Purpose or PWM output when so set up by the control data. Segment output for displaying the display data transferred by serial data input. Key scan outputs Although normal key scan timing lines require diodes to be inserted in the timing lines to prevent shorts, since these outputs are unbalanced CMOS transistor outputs, these outputs will not be damaged by shorting when these outputs are used to form a key matrix. The KS1/S53 to KS6/S58 pins can be used as Segment outputs when so specified by the control data. Key scan inputs These pins have built-in pull-down resistors. The KI1/S59 to KI5/S63 pins can be used as Segment outputs when so specified by the control data. Common driver output pins. The frame frequency is fo[Hz]. Common / Segment output for LCD driving Assigned as Common output in 1/8, 1/7 and 1/5 Duty modes and Segment output in Static, 1/3 and 1/4 Duty modes. Handling when unused OPEN - O O OPEN OPEN - I/O OPEN SCE SCL SDI SDO VDD 76 77 78 73 70 H ↑ - I I I O - OPEN - VSS 71 Segment output for displaying the display data transferred by serial data input. The OSC_IN/S70 pin can be used as external frequency input pin when set up by the control data. Serial data transfer inputs. Must be connected to the controller. SCE: Chip enable SCL: Synchronization clock SDI: Transfer data Output data Power supply pin of the IC A power voltage of 2.7V to 6.0V must be applied to this pin. Power supply pin. Must be connected to ground. - - - www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 6/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) IO Equivalent Circuit VDD VDD SCE/SDI/SCL VSS VSS VDD VDD S10 to S52, S68, S69, COM1 to COM4 OSC_IN/S70 VSS VSS VDD VDD COM5/S67 to COM8/S64 S1/P1/G1 to S9/P9/G9, KS1/S53 to KS6/S58 VSS VSS VDD VDD KI1/S59 to KI5/S63 SDO VSS VSS Figure 6. I/O Equivalent Circuit www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 7/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Serial Data Transfer Formats 1. 1/8 Duty (1) When SCL is stopped at the low level SCE SCL SDI 1 0 0 1 0 0 1 0 D1 D2 D3 D4 D5 D6 D7 D8 Device Address 8 bits --- D90 D91 D92 D93 D94 D95 D96 0 --- 0 DR0 DR1 DT0 DT1 DT2 KM0 KM1 KM2 P0 Display Data 96 bits P1 P2 P3 FL FC0 FC1 FC2 FC3 OC SC BU0 BU1 BU2 0 0 0 DD 3 bits Control Data 53 bits SCE SCL SDI 1 0 0 1 0 0 1 0 D97 D98 D99 D100 D101 D102 D103 D104 Device Address 8 bits --- D186 D187 D188 D189 D190 D191 D192 0 0 --- 0 0 0 0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PG8 PG9 0 PF0 PF1 PF2 PF3 CT0 CT1 CT2 CT3 0 Control Data 53 bits Display Data 96 bits 0 1 DD 3 bits SCE SCL SDI 1 0 0 1 0 0 1 0 D193 D194 D195 D196 D197 D198 D200 D201 Device Address 8 bits --- D282 D283 D284 D285 D286 D287 D288 0 0 --- 0 0 WN10 WN11 --- WN17 WN18 WN20 WN21 --- WN27 WN28 WN30 WN31 --- WN37 WN38 WN40 WN41 --- WN47 WN48 0 Control Data 53 bits Display Data 96 bits 1 0 DD 3 bits SCE SCL SDI 1 0 0 1 0 0 1 0 D289 D290 D291 D292 D293 D294 D295 D296 Device Address 8 bits --- D378 D379 D380 D381 D382 D383 D384 0 0 --- 0 0 WN50 WN51 --- WN57 WN58 WN60 WN61 Display Data 96 bits --- WN77 WN78 WN80 WN81 --- WN87 WN88 WN90 WN91 --- WN97 WN98 0 1 1 DD 3 bits Control Data 53 bits SCE SCL SDI 1 0 0 1 0 0 1 0 D385 D386 D387 D388 D389 D390 D391 D392 --- D474 D475 D476 D477 D478 D479 D480 0 0 --- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Control Data 53 bits Display Data 96 bits Device Address 8 bits 0 0 DD 3 bits SCE SCL SDI 1 0 0 1 0 0 1 0 D481 D482 D483 D484 D485 D486 --- Device Address 8 bits D523 D524 D525 D526 D527 D528 0 --- 0 0 0 --- 0 0 0 0 0 0 0 Display Data 96 bits 0 0 0 0 0 Control Data 149 bits 0 0 0 0 0 0 0 0 0 0 1 0 1 DD 3 bits (Note6) Figure 7. 3-SPI Data Transfer Format (Note6) DD is direction data. www.rohm.com © 2015 ROHM Co., Ltd. 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TSZ22111 • 15 • 001 8/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Serial Data Transfer Formats – continued (2) When SCL is stopped at the high level SCE SCL SDI 1 0 0 1 0 0 1 0 D1 D2 D3 D4 D5 D6 D7 D8 Device Address 8 bits --- D90 D91 D92 D93 D94 D95 D96 0 --- 0 DR0 DR1 DT0 DT1 DT2 KM0 KM1 KM2 P0 Display Data 96 bits P1 P2 P3 FL FC0 FC1 FC2 FC3 OC SC BU0 BU1 BU2 0 0 0 DD 3 bits Control Data 53 bits SCE SCL SDI 1 0 0 1 0 0 1 0 D97 D98 D99 D100 D101 D102 D103 D104 Device Address 8 bits --- D186 D187 D188 D189 D190 D191 D192 0 0 --- 0 0 0 0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PG8 PG9 0 PF0 PF1 PF2 PF3 CT0 CT1 CT2 CT3 0 Control Data 53 bits Display Data 96 bits 0 1 DD 3 bits SCE SCL SDI 1 0 0 1 0 0 1 0 D193 D194 D195 D196 D197 D198 D200 D201 Device Address 8 bits --- D282 D283 D284 D285 D286 D287 D288 0 0 --- 0 0 WN10 WN11 --- WN17 WN18 WN20 WN21 --- WN27 WN28 WN30 WN31 --- WN37 WN38 WN40 WN41 --- WN47 WN48 0 Control Data 53 bits Display Data 96 bits 1 0 DD 3 bits SCE SCL SDI 1 0 0 1 0 0 1 0 D289 D290 D291 D292 D293 D294 D295 D296 Device Address 8 bits --- D378 D379 D380 D381 D382 D383 D384 0 0 --- 0 0 WN50 WN51 --- WN57 WN58 WN60 WN61 Display Data 96 bits --- WN77 WN78 WN80 WN81 --- WN87 WN88 WN90 WN91 --- WN97 WN98 0 1 1 DD 3 bits Control Data 53 bits SCE SCL SDI 1 0 0 1 0 0 1 0 D385 D386 D387 D388 D389 D390 D391 D392 --- D474 D475 D476 D477 D478 D479 D480 0 0 0 0 0 0 0 0 0 0 0 0 --- 0 0 0 0 0 0 0 0 0 0 0 0 1 Control Data 53 bits Display Data 96 bits Device Address 8 bits 0 0 DD 3 bits SCE SCL SDI 1 0 0 1 0 0 1 0 D481 D482 D483 D484 D485 D486 --- Device Address 8 bits D523 D524 D525 D526 D527 D528 0 --- 0 0 0 0 0 0 0 0 0 0 0 Display Data 96 bits 0 0 --- 0 0 0 0 0 0 0 0 0 0 0 0 Control Data 53 bits 1 0 1 DD 3 bits (Note7) Figure 8. 3-SPI Data Transfer Format (Note7) DD is direction data. Device code ································ ”49H” KM0 to KM2 ································ Key Scan output port/Segment output port switching control data D1 to D528 ·································· Display data P0 to P3 ····································· Segment/PWM/General-Purpose output port switching control data FL ············································· Line Inversion or Frame Inversion switching control data DR0 to DR1 ································· 1/4 bias driver, 1/3 bias driver or 1/2 bias driver switching control data DT0 to DT2 ································· 1/8-duty drive, 1/7-duty drive, 1/5-duty drive, 1/4-duty drive, 1/3-duty drive or Static drive switching control data FC0 to FC3 ································· Common/Segment output waveform frame frequency setting control data OC ············································ Internal oscillator operating mode/External clock operating mode switching control data SC ············································· Segment on/off control data BU0 to BU2 ································· Normal mode/Power-saving mode control data PG1 to PG9 ································· PWM/General-Purpose output port select data PF0 to PF3·································· PWM output waveform frame frequency setting control data. CT0 to CT3 ································· LCD bias voltage VLCD setting control data. W10 to W18, W20 to W28, W30 to W38,W40 to W48, W50 to W58, W60 to W68, W70 to W78, W80 to W88, W90 to W98 ········································· PWM output duty setting control data When it is coincident with device code, BU97550KV-M capture display data and control data at falling edge of SCE. So, please transfer the bit number of send display data and control data as specified number in the above figure. Specified number of bits is 160bit (Device code: 8bit, Display data and Control data: 149bit, DD: 3bit). www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 9/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Serial Data Transfer Formats – continued 2. 1/7 Duty (1) When SCL is stopped at the low level SCE SCL SDI 1 0 0 1 0 0 1 0 D1 D2 D3 D4 D5 D6 D7 D8 Device Address 8 bits --- D90 D91 D92 D93 D94 D95 D96 0 --- 0 DR0 DR1 DT0 DT1 DT2 KM0 KM1 KM2 P0 Display Data 96 bits P1 P2 P3 FL FC0 FC1 FC2 FC3 OC SC BU0 BU1 BU2 0 0 0 DD Control Data 53 bits SCE SCL SDI 1 0 0 1 0 0 1 0 D97 D98 D99 D100 D101 D102 D103 D104 Device Address 8 bits --- D186 D187 D188 D189 D190 D191 D192 0 0 --- 0 0 0 0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PG8 PG9 0 PF0 PF1 PF2 PF3 CT0 CT1 CT2 CT3 0 Control Data 53 bits Display Data 96 bits 0 1 DD SCE SCL SDI 1 0 0 1 0 0 1 0 D193 D194 D195 D196 D197 D198 D200 D201 Device Address 8 bits --- D282 D283 D284 D285 D286 D287 D288 0 0 --- 0 0 WN10 WN11 --- WN17 WN18 WN20 WN21 --- WN27 WN28 WN30 WN31 --- WN37 WN38 WN40 WN41 --- WN47 WN48 0 Control Data 53 bits Display Data 96 bits 1 0 DD SCE SCL SDI 1 0 0 1 0 0 1 0 D289 D290 D291 D292 D293 D294 D295 D296 Device Address 8 bits --- D378 D379 D380 D381 D382 D383 D384 0 0 --- 0 0 WN50 WN51 --- WN57 WN58 WN60 WN61 Display Data 96 bits --- WN77 WN78 WN80 WN81 --- WN87 WN88 WN90 WN91 --- WN97 WN98 0 1 1 DD Control Data 53 bits SCE SCL SDI 1 0 0 1 0 0 1 0 D385 D386 D387 D388 D389 D390 D391 --- D463 D465 D467 D468 D469 0 --- 0 0 0 0 0 0 0 0 0 0 0 0 0 --- 0 0 0 0 0 0 0 0 0 0 0 0 1 Control Data 149 bits Display Data 96 bits Device Address 8 bits 0 0 DD SCE SCL SDI 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 Device Address 8 bits --- 0 0 0 0 0 0 0 0 0 0 --- 0 0 0 0 0 0 0 Display Data 96 bits 0 0 --- 0 Control Data 53 bits 0 0 0 0 0 0 0 0 0 0 0 1 0 1 DD (Note8) Figure 9. 3-SPI Data Transfer Format (Note8) DD is direction data. www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 10/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Serial Data Transfer Formats – continued (2) When SCL is stopped at the high level SCE SCL SDI 1 0 0 1 0 0 1 0 D1 D2 D3 D4 D5 D6 D7 D8 Device Address 8 bits --- D90 D91 D92 D93 D94 D95 D96 0 --- 0 DR0 DR1 DT0 DT1 DT2 KM0 KM1 KM2 P0 Display Data 96 bits P1 P2 P3 FL FC0 FC1 FC2 FC3 OC SC BU0 BU1 BU2 0 0 0 DD 3 bits Control Data 53 bits SCE SCL SDI 1 0 0 1 0 0 1 0 D97 D98 D99 D100 D101 D102 D103 D104 Device Address 8 bits --- D186 D187 D188 D189 D190 D191 D192 0 0 --- 0 0 0 0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PG8 PG9 0 PF0 PF1 PF2 PF3 CT0 CT1 CT2 CT3 0 Control Data 53 bits Display Data 96 bits 0 1 DD 3 bits SCE SCL SDI 1 0 0 1 0 0 1 0 D193 D194 D195 D196 D197 D198 D200 D201 Device Address 8 bits --- D282 D283 D284 D285 D286 D287 D288 0 0 --- 0 0 WN10 WN11 --- WN17 WN18 WN20 WN21 --- WN27 WN28 WN30 WN31 --- WN37 WN38 WN40 WN41 --- WN47 WN48 0 Control Data 53 bits Display Data 96 bits 1 0 DD 3 bits SCE SCL SDI 1 0 0 1 0 0 1 0 D289 D290 D291 D292 D293 D294 D295 D296 Device Address 8 bits --- D378 D379 D380 D381 D382 D383 D384 0 0 --- 0 0 WN50 WN51 --- WN57 WN58 WN60 WN61 Display Data 96 bits --- WN77 WN78 WN80 WN81 --- WN87 WN88 WN90 WN91 --- WN97 WN98 0 1 1 DD 3 bits Control Data 53 bits SCE SCL SDI 1 0 0 1 0 0 1 0 D385 D386 D387 D388 D389 D390 D391 --- D463 D465 D467 D468 D469 0 --- 0 0 0 0 0 0 0 0 0 0 0 0 0 --- 0 0 0 0 0 0 0 0 0 0 0 0 1 Control Data 53 bits Display Data 96 bits Device Address 8 bits 0 0 DD 3 bits SCE SCL SDI 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 Device Address 8 bits 0 --- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Display Data 96 bits 0 0 --- 0 0 0 0 0 0 0 0 0 0 0 0 Control Data 53 bits 1 0 1 DD 3 bits (Note9) Figure 10. 3-SPI Data Transfer Format (Note9) DD is direction data. Device code ································ ”49H” KM0 to KM2 ································ Key Scan output port/Segment output port switching control data D1 to D469·································· Display data P0 to P3 ····································· Segment/PWM/General-Purpose output port switching control data FL ············································· Line Inversion or Frame Inversion switching control data DR0 to DR1 ································· 1/4 bias driver, 1/3 bias driver or 1/2 bias driver switching control data DT0 to DT2 ································· 1/8-duty drive, 1/7-duty drive, 1/5-duty drive, 1/4-duty drive, 1/3-duty drive or Static drive switching control data FC0 to FC3 ································· Common/Segment output waveform frame frequency setting control data OC ············································ Internal oscillator operating mode/External clock operating mode switching control data SC ············································· Segment on/off control data BU0 to BU2 ································· Normal mode/Power-saving mode control data PG1 to PG9 ································· PWM/General-Purpose output port select data PF0 to PF3·································· PWM output waveform frame frequency setting control data. CT0 to CT3 ································· LCD bias voltage VLCD setting control data. W10 to W18, W20 to W28, W30 to W38,W40 to W48, W50 to W58, W60 to W68, W70 to W78, W80 to W88, W90 to W98 ········································· PWM output duty setting control data When it is coincident with device code, BU97550KV-M capture display data and control data at falling edge of SCE. So, please transfer the bit number of send display data and control data as specified number in the above figure. Specified number of bits is 160bit (Device code: 8bit, Display data and Control data: 149bit, DD: 3bit). www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 11/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Serial Data Transfer Formats – continued 3. 1/5 Duty (1) When SCL is stopped at the low level SCE SCL SDI 1 0 0 1 0 0 1 0 D1 D2 D3 D4 D5 D6 D7 D8 Device Address 8 bits --- D90 D91 D92 D93 D94 D95 D96 0 --- 0 DR0 DR1 DT0 DT1 DT2 KM0 KM1 KM2 P0 Display Data 96 bits P1 P2 P3 FL FC0 FC1 FC2 FC3 OC SC BU0 BU1 BU2 0 0 0 DD 3 bits Control Data 53 bits SCE SCL SDI 1 0 0 1 0 0 1 0 D97 D98 D99 D100 D101 D102 D103 D104 Device Address 8 bits --- D186 D187 D188 D189 D190 D191 D192 0 0 --- 0 0 0 0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PG8 PG9 0 PF0 PF1 PF2 PF3 CT0 CT1 CT2 CT3 0 Control Data 53 bits Display Data 96 bits 0 1 DD 3 bits SCE SCL SDI 1 0 0 1 0 0 1 0 D193 D194 D195 D196 D197 D198 D200 D201 Device Address 8 bits --- D282 D283 D284 D285 D286 D287 D288 0 0 --- 0 0 WN10 WN11 --- WN17 WN18 WN20 WN21 --- WN27 WN28 WN30 WN31 --- WN37 WN38 WN40 WN41 --- WN47 WN48 0 Control Data 53 bits Display Data 96 bits 1 0 DD 3 bits SCE SCL SDI 1 0 0 1 0 0 1 0 D289 D290 D291 D292 D293 D294 --- D340 Device Address 8 bits D341 D342 D343 D344 D345 0 --- 0 0 0 --- 0 0 WN50 WN51 --- WN57 WN58 WN60 WN61 Display Data 96 bits --- WN77 WN78 WN80 WN81 --- WN87 WN88 WN90 WN91 --- WN97 WN98 0 1 1 DD 3 bits Control Data 53 bits SCE SCL SDI 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 --- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 --- 0 0 0 0 0 0 0 0 0 0 0 0 1 Control Data 53 bits Display Data 96 bits Device Address 8 bits 0 0 DD 3 bits SCE SCL SDI 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 Device Address 8 bits 0 --- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Display Data 96 bits --- 0 0 Control Data 53 bits 0 0 0 0 0 0 0 0 0 0 1 0 1 DD 3 bits (Note10) Figure 11. 3-SPI Data Transfer Format (Note10) DD is direction data. www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 12/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Serial Data Transfer Formats – continued (2) When SCL is stopped at the high level SCE SCL SDI 1 0 0 1 0 0 1 0 D1 D2 D3 D4 D5 D6 D7 D8 Device Address 8 bits --- D90 D91 D92 D93 D94 D95 D96 0 --- 0 DR0 DR1 DT0 DT1 DT2 KM0 KM1 KM2 P0 Display Data 96 bits P1 P2 P3 FL FC0 FC1 FC2 FC3 OC SC BU0 BU1 BU2 0 0 0 DD 3 bits Control Data 53 bits SCE SCL SDI 1 0 0 1 0 0 1 0 D97 D98 D99 D100 D101 D102 D103 D104 Device Address 8 bits --- D186 D187 D188 D189 D190 D191 D192 0 0 --- 0 0 0 0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PG8 PG9 0 PF0 PF1 PF2 PF3 CT0 CT1 CT2 CT3 0 Control Data 53 bits Display Data 96 bits 0 1 DD 3 bits SCE SCL SDI 1 0 0 1 0 0 1 0 D193 D194 D195 D196 D197 D198 D200 D201 Device Address 8 bits --- D282 D283 D284 D285 D286 D287 D288 0 0 --- 0 0 WN10 WN11 --- WN17 WN18 WN20 WN21 --- WN27 WN28 WN30 WN31 --- WN37 WN38 WN40 WN41 --- WN47 WN48 0 Control Data 53 bits Display Data 96 bits 1 0 DD 3 bits SCE SCL SDI 1 0 0 1 0 0 1 0 D289 D290 D291 D292 D293 D294 --- D340 Device Address 8 bits D341 D342 D343 D344 D345 0 --- 0 0 0 --- 0 0 WN50 WN51 --- WN57 WN58 WN60 WN61 Display Data 96 bits --- WN77 WN78 WN80 WN81 --- WN87 WN88 WN90 WN91 --- WN97 WN98 0 1 1 DD 3 bits Control Data 53 bits SCE SCL SDI 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 --- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 --- 0 0 0 0 0 0 0 0 0 0 0 0 1 Control Data 53 bits Display Data 96 bits Device Address 8 bits 0 0 DD 3 bits SCE SCL SDI 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 Device Address 8 bits 0 --- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Display Data 96 bits --- 0 0 0 0 0 0 0 0 0 0 0 0 Control Data 53 bits 1 0 1 DD 3 bits (Note11) Figure 12. 3-SPI Data Transfer Format (Note11) DD is direction data. Device code ································ ”49H” KM0 to KM2 ································ Key Scan output port/Segment output port switching control data D1 to D345·································· Display data P0 to P3 ····································· Segment/PWM/General-Purpose output port switching control data FL ············································· Line Inversion or Frame Inversion switching control data DR0 to DR1 ································· 1/4 bias driver, 1/3 bias driver or 1/2 bias driver switching control data DT0 to DT2 ································· 1/8-duty drive, 1/7-duty drive, 1/5-duty drive, 1/4-duty drive, 1/3-duty drive or Static drive switching control data FC0 to FC3 ································· Common/Segment output waveform frame frequency setting control data OC ············································ Internal oscillator operating mode/External clock operating mode switching control data SC ············································· Segment on/off control data BU0 to BU2 ································· Normal mode/Power-saving mode control data PG1 to PG9 ································· PWM/General-Purpose output port select data PF0 to PF3·································· PWM output waveform frame frequency setting control data. CT0 to CT3 ································· LCD bias voltage VLCD setting control data. W10 to W18, W20 to W28, W30 to W38, W40 to W48, W50 to W58, W60 to W68, W70 to W78, W80 to W88, W90 to W98 ········································· PWM output duty setting control data When it is coincident with device code, BU97550KV-M capture display data and control data at falling edge of SCE. So, please transfer the bit number of send display data and control data as specified number in the above figure. Specified number of bits is 160bit (Device code: 8bit, Display data and Control data: 149bit, DD: 3bit). www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 13/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Serial Data Transfer Formats – continued 4. 1/4 Duty (1) When SCL is stopped at the low level SCE SCL SDI 1 0 0 1 0 0 1 0 D1 D2 D3 D4 D5 D6 D7 D8 Device Address 8 bits --- D90 D91 D92 D93 D94 D95 D96 0 --- 0 DR0 DR1 DT0 DT1 DT2 KM0 KM1 KM2 P0 Display Data 96 bits P1 P2 P3 FL FC0 FC1 FC2 FC3 OC SC BU0 BU1 BU2 0 0 0 DD 3 bits Control Data 53 bits SCE SCL SDI 1 0 0 1 0 0 1 0 D97 D98 D99 D100 D101 D102 D103 D104 Device Address 8 bits --- D186 D187 D188 D189 D190 D191 D192 0 0 --- 0 0 0 0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PG8 PG9 0 PF0 PF1 PF2 PF3 CT0 CT1 CT2 CT3 0 Control Data 53 bits Display Data 96 bits 0 1 DD 3 bits SCE SCL SDI 1 0 0 1 0 0 1 0 D193 D194 D195 D196 D197 D198 D200 D201 Device Address 8 bits --- D276 D278 D279 D280 0 --- 0 0 0 --- 0 0 WN10 WN11 --- WN17 WN18 WN20 WN21 --- WN27 WN28 WN30 WN31 --- WN37 WN38 WN40 WN41 --- WN47 WN48 0 Control Data 53 bits Display Data 96 bits 1 0 DD 3 bits SCE SCL SDI 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 Device Address 8 bits --- 0 0 0 0 0 0 0 0 0 --- 0 0 WN50 WN51 --- WN57 WN58 WN60 WN61 Display Data 96 bits --- WN77 WN78 WN80 WN81 --- WN87 WN88 WN90 WN91 --- WN97 WN98 0 1 1 DD 3 bits Control Data 53 bits SCE SCL SDI 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 Device Address 8 bits --- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 --- 0 0 0 0 0 0 0 0 0 0 0 0 1 Control Data 53 bits Display Data 96 bits 0 0 DD 3 bits SCE SCL SDI 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 Device Address 8 bits 0 --- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Display Data 96 bits --- 0 0 Control Data 53 bits 0 0 0 0 0 0 0 0 0 0 1 0 1 DD 3 bits (Note12) Figure 13. 3-SPI Data Transfer Format (Note12) DD is direction data. www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 14/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Serial Data Transfer Formats – continued (2) When SCL is stopped at the high level SCE SCL SDI 1 0 0 1 0 0 1 0 D1 D2 D3 D4 D5 D6 D7 D8 Device Address 8 bits --- D90 D91 D92 D93 D94 D95 D96 0 --- 0 DR0 DR1 DT0 DT1 DT2 KM0 KM1 KM2 P0 Display Data 96 bits P1 P2 P3 FL FC0 FC1 FC2 FC3 OC SC BU0 BU1 BU2 0 0 0 DD 3 bits Control Data 53 bits SCE SCL SDI 1 0 0 1 0 0 1 0 D97 D98 D99 D100 D101 D102 D103 D104 Device Address 8 bits --- D186 D187 D188 D189 D190 D191 D192 0 0 --- 0 0 0 0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PG8 PG9 0 PF0 PF1 PF2 PF3 CT0 CT1 CT2 CT3 0 Control Data 53 bits Display Data 96 bits 0 1 DD 3 bits SCE SCL SDI 1 0 0 1 0 0 1 0 D193 D194 D195 D196 D197 D198 D200 D201 Device Address 8 bits --- D276 D278 D279 D280 0 --- 0 0 0 --- 0 0 WN10 WN11 --- WN17 WN18 WN20 WN21 --- WN27 WN28 WN30 WN31 --- WN37 WN38 WN40 WN41 --- WN47 WN48 0 Control Data 53 bits Display Data 96 bits 1 0 DD 3 bits SCE SCL SDI 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 Device Address 8 bits --- 0 0 0 0 0 0 0 0 0 --- 0 0 WN50 WN51 --- WN57 WN58 WN60 WN61 Display Data 96 bits --- WN77 WN78 WN80 WN81 --- WN87 WN88 WN90 WN91 --- WN97 WN98 0 1 1 DD 3 bits Control Data 53 bits SCE SCL SDI 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 Device Address 8 bits --- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 --- 0 0 0 0 0 0 0 0 0 0 0 0 1 Control Data 53 bits Display Data 96 bits 0 0 DD 3 bits SCE SCL SDI 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 Device Address 8 bits 0 --- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Display Data 96 bits --- 0 0 0 0 0 0 0 0 0 0 0 0 Control Data 53 bits 1 0 1 DD 3 bits (Note13) Figure 14. 3-SPI Data Transfer Format (Note13) DD is direction data. Device code ································ ”49H” KM0 to KM2 ································ Key Scan output port/Segment output port switching control data D1 to D280·································· Display data P0 to P3 ····································· Segment/PWM/General-Purpose output port switching control data FL ············································· Line Inversion or Frame Inversion switching control data DR0 to DR1 ································· 1/4 bias driver, 1/3 bias driver or 1/2 bias driver switching control data DT0 to DT2 ································· 1/8-duty drive, 1/7-duty drive, 1/5-duty drive, 1/4-duty drive, 1/3-duty drive or Static drive switching control data FC0 to FC3 ································· Common/Segment output waveform frame frequency setting control data OC ············································ Internal oscillator operating mode/External clock operating mode switching control data SC ············································· Segment on/off control data BU0 to BU2 ································· Normal mode/Power-saving mode control data PG1 to PG9 ································· PWM/General-Purpose output port select data PF0 to PF3·································· PWM output waveform frame frequency setting control data. CT0 to CT3 ································· LCD bias voltage VLCD setting control data. W10 to W18, W20 to W28, W30 to W38, W40 to W48, W50 to W58, W60 to W68, W70 to W78, W80 to W88, W90 to W98 ········································· PWM output duty setting control data When it is coincident with device code, BU97550KV-M capture display data and control data at falling edge of SCE. So, please transfer the bit number of send display data and control data as specified number in the above figure. Specified number of bits is 160bit (Device code: 8bit, Display data and Control data: 149bit, DD: 3bit). www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 15/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Serial Data Transfer Formats – continued 5. 1/3 Duty (1) When SCL is stopped at the low level SCE SCL SDI 1 0 0 1 0 0 1 0 D1 D2 D3 D4 D5 D6 D7 D8 Device Address 8 bits --- D90 D91 D92 D93 D94 D95 D96 0 --- 0 DR0 DR1 DT0 DT1 DT2 KM0 KM1 KM2 P0 Display Data 96 bits P1 P2 P3 FL FC0 FC1 FC2 FC3 OC SC BU0 BU1 BU2 0 0 0 DD 3 bits Control Data 53 bits SCE SCL SDI 1 0 0 1 0 0 1 0 D97 D98 D99 D100 D101 D102 D103 D104 Device Address 8 bits --- D186 D187 D188 D189 D190 D191 D192 0 0 --- 0 0 0 0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PG8 PG9 0 PF0 PF1 PF2 PF3 CT0 CT1 CT2 CT3 0 Control Data 53 bits Display Data 96 bits 0 1 DD 3 bits SCE SCL SDI 1 0 0 1 0 0 1 0 D193 D194 D195 D196 --- D205 D206 D207 Device Address 8 bits D209 210 0 0 0 0 --- 0 0 0 0 0 0 WN10 WN11 --- WN17 WN18 WN20 WN21 --- WN27 WN28 WN30 WN31 --- WN37 WN38 WN40 WN41 --- WN47 WN48 0 Control Data 53 bits Display Data 96 bits 1 0 DD 3 bits SCE SCL SDI 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 Device Address 8 bits --- 0 0 0 0 0 0 0 0 0 --- 0 0 WN50 WN51 --- WN57 WN58 WN60 WN61 Display Data 96 bits --- WN77 WN78 WN80 WN81 --- WN87 WN88 WN90 WN91 --- WN97 WN98 0 1 1 DD 3 bits Control Data 53 bits SCE SCL SDI 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 --- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Display Data 96 bits Device Address 8 bits --- 0 0 0 0 0 0 0 0 0 0 0 0 1 Control Data 53 bits 0 0 DD 3 bits SCE SCL SDI 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 Device Address 8 bits 0 --- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Display Data 96 bits 0 0 --- 0 Control Data 53 bits 0 0 0 0 0 0 0 0 0 0 0 1 0 1 DD 3 bits (Note14) Figure 15. 3-SPI Data Transfer Format (Note14) DD is direction data. www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 16/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Serial Data Transfer Formats – continued (2) When SCL is stopped at the high level SCE SCL SDI 1 0 0 1 0 0 1 0 D1 D2 D3 D4 D5 D6 D7 D8 Device Address 8 bits --- D90 D91 D92 D93 D94 D95 D96 0 --- 0 DR0 DR1 DT0 DT1 DT2 KM0 KM1 KM2 P0 Display Data 96 bits P1 P2 P3 FL FC0 FC1 FC2 FC3 OC SC BU0 BU1 BU2 0 0 0 DD 3 bits Control Data 53 bits SCE SCL SDI 1 0 0 1 0 0 1 0 D97 D98 D99 D100 D101 D102 D103 D104 Device Address 8 bits --- D186 D187 D188 D189 D190 D191 D192 0 0 --- 0 0 0 0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PG8 PG9 0 PF0 PF1 PF2 PF3 CT0 CT1 CT2 CT3 0 Control Data 53 bits Display Data 96 bits 0 1 DD 3 bits SCE SCL SDI 1 0 0 1 0 0 1 0 D193 D194 D195 D196 --- D205 D206 D207 Device Address 8 bits D209 210 0 0 0 0 --- 0 0 0 0 0 0 WN10 WN11 --- WN17 WN18 WN20 WN21 --- WN27 WN28 WN30 WN31 --- WN37 WN38 WN40 WN41 --- WN47 WN48 0 Control Data 53 bits Display Data 96 bits 1 0 DD 3 bits SCE SCL SDI 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 Device Address 8 bits --- 0 0 0 0 0 0 0 0 0 --- 0 0 WN50 WN51 --- WN57 WN58 WN60 WN61 Display Data 96 bits --- WN77 WN78 WN80 WN81 --- WN87 WN88 WN90 WN91 --- WN97 WN98 0 1 1 DD 3 bits Control Data 53 bits SCE SCL SDI 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 --- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Display Data 96 bits Device Address 8 bits --- 0 0 0 0 0 0 0 0 0 0 0 0 1 Control Data 53 bits 0 0 DD 3 bits SCE SCL SDI 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 Device Address 8 bits 0 --- 0 0 0 0 0 0 0 0 0 0 Display Data 96 bits 0 0 0 0 0 0 0 0 0 --- 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 DD 3 bits Control Data 53 bits (Note15) Figure 16. 3-SPI Data Transfer Format (Note15) DD is direction data. Device code ································ ”49H” KM0 to KM2 ································ Key Scan output port/Segment output port switching control data D1 to D210·································· Display data P0 to P3 ····································· Segment/PWM/General-Purpose output port switching control data FL ············································· Line Inversion or Frame Inversion switching control data DR0 to DR1 ································· 1/4 bias driver, 1/3 bias driver or 1/2 bias driver switching control data DT0 to DT2 ································· 1/8-duty drive, 1/7-duty drive, 1/5-duty drive, 1/4-duty drive, 1/3-duty drive or Static drive switching control data FC0 to FC3 ································· Common/Segment output waveform frame frequency setting control data OC ············································ Internal oscillator operating mode/External clock operating mode switching control data SC ············································· Segment on/off control data BU0 to BU2 ································· Normal mode/Power-saving mode control data PG1 to PG9 ································· PWM/General-Purpose output port select data PF0 to PF3·································· PWM output waveform frame frequency setting control data. CT0 to CT3 ································· LCD bias voltage VLCD setting control data. W10 to W18, W20 to W28, W30 to W38, W40 to W48, W50 to W58, W60 to W68, W70 to W78, W80 to W88, W90 to W98 ········································· PWM output duty setting control data When it is coincident with device code, BU97550KV-M capture display data and control data at falling edge of SCE. So, please transfer the bit number of send display data and control data as specified number in the above figure. Specified number of bits is 160bit (Device code: 8bit, Display data and Control data: 149bit, DD: 3bit). www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 17/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Serial Data Transfer Formats – continued 6. Static (1) When SCL is stopped at the low level SCE SCL SDI 1 0 0 1 0 0 1 0 D1 D2 D3 D4 D5 D6 D7 D8 Device Address 8 bits --- D67 D68 D69 D70 0 --- 0 0 --- 0 DR0 DR1 DT0 DT1 DT2 KM0 KM1 KM2 P0 Display Data 96 bits P1 P2 P3 FL FC0 FC1 FC2 FC3 OC SC BU0 BU1 BU2 0 0 0 DD 3 bits Control Data 53 bits SCE SCL SDI 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 Device Address 8 bits --- 0 0 0 0 0 0 0 0 0 --- 0 0 0 0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PG8 PG9 0 PF0 PF1 PF2 PF3 CT0 CT1 CT2 CT3 0 Control Data 53 bits Display Data 96 bits 0 1 DD 3 bits SCE SCL SDI 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 Device Address 8 bits --- 0 0 0 0 0 0 0 0 0 0 0 0 WN10 WN11 --- WN17 WN18 WN20 WN21 --- WN27 WN28 WN30 WN31 --- WN37 WN38 WN40 WN41 --- WN47 WN48 0 Control Data 53 bits Display Data 96 bits 1 0 DD 3 bits SCE SCL SDI 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 Device Address 8 bits --- 0 0 0 0 0 0 0 0 0 --- 0 0 WN50 WN51 --- WN57 WN58 WN60 WN61 Display Data 96 bits --- WN77 WN78 WN80 WN81 --- WN87 WN88 WN90 WN91 --- WN97 WN98 0 1 1 DD 3 bits Control Data 53 bits SCE SCL SDI 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 --- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Display Data 96 bits Device Address 8 bits --- 0 0 0 0 0 0 0 0 0 0 0 0 1 Control Data 53 bits 0 0 DD 3 bits SCE SCL SDI 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 Device Address 8 bits 0 --- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Display Data 96 bits 0 0 --- 0 Control Data 53 bits 0 0 0 0 0 0 0 0 0 0 0 1 0 1 DD 3 bits (Note16) Figure 17. 3-SPI Data Transfer Format (Note16) DD is direction data. www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 18/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Serial Data Transfer Formats – continued (2) When SCL is stopped at the high level SCE SCL SDI 1 0 0 1 0 0 1 0 D1 D2 D3 D4 D5 D6 D7 D8 Device Address 8 bits --- D67 D68 D69 D70 0 --- 0 0 --- 0 DR0 DR1 DT0 DT1 DT2 KM0 KM1 KM2 P0 Display Data 96 bits P1 P2 P3 FL FC0 FC1 FC2 FC3 OC SC BU0 BU1 BU2 0 0 0 DD 3 bits Control Data 53 bits SCE SCL SDI 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 Device Address 8 bits --- 0 0 0 0 0 0 0 0 0 --- 0 0 0 0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PG8 PG9 0 PF0 PF1 PF2 PF3 CT0 CT1 CT2 CT3 0 Control Data 53 bits Display Data 96 bits 0 1 DD 3 bits SCE SCL SDI 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 Device Address 8 bits --- 0 0 0 0 0 0 0 0 0 0 0 0 WN10 WN11 --- WN17 WN18 WN20 WN21 --- WN27 WN28 WN30 WN31 --- WN37 WN38 WN40 WN41 --- WN47 WN48 0 Control Data 53 bits Display Data 96 bits 1 0 DD 3 bits SCE SCL SDI 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 Device Address 8 bits --- 0 0 0 0 0 0 0 0 0 --- 0 0 WN50 WN51 --- WN57 WN58 WN60 WN61 Display Data 96 bits --- WN77 WN78 WN80 WN81 --- WN87 WN88 WN90 WN91 --- WN97 WN98 0 1 1 DD 3 bits Control Data 53 bits SCE SCL SDI 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 --- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Display Data 96 bits Device Address 8 bits --- 0 0 0 0 0 0 0 0 0 0 0 0 1 Control Data 53 bits 0 0 DD 3 bits SCE SCL SDI 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 Device Address 8 bits 0 --- 0 0 0 0 0 0 0 0 0 0 Display Data 96 bits 0 0 0 0 0 0 0 0 0 --- 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 DD 3 bits Control Data 53 bits (Note17) Figure 18. 3-SPI Data Transfer Format (Note17) DD is direction data. Device code ································ ”49H” KM0 to KM2 ································ Key Scan output port/Segment output port switching control data D1 to D70 ··································· Display data P0 to P3 ····································· Segment/PWM/General-Purpose output port switching control data FL ············································· Line Inversion or Frame Inversion switching control data DR0 to DR1 ································· 1/4 bias driver, 1/3 bias driver or 1/2 bias driver switching control data DT0 to DT2 ································· 1/8-duty drive, 1/7-duty drive, 1/5-duty drive, 1/4-duty drive, 1/3-duty drive or Static drive switching control data FC0 to FC3 ································· Common/Segment output waveform frame frequency setting control data OC ············································ Internal oscillator operating mode/External clock operating mode switching control data SC ············································· Segment on/off control data BU0 to BU2 ································· Normal mode/Power-saving mode control data PG1 to PG9 ································· PWM/General-Purpose output port select data PF0 to PF3·································· PWM output waveform frame frequency setting control data. CT0 to CT3 ································· LCD bias voltage VLCD setting control data. W10 to W18, W20 to W28, W30 to W38, W40 to W48, W50 to W58, W60 to W68, W70 to W78, W80 to W88, W90 to W98 ········································· PWM output duty setting control data When it is coincident with device code, BU97550KV-M capture display data and control data at falling edge of SCE. So, please transfer the bit number of send display data and control data as specified number in the above figure. Specified number of bits is 160bit (Device code: 8bit, Display data and Control data: 149bit, DD: 3bit). www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 19/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Control Data Functions 1. KM0, KM1 and KM2: Key Scan output port/Segment output port switching control data These control data bits switch the functions of the KS1/S53 to KS6/S58 output pins between key scan output and Segment output. Output Pin State Maximum Number Reset KM0 KM1 KM2 of Input keys condition KS1/S53 KS2/S54 KS3/S55 KS4/S56 KS5/S57 KS6/S58 0 0 0 KS1 KS2 KS3 KS4 KS5 KS6 30 0 0 1 S53 KS2 KS3 KS4 KS5 KS6 25 0 1 0 S53 S54 KS3 KS4 KS5 KS6 20 0 1 1 S53 S54 S55 KS4 KS5 KS6 15 1 0 0 S53 S54 S55 S56 KS5 KS6 10 1 0 1 S53 S54 S55 S56 S57 KS6 5 1 1 0 S53 S54 S55 S56 S57 S58 0 1 1 1 S53 S54 S55 S56 S57 S58 0 ○ 2. P0, P1, P2 and P3: Segment/PWM/General-Purpose output port switching control data These control bits are used to select the function of the S1/P1/G1 to S9/P9/G9 output Pins (Segment output Pins or PWM output Pins or General-Purpose output Pins). Reset P0 P1 P2 P3 S1/P1/G1 S2/P2/G2 S3/P3/G3 S4/P4/G4 S5/P5/G5 S6/P6/G6 S7/P7/G7 S8/P8/G8 S9/P9/G9 condition 0 0 0 0 S1 S2 S3 S4 S5 S6 S7 S8 S9 0 0 0 1 P1/G1 S2 S3 S4 S5 S6 S7 S8 S9 0 0 1 0 P1/G1 P2/G2 S3 S4 S5 S6 S7 S8 S9 0 0 1 1 P1/G1 P2/G2 P3/G3 S4 S5 S6 S7 S8 S9 0 1 0 0 P1/G1 P2/G2 P3/G3 P4/G4 S5 S6 S7 S8 S9 0 1 0 1 P1/G1 P2/G2 P3/G3 P4/G4 P5/G5 S6 S7 S8 S9 0 1 1 0 P1/G1 P2/G2 P3/G3 P4/G4 P5/G5 P6/G6 S7 S8 S9 0 1 1 1 P1/G1 P2/G2 P3/G3 P4/G4 P5/G5 P6/G6 P7/G7 S8 S9 1 0 0 0 P1/G1 P2/G2 P3/G3 P4/G4 P5/G5 P6/G6 P7/G7 P8/G8 S9 1 0 0 1 P1/G1 P2/G2 P3/G3 P4/G4 P5/G5 P6/G6 P7/G7 P8/G8 P9/G9 1 0 1 0 S1 S2 S3 S4 S5 S6 S7 S8 S9 1 0 1 1 S1 S2 S3 S4 S5 S6 S7 S8 S9 1 1 0 0 S1 S2 S3 S4 S5 S6 S7 S8 S9 1 1 0 1 S1 S2 S3 S4 S5 S6 S7 S8 S9 1 1 1 0 S1 S2 S3 S4 S5 S6 S7 S8 S9 1 1 1 1 S1 S2 S3 S4 S5 S6 S7 S8 S9 ○ PWM output or General-Purpose output is selected by PGx(x=1 to 9) control data bit. When the General-Purpose output Port Function is selected, the correspondence between the output Pins and the respective display data is given in the table below. Corresponding Display Data Output Pins 1/8 Duty mode 1/7 Duty mode 1/5 Duty mode 1/4 Duty mode 1/3 Duty mode Static S1/P1/G1 D1 D1 D1 D1 D1 D1 S2/P2/G2 D9 D8 D6 D5 D4 D2 S3/P3/G3 D17 D15 D11 D9 D7 D3 S4/P4/G4 D25 D22 D16 D13 D10 D4 S5/P5/G5 D33 D29 D21 D17 D13 D5 S6/P6/G6 D41 D36 D26 D21 D16 D6 S7/P7/G7 D49 D43 D31 D25 D19 D7 S8/P8/G8 D57 D50 D36 D29 D22 D8 S9/P9/G9 D65 D57 D41 D33 D25 D9 When the General-Purpose output Port Function is selected, the respective output pin outputs a “H” level when its corresponding display data is set to “1”. Likewise, it will output a “L” level, if its corresponding display data is set to “0”. For example, at 1/4 Duty mode, S4/P4/G4 is used as a General-Purpose output Port, if its corresponding display data D13 is set to “1”, then S4/P4/G4 will output “H” level. Likewise, if D13 is set to “0”, then S4/P4/G4 will output “L” level. 3. FL: Line Inversion or Frame Inversion switching control data This control data bit selects either line inversion mode or frame inversion mode. FL Inversion mode Reset condition 0 Line Inversion ○ 1 Frame Inversion - www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 20/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Control Data Functions – continued 4. DR: 1/4 bias drive, 1/3 bias drive, 1/2 bias drive or 1/1 bias drive switching control data This control data bit selects either 1/4 bias drive, 1/3 bias drive, 1/2 bias drive or 1/1 bias drive. DR0 DR1 Bias drive scheme 0 0 1/3 Bias 0 1 1/1 Bias 1 0 1/4 Bias 1 1 1/2 Bias Reset condition ○ - 5. DT: 1/8 duty drive, 1/7 duty drive, 1/5 duty drive, 1/4 duty drive, 1/3 duty drive or Static switching control data These control data bits select either 1/8 duty drive, 1/7 duty drive, 1/5 duty drive, 1/4 duty drive, 1/3 duty drive or Static DT0 DT1 DT2 Duty drive scheme Reset condition 0 0 0 Static drive 0 0 1 1/3 duty drive 0 1 0 1/4 duty drive ○ 0 1 1 1/5 duty drive 1 0 0 1/7 duty drive 1 0 1 1/8 duty drive 1 1 0 1/4 duty drive 1 1 1 1/4 duty drive 6. FC0, FC1, FC2 and FC3: Common/Segment output waveform frame frequency setting control data These control data bits set the frame frequency for Common and Segment output waveforms. FC0 FC1 FC2 FC3 Frame Frequency fo(Hz) Reset condition 0 0 0 0 fosc(Note18) / 12288 ○ 0 0 0 1 fosc / 10752 0 0 1 0 fosc / 9216 0 0 1 1 fosc / 7680 0 1 0 0 fosc / 6144 0 1 0 1 fosc / 4608 0 1 1 0 fosc / 3840 0 1 1 1 fosc / 3072 1 0 0 0 fosc / 2880 1 0 0 1 fosc / 2688 1 0 1 0 fosc / 2496 1 0 1 1 fosc / 2304 1 1 0 0 fosc / 2112 1 1 0 1 fosc / 1920 1 1 1 0 fosc / 1728 1 1 1 1 fosc / 1536 (Note18)fosc: Internal Oscillation Frequency (600 [kHz] Typ) www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 21/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Control Data Functions – continued 7. OC: Internal oscillator operating mode/External clock operating mode switching control data This control data bit selects oscillation mode. OC Operating mode In/Out pin(OSC/S70) status 0 Internal oscillator S70 (Segment output) 1 External Clock OSC_IN (clock input) Reset condition ○ - Internal oscillation / external clock select signal behavior is below. Input external clock after serial data sending. SCE SCL SDI 1 0 0 1 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 D1 D2 SC Display Data/ Control Data Dev ice Code 8bits BU0 BU1 BU2 0 0 0 DD 3 bits Internal oscillation・Extarnal Clock Select signal(Internal signal) Internal oscillation OSC (Internal signal) Extarnal Clock (OSC_IN) 8. SC: Segment on/off control data This control data bit controls the on/off state of the Segments. SC Display state Reset condition 0 ON 1 OFF ○ Note that when the Segments are turned off by setting SC to “1”, the Segments are turned off by outputting Segment off waveforms from the Segment output pins. www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 22/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Control Data Functions – continued 9. BU0, BU1 and BU2: Normal mode/Power-saving mode control data These control data bits select either normal mode or Power-saving mode. Output Pin States During Key Scan Standby Common outputs KS1 KS2 KS3 KS4 KS5 KS6 0 0 0 Normal Operating Operating H H H H H H 0 0 1 L L L L L H 0 1 0 L L L L H H 0 1 1 L L L H H H Power1 0 0 L L H H H H Stopped Low(VSS) saving 1 0 1 L H H H H H 1 1 0 H H H H H H 1 1 1 H H H H H H Power-saving mode status: S1/P1/G1 to S9/P9/G9 = active only General-Purpose output S10 to OSC_IN/S70 = low (VSS) COM1 to COM8 = low (VSS) Shut off current to the LCD drive bias voltage generation circuit Stop the Internal oscillation circuit However, serial data transfer is possible when at Power-saving mode. BU0 BU1 BU2 OSC Oscillator Mode Segment outputs Reset condition ○ 10. PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8 and PG9: PWM/ General-Purpose output port control data This control data bit select either PWM output or General-Purpose output of Sx/Px/Gx pins. (x=1 to 9) PGx(x=1 to 9) Mode Reset condition 0 PWM output ○ 1 General-Purpose output [PWMGPO Changing function] Normal behavior of changing GPO to PWM is below. - PWM operation is started by command import timing of DD: 001 during GPO  PWM change. - Please take care of reflect timing of new duty setting of DD: 010 and DD: 011 is from the next PWM. DD: 000 SCE DD: 001 DD: 010 GPO---> PWM change DD: 011 DD: 100 DD: 101 new duty decided timing PWM/GPO output start of PWM operation next PWM cycle (PWM waveform in immediate duty) (PWM waveform in new duty) In order to avoid this operation, please input commands in reverse as below. DD:101 SCE DD:100 new duty decided timing DD:011 DD:010 DD:001 DD:000 GPO --> PWM change PWM/GPO output Start of PWM operation (PWM waveform on new duty) www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 23/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Control Data Functions – continued 11. PF0, PF1, PF2, and PF3: PWM output waveform frame frequency setting control data These control data bits set the frame frequency for PWM output waveforms. PF0 PF1 PF2 PF3 PWM output Frame Frequency fp(Hz) 0 0 0 0 fosc / 4096 0 0 0 1 fosc / 3840 0 0 1 0 fosc / 3584 0 0 1 1 fosc / 3328 0 1 0 0 fosc / 3072 0 1 0 1 fosc / 2816 0 1 1 0 fosc / 2560 0 1 1 1 fosc / 2304 1 0 0 0 fosc / 2048 1 0 0 1 fosc / 1792 1 0 1 0 fosc / 1536 1 0 1 1 fosc / 1280 1 1 0 0 fosc / 1024 1 1 0 1 fosc / 768 1 1 1 0 fosc / 512 1 1 1 1 fosc / 256 www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 24/72 Reset condition ○ - TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Control Data Functions – continued 12. CT0, CT1, CT2 and CT3: Display Contrast setting control data These control data bits set display contrast CT0 CT1 CT2 CT3 LCD Drive bias voltage for VLCD Level 0 0 0 0 1.000*VDD 0 0 0 1 0.975*VDD 0 0 1 0 0.950*VDD 0 0 1 1 0.925*VDD 0 1 0 0 0.900*VDD 0 1 0 1 0.875*VDD 0 1 1 0 0.850*VDD 0 1 1 1 0.825*VDD 1 0 0 0 0.800*VDD 1 0 0 1 0.775*VDD 1 0 1 0 0.750*VDD 1 0 1 1 0.725*VDD 1 1 0 0 0.700*VDD 1 1 0 1 0.675*VDD 1 1 1 0 0.650*VDD 1 1 1 1 0.625*VDD Reset condition ○ - Avoid setting VLCD voltage under 2.5V. And ensure “VDD – VLCD > 0.6V” condition is satisfied. Unstable IC output voltage may result if the above conditions are not satisfied. The relationship of LCD display contrast setting and VLCD voltage CT Setting formula VDD= 6.000 VDD= 5.500 VDD= 5.000 VDD= 4.500 VDD= 4.000 VDD= 3.000 [V] 0 VDD VLCD= 6.000 VLCD= 5.500 VLCD= 5.000 VLCD= 4.500 VLCD= 4.000 VLCD= 3.000 [V] 1 0.975*VDD VLCD= 5.850 VLCD= 5.363 VLCD= 4.875 VLCD= 4.388 VLCD= 3.900 VLCD= 2.925 [V] 2 0.950*VDD VLCD= 5.700 VLCD= 5.225 VLCD= 4.750 VLCD= 4.275 VLCD= 3.800 VLCD= 2.850 [V] 3 0.925*VDD VLCD= 5.550 VLCD= 5.088 VLCD= 4.625 VLCD= 4.163 VLCD= 3.700 VLCD= 2.775 [V] 4 0.900*VDD VLCD= 5.400 VLCD= 4.950 VLCD= 4.500 VLCD= 4.050 VLCD= 3.600 VLCD= 2.700 [V] 5 0.875*VDD VLCD= 5.250 VLCD= 4.813 VLCD= 4.375 VLCD= 3.938 VLCD= 3.500 VLCD= 2.625 [V] 6 0.850*VDD VLCD= 5.100 VLCD= 4.675 VLCD= 4.250 VLCD= 3.825 VLCD= 3.400 VLCD= 2.550 [V] 7 0.825*VDD VLCD= 4.950 VLCD= 4.538 VLCD= 4.125 VLCD= 3.713 VLCD= 3.300 VLCD= 2.475 [V] 8 0.800*VDD VLCD= 4.800 VLCD= 4.400 VLCD= 4.000 VLCD= 3.600 VLCD= 3.200 VLCD= 2.400 [V] 9 0.775*VDD VLCD= 4.650 VLCD= 4.263 VLCD= 3.875 VLCD= 3.488 VLCD= 3.100 VLCD= 2.325 [V] 10 0.750*VDD VLCD= 4.500 VLCD= 4.125 VLCD= 3.750 VLCD= 3.375 VLCD= 3.000 VLCD= 2.250 [V] 11 0.725*VDD VLCD= 4.350 VLCD= 3.988 VLCD= 3.625 VLCD= 3.263 VLCD= 2.900 VLCD= 2.175 [V] 12 0.700*VDD VLCD= 4.200 VLCD= 3.850 VLCD= 3.500 VLCD= 3.150 VLCD= 2.800 VLCD= 2.100 [V] 13 0.675*VDD VLCD= 4.050 VLCD= 3.713 VLCD= 3.375 VLCD= 3.038 VLCD= 2.700 VLCD= 2.025 [V] 14 0.650*VDD VLCD= 3.900 VLCD= 3.575 VLCD= 3.250 VLCD= 2.925 VLCD= 2.600 VLCD= 1.950 [V] 15 0.625*VDD VLCD= 3.750 VLCD= 3.438 VLCD= 3.125 VLCD= 2.813 VLCD= 2.500 VLCD= 1.875 [V] Disabled www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 25/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Control Data Functions – continued 13. W10 to W18(Note19), W20 to W28, W30 to W38, W40 to W48, W50 to W58, W60 to W68, W70 to W78, W80 to W88 and W90 to W98: PWM output waveform duty setting control data. These control data bits set the high level pulse width (duty) for PWM output waveforms. n = 1 to 9, Tp = 1/fp Wn0 Wn1 Wn2 Wn3 Wn4 Wn5 Wn6 Wn7 Wn8 PWM duty Reset condition 0 0 0 0 0 0 0 0 0 (0/256) x Tp ○ 0 0 0 0 0 0 0 0 1 (1/256) x Tp 0 0 0 0 0 0 0 1 0 (2/256) x Tp 0 0 0 0 0 0 0 1 1 (3/256) x Tp 0 0 0 0 0 0 1 0 0 (4/256) x Tp 0 0 0 0 0 0 1 0 1 (5/256) x Tp 0 0 0 0 0 0 1 1 0 (6/256) x Tp 0 0 0 0 0 0 1 1 1 (7/256) x Tp 0 0 0 0 0 1 0 0 0 (8/256) x Tp 0 0 0 0 0 1 0 0 1 (9/256) x Tp 0 0 0 0 0 1 0 1 0 (10/256) x Tp 0 0 0 0 0 1 0 1 1 (11/256) x Tp 0 0 0 0 0 1 1 0 0 (12/256) x Tp 0 0 0 0 0 1 1 0 1 (13/256) x Tp 0 0 0 0 0 1 1 1 0 (14/256) x Tp 0 0 0 0 0 1 1 1 1 (15/256) x Tp 0 0 0 0 1 0 0 0 0 (16/256) x Tp 0 0 0 0 1 0 0 0 1 (17/256) x Tp 0 0 0 0 1 0 0 1 0 (18/256) x Tp 0 0 0 0 1 0 0 1 1 (19/256) x Tp 0 0 0 0 1 0 1 0 0 (20/256) x Tp … … … … … … … … … … 0 1 1 1 0 1 0 1 1 (235/256) x Tp 0 1 1 1 0 1 1 0 0 (236/256) x Tp 0 1 1 1 0 1 1 0 1 (237/256) x Tp 0 1 1 1 0 1 1 1 0 (238/256) x Tp 0 1 1 1 0 1 1 1 1 (239/256) x Tp 0 1 1 1 1 0 0 0 0 (240/256) x Tp 0 1 1 1 1 0 0 0 1 (241/256) x Tp 0 1 1 1 1 0 0 1 0 (242/256) x Tp 0 1 1 1 1 0 0 1 1 (243/256) x Tp 0 1 1 1 1 0 1 0 0 (244/256) x Tp 0 1 1 1 1 0 1 0 1 (245/256) x Tp 0 1 1 1 1 0 1 1 0 (246/256) x Tp 0 1 1 1 1 0 1 1 1 (247/256) x Tp 0 1 1 1 1 1 0 0 0 (248/256) x Tp 0 1 1 1 1 1 0 0 1 (249/256) x Tp 0 1 1 1 1 1 0 1 0 (250/256) x Tp 0 1 1 1 1 1 0 1 1 (251/256) x Tp 0 1 1 1 1 1 1 0 0 (252/256) x Tp 0 1 1 1 1 1 1 0 1 (253/256) x Tp 0 1 1 1 1 1 1 1 0 (254/256) x Tp 0 1 1 1 1 1 1 1 1 (255/256) x Tp 1 0 0 0 0 0 0 0 0 (256/256) x Tp 1 0 0 0 0 0 0 0 1 (256/256) x Tp 1 0 0 0 0 0 0 1 0 (256/256) x Tp 1 0 0 0 0 0 0 1 1 (256/256) x Tp … … … … … … … … … … 1 1 1 1 1 1 1 0 0 (256/256) x Tp 1 1 1 1 1 1 1 0 1 (256/256) x Tp 1 1 1 1 1 1 1 1 0 (256/256) x Tp 1 1 1 1 1 1 1 1 1 (256/256) x Tp (Note19) W10 to W18:S1/P1/G1 PWM duty data W20 to W28:S2/P2/G2 PWM duty data W30 to W38:S3/P3/G3 PWM duty data W40 to W48:S4/P4/G4 PWM duty data W50 to W58:S5/P5/G5 PWM duty data W60 to W68:S6/P6/G6 PWM duty data W70 to W78:S7/P7/G7 PWM duty data W80 to W88:S8/P8/G8 PWM duty data W90 to W98:S9/P9/G9 PWM duty data www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 26/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Display Data and Output Pin Correspondence 1. 1/8 Duty Output Pin(Note20) S1/P1/G1 S2/P2/G2 S3/P3/G3 S4/P4/G4 S5/P5/G5 S6/P6/G6 S7/P7/G7 S8/P8/G8 S9/P9/G9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 KS1/S53 KS2/S54 KS3/S55 KS4/S56 KS5/S57 KS6/S58 KI1/S59 KI2/S60 KI3/S61 KI4/S62 KI5/S63 COM1 D1 D9 D17 D25 D33 D41 D49 D57 D65 D73 D81 D89 D97 D105 D113 D121 D129 D137 D145 D153 D161 D169 D177 D185 D193 D201 D209 D217 D225 D233 D241 D249 D257 D265 D273 D281 D289 D297 D305 D313 D321 D329 D337 D345 D353 D361 D369 D377 D385 D393 D401 D409 D417 D425 D433 D441 D449 D457 D465 D473 D481 D489 D497 www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 COM2 D2 D10 D18 D26 D34 D42 D50 D58 D66 D74 D82 D90 D98 D106 D114 D122 D130 D138 D146 D154 D162 D170 D178 D186 D194 D202 D210 D218 D226 D234 D242 D250 D258 D266 D274 D282 D290 D298 D306 D314 D322 D330 D338 D346 D354 D362 D370 D378 D386 D394 D402 D410 D418 D426 D434 D442 D450 D458 D466 D474 D482 D490 D498 COM3 D3 D11 D19 D27 D35 D43 D51 D59 D67 D75 D83 D91 D99 D107 D115 D123 D131 D139 D147 D155 D163 D171 D179 D187 D195 D203 D211 D219 D227 D235 D243 D251 D259 D267 D275 D283 D291 D299 D307 D315 D323 D331 D339 D347 D355 D363 D371 D379 D387 D395 D403 D411 D419 D427 D435 D443 D451 D459 D467 D475 D483 D491 D499 27/72 COM4 D4 D12 D20 D28 D36 D44 D52 D60 D68 D76 D84 D92 D100 D108 D116 D124 D132 D140 D148 D156 D164 D172 D180 D188 D196 D204 D212 D220 D228 D236 D244 D252 D260 D268 D276 D284 D292 D300 D308 D316 D324 D332 D340 D348 D356 D364 D372 D380 D388 D396 D404 D412 D420 D428 D436 D444 D452 D460 D468 D476 D484 D492 D500 COM5 D5 D13 D21 D29 D37 D45 D53 D61 D69 D77 D85 D93 D101 D109 D117 D125 D133 D141 D149 D157 D165 D173 D181 D189 D197 D205 D213 D221 D229 D237 D245 D253 D261 D269 D277 D285 D293 D301 D309 D317 D325 D333 D341 D349 D357 D365 D373 D381 D389 D397 D405 D413 D421 D429 D437 D445 D453 D461 D469 D477 D485 D493 D501 COM6 D6 D14 D22 D30 D38 D46 D54 D62 D70 D78 D86 D94 D102 D110 D118 D126 D134 D142 D150 D158 D166 D174 D182 D190 D198 D206 D214 D222 D230 D238 D246 D254 D262 D270 D278 D286 D294 D302 D310 D318 D326 D334 D342 D350 D358 D366 D374 D382 D390 D398 D406 D414 D422 D430 D438 D446 D454 D462 D470 D478 D486 D494 D502 COM7 D7 D15 D23 D31 D39 D47 D55 D63 D71 D79 D87 D95 D103 D111 D119 D127 D135 D143 D151 D159 D167 D175 D183 D191 D199 D207 D215 D223 D231 D239 D247 D255 D263 D271 D279 D287 D295 D303 D311 D319 D327 D335 D343 D351 D359 D367 D375 D383 D391 D399 D407 D415 D423 D431 D439 D447 D455 D463 D471 D479 D487 D495 D503 COM8 D8 D16 D24 D32 D40 D48 D56 D64 D72 D80 D88 D96 D104 D112 D120 D128 D136 D144 D152 D160 D168 D176 D184 D192 D200 D208 D216 D224 D232 D240 D248 D256 D264 D272 D280 D288 D296 D304 D312 D320 D328 D336 D344 D352 D360 D368 D376 D384 D392 D400 D408 D416 D424 D432 D440 D448 D456 D464 D472 D480 D488 D496 D504 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Display Data and Output Pin Correspondence – continued Output Pin COM8/S64 COM7/S65 COM6/S66 COM5/S67 S68 S69 OSC_IN/S70 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 D505 D513 D521 D506 D514 D522 D507 D515 D523 D508 D516 D524 D509 D517 D525 D510 D518 D526 D511 D519 D527 D512 D520 D528 (Note20) The Segment output Port function is assumed to be selected for the output pins – S1/P1/G1 to S9/P9/G9, KS1/S53 to KS6/S58, KI1/S59 to KI5/S63 and OSC_IN/S70. Also, COM8/S64, COM7/S65, COM6/S66, COM5/S67 pins are used as Common outputs. To illustrate further, the states of the S21 output pin is given in the table below. Display Data State of S21 output Pin D161 D162 D163 D164 D165 D166 D167 D168 0 0 0 0 0 0 0 0 LCD Segments corresponding to COM1 to COM8 are OFF. 0 0 0 0 0 0 0 1 LCD Segment corresponding to COM8 is ON. 0 0 0 0 0 0 1 0 LCD Segment corresponding to COM7 is ON. 0 0 0 0 0 0 1 1 LCD Segments corresponding to COM7 and COM8 are ON. 0 0 0 0 0 1 0 0 LCD Segment corresponding to COM6 is ON. 0 0 0 0 0 1 0 1 LCD Segments corresponding to COM6 and COM8 are ON. 0 0 0 0 0 1 1 0 LCD Segments corresponding to COM6 and COM7 are ON. 0 0 0 0 0 1 1 1 LCD Segments corresponding to COM6, COM7 and COM8 are ON. 0 0 0 0 1 0 0 0 LCD Segment corresponding to COM5 is ON. 0 0 0 0 1 0 0 1 LCD Segments corresponding to COM5 and COM8 are ON. 0 0 0 0 1 0 1 0 LCD Segments corresponding to COM5 and COM7 are ON. 0 0 0 0 1 0 1 1 LCD Segments corresponding to COM5, COM7 and COM8 are ON. 0 0 0 0 1 1 0 0 LCD Segments corresponding to COM5 and COM6 are ON. 0 0 0 0 1 1 0 1 LCD Segments corresponding to COM5, COM6, and COM8 are ON. 0 0 0 0 1 1 1 0 LCD Segments corresponding to COM5, COM6, and COM7 are ON. LCD Segments corresponding to COM5, COM6, COM7 and COM8 0 0 0 0 1 1 1 1 are ON. 0 0 0 1 0 0 0 0 LCD Segment corresponding to COM4 is ON. 0 0 0 1 0 0 0 1 LCD Segments corresponding to COM4 and COM8 are ON. 0 0 0 1 0 0 1 0 LCD Segments corresponding to COM4 and COM7 are ON. 0 0 0 1 0 0 1 1 LCD Segments corresponding to COM4, COM7 and COM8 are ON. 0 0 0 1 0 1 0 0 LCD Segments corresponding to COM4 and COM6 are ON. 0 0 0 1 0 1 0 1 LCD Segments corresponding to COM4, COM6 and COM8 are ON. 0 0 0 1 0 1 1 0 LCD Segments corresponding to COM4, COM6 and COM7 are ON. LCD Segments corresponding to COM4, COM6, COM7 and COM8 0 0 0 1 0 1 1 1 are ON. 0 0 0 1 1 0 0 0 LCD Segments corresponding to COM4 and COM5 are ON. 0 0 0 1 1 0 0 1 LCD Segments corresponding to COM4, COM5 and COM8 are ON. 0 0 0 1 1 0 1 0 LCD Segments corresponding to COM4, COM5 and COM7 are ON. LCD Segments corresponding to COM4, COM5, COM7 and COM8 0 0 0 1 1 0 1 1 are ON. 0 0 0 1 1 1 0 0 LCD Segments corresponding to COM4, COM5 and COM6 are ON. LCD Segments corresponding to COM4, COM5, COM6 and COM8 0 0 0 1 1 1 0 1 are ON. LCD Segments corresponding to COM4, COM5, COM6 and COM7 0 0 0 1 1 1 1 0 are ON. . . . . . . . . . 1 1 1 1 1 1 1 1 LCD Segments corresponding to COM1 to COM8 are ON. www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 28/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Display Data and Output Pin Correspondence – continued 2. 1/7 Duty Output Pin(Note21) S1/P1/G1 S2/P2/G2 S3/P3/G3 S4/P4/G4 S5/P5/G5 S6/P6/G6 S7/P7/G7 S8/P8/G8 S9/P9/G9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 KS1/S53 KS2/S54 KS3/S55 KS4/S56 KS5/S57 KS6/S58 KI1/S59 KI2/S60 KI3/S61 KI4/S62 KI5/S63 COM1 D1 D8 D15 D22 D29 D36 D43 D50 D57 D64 D71 D78 D85 D92 D99 D106 D113 D120 D127 D134 D141 D148 D155 D162 D169 D176 D183 D190 D197 D204 D211 D218 D225 D232 D239 D246 D253 D260 D267 D274 D281 D288 D295 D302 D309 D316 D323 D330 D337 D344 D351 D358 D365 D372 D379 D386 D393 D400 D407 D414 D421 D428 D435 www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 COM2 D2 D9 D16 D23 D30 D37 D44 D51 D58 D65 D72 D79 D86 D93 D100 D107 D114 D121 D128 D135 D142 D149 D156 D163 D170 D177 D184 D191 D198 D205 D212 D219 D226 D233 D240 D247 D254 D261 D268 D275 D282 D289 D296 D303 D310 D317 D324 D331 D338 D345 D352 D359 D366 D373 D380 D387 D394 D401 D408 D415 D422 D429 D436 COM3 D3 D10 D17 D24 D31 D38 D45 D52 D59 D66 D73 D80 D87 D94 D101 D108 D115 D122 D129 D136 D143 D150 D157 D164 D171 D178 D185 D192 D199 D206 D213 D220 D227 D234 D241 D248 D255 D262 D269 D276 D283 D290 D297 D304 D311 D318 D325 D332 D339 D346 D353 D360 D367 D374 D381 D388 D395 D402 D409 D416 D423 D430 D437 29/72 COM4 D4 D11 D18 D25 D32 D39 D46 D53 D60 D67 D74 D81 D88 D95 D102 D109 D116 D123 D130 D137 D144 D151 D158 D165 D172 D179 D186 D193 D200 D207 D214 D221 D228 D235 D242 D249 D256 D263 D270 D277 D284 D291 D298 D305 D312 D319 D326 D333 D340 D347 D354 D361 D368 D375 D382 D389 D396 D403 D410 D417 D424 D431 D438 COM5 D5 D12 D19 D26 D33 D40 D47 D54 D61 D68 D75 D82 D89 D96 D103 D110 D117 D124 D131 D138 D145 D152 D159 D166 D173 D180 D187 D194 D201 D208 D215 D222 D229 D236 D243 D250 D257 D264 D271 D278 D285 D292 D299 D306 D313 D320 D327 D334 D341 D348 D355 D362 D369 D376 D383 D390 D397 D404 D411 D418 D425 D432 D439 COM6 D6 D13 D20 D27 D34 D41 D48 D55 D62 D69 D76 D83 D90 D97 D104 D111 D118 D125 D132 D139 D146 D153 D160 D167 D174 D181 D188 D195 D202 D209 D216 D223 D230 D237 D244 D251 D258 D265 D272 D279 D286 D293 D300 D307 D314 D321 D328 D335 D342 D349 D356 D363 D370 D377 D384 D391 D398 D405 D412 D419 D426 D433 D440 COM7 D7 D14 D21 D28 D35 D42 D49 D56 D63 D70 D77 D84 D91 D98 D105 D112 D119 D126 D133 D140 D147 D154 D161 D168 D175 D182 D189 D196 D203 D210 D217 D224 D231 D238 D245 D252 D259 D266 D273 D280 D287 D294 D301 D308 D315 D322 D329 D336 D343 D350 D357 D364 D371 D378 D385 D392 D399 D406 D413 D420 D427 D434 D441 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Display Data and Output Pin Correspondence – continued Output Pin COM8 / S64 COM7 / S65 COM6 / S66 COM5 / S67 S68 S69 OSC_IN/S70 COM1 D442 COM2 D443 COM3 D444 COM4 D445 COM5 D446 COM6 D447 COM7 D448 D449 D456 D463 D450 D457 D464 D451 D458 D465 D452 D459 D466 D453 D460 D467 D454 D461 D468 D455 D462 D469 (Note21) The Segment output Port function is assumed to be selected for the output pins – S1/P1/G1 to S9/P9/G9, KS1/S53 to KS6/S58, KI1/S59 to KI5/S63 and OSC_IN/S70. Also, COM7/S65, COM6/S66, COM5/S67 pins are used as Common outputs. To illustrate further, the states of the S21 output pin is given in the table below. Display data State of S21 output Pin D141 D142 D143 D144 D145 D146 D147 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 0 0 1 0 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 1 0 1 0 0 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 1 0 1 0 0 1 1 1 1 0 . 1 . 1 . 1 . 1 . 1 . 1 . 1 www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 LCD Segments corresponding to COM1 to COM7 are OFF. LCD Segment corresponding to COM7 is ON. LCD Segment corresponding to COM6 is ON. LCD Segments corresponding to COM6 and COM7 are ON. LCD Segment corresponding to COM5 is ON. LCD Segments corresponding to COM5 and COM7 are ON. LCD Segments corresponding to COM5 and COM6 are ON. LCD Segments corresponding to COM5, COM6 and COM7 are ON. LCD Segment corresponding to COM4 is ON. LCD Segments corresponding to COM4 and COM7 are ON. LCD Segments corresponding to COM4 and COM6 are ON LCD Segments corresponding to COM4, COM6 and COM7 are ON. LCD Segments corresponding to COM4 and COM5 are ON. LCD Segments corresponding to COM4, COM5, and COM7 are ON. LCD Segments corresponding to COM4, COM5, and COM6 are ON. LCD Segments corresponding to COM4, COM5, COM6 and COM7 are ON. LCD Segment corresponding to COM3 is ON. LCD Segments corresponding to COM3 and COM7 are ON. LCD Segments corresponding to COM3 and COM6 are ON. LCD Segments corresponding to COM3, COM6 and COM7 are ON. LCD Segments corresponding to COM3 and COM5 are ON. LCD Segments corresponding to COM3, COM5 and COM7 are ON. LCD Segments corresponding to COM3, COM5 and COM6 are ON. LCD Segments corresponding to COM3, COM5, COM6 and COM7 are ON. LCD Segments corresponding to COM3 and COM4 are ON. LCD Segments corresponding to COM3, COM4 and COM7 are ON. LCD Segments corresponding to COM3, COM4 and COM6 are ON. LCD Segments corresponding to COM3, COM4, COM6 and COM7 are ON. LCD Segments corresponding to COM3, COM4 and COM5 are ON. LCD Segments corresponding to COM3, COM4, COM5 and COM7 are ON. LCD Segments corresponding to COM3, COM4, COM5 and COM6 are ON. . LCD Segments corresponding to COM1 to COM7 are ON. 30/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Display Data and Output Pin Correspondence – continued 3. 1/5 duty Output Pin(Note22) S1/P1/G1 S2/P2/G2 S3/P3/G3 S4/P4/G4 S5/P5/G5 S6/P6/G6 S7/P7/G7 S8/P8/G8 S9/P9/G9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 KS1/S53 KS2/S54 KS3/S55 KS4/S56 KS5/S57 KS6/S58 KI1/S59 KI2/S60 KI3/S61 KI4/S62 KI5/S63 COM1 D1 D6 D11 D16 D21 D26 D31 D36 D41 D46 D51 D56 D61 D66 D71 D76 D81 D86 D91 D96 D101 D106 D111 D116 D121 D126 D131 D136 D141 D146 D151 D156 D161 D166 D171 D176 D181 D186 D191 D196 D201 D206 D211 D216 D221 D226 D231 D236 D241 D246 D251 D256 D261 D266 D271 D276 D281 D286 D291 D296 D301 D306 D311 www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 COM2 D2 D7 D12 D17 D22 D27 D32 D37 D42 D47 D52 D57 D62 D67 D72 D77 D82 D87 D92 D97 D102 D107 D112 D117 D122 D127 D132 D137 D142 D147 D152 D157 D162 D167 D172 D177 D182 D187 D192 D197 D202 D207 D212 D217 D222 D227 D232 D237 D242 D247 D252 D257 D262 D267 D272 D277 D282 D287 D292 D297 D302 D307 D312 COM3 D3 D8 D13 D18 D23 D28 D33 D38 D43 D48 D53 D58 D63 D68 D73 D78 D83 D88 D93 D98 D103 D108 D113 D118 D123 D128 D133 D138 D143 D148 D153 D158 D163 D168 D173 D178 D183 D188 D193 D198 D203 D208 D213 D218 D223 D228 D233 D238 D243 D248 D253 D258 D263 D268 D273 D278 D283 D288 D293 D298 D303 D308 D313 31/72 COM4 D4 D9 D14 D19 D24 D29 D34 D39 D44 D49 D54 D59 D64 D69 D74 D79 D84 D89 D94 D99 D104 D109 D114 D119 D124 D129 D134 D139 D144 D149 D154 D159 D164 D169 D174 D179 D184 D189 D194 D199 D204 D209 D214 D219 D224 D229 D234 D239 D244 D249 D254 D259 D264 D269 D274 D279 D284 D289 D294 D299 D304 D309 D314 COM5 D5 D10 D15 D20 D25 D30 D35 D40 D45 D50 D55 D60 D65 D70 D75 D80 D85 D90 D95 D100 D105 D110 D115 D120 D125 D130 D135 D140 D145 D150 D155 D160 D165 D170 D175 D180 D185 D190 D195 D200 D205 D210 D215 D220 D225 D230 D235 D240 D245 D250 D255 D260 D265 D270 D275 D280 D285 D290 D295 D300 D305 D310 D315 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Display Data and Output Pin Correspondence – continued Output Pin COM8/S64 COM7/S65 COM6/S66 COM5/S67 S68 S69 OSC_IN/S70 COM1 D316 D321 D326 COM2 D317 D322 D327 COM3 D318 D323 D328 COM4 D319 D324 D329 COM5 D320 D325 D330 D331 D336 D341 D332 D337 D342 D333 D338 D343 D334 D339 D344 D335 D340 D345 (Note22) The Segment output Port function is assumed to be selected for the output pins – S1/P1/G1 to S9/P9/G9, KS1/S53 to KS6/S58, KI1/S59 to KI5/S63 and OSC_IN/S70. Also, COM5/S67 pins are used as Common outputs. To illustrate further, the states of the S21 output pin is given in the table below. Display Data State of S21 output Pin D101 D102 D103 D104 D105 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 LCD Segments corresponding to COM1 to COM5 are OFF. LCD Segment corresponding to COM5 is ON. LCD Segment corresponding to COM4 is ON. LCD Segments corresponding to COM4 and COM5 are ON. LCD Segment corresponding to COM3 is ON. LCD Segments corresponding to COM3 and COM5 are ON. LCD Segments corresponding to COM3 and COM4 are ON. LCD Segments corresponding to COM3, COM4 and COM5 are ON. LCD Segment corresponding to COM2 is ON. LCD Segments corresponding to COM2 and COM5 are ON. LCD Segments corresponding to COM2 and COM4 are ON. LCD Segments corresponding to COM2, COM4 and COM5 are ON. LCD Segments corresponding to COM2 and COM3 are ON. LCD Segments corresponding to COM2, COM3, and COM5 are ON. LCD Segments corresponding to COM2, COM3, and COM4 are ON. LCD Segments corresponding to COM2, COM3, COM4 and COM5 are ON. LCD Segment corresponding to COM1 is ON. LCD Segments corresponding to COM1 and COM5 are ON. LCD Segments corresponding to COM1 and COM4 are ON. LCD Segments corresponding to COM1, COM4 and COM5 are ON. LCD Segments corresponding to COM1 and COM3 are ON. LCD Segments corresponding to COM1, COM3 and COM5 are ON. LCD Segments corresponding to COM1, COM3 and COM4 are ON. LCD Segments corresponding to COM1, COM3, COM4 and COM5 are ON. LCD Segments corresponding to COM1 and COM2 are ON. LCD Segments corresponding to COM1, COM2 and COM5 are ON. LCD Segments corresponding to COM1, COM2 and COM4 are ON. LCD Segments corresponding to COM1, COM2, COM4 and COM5 are ON. LCD Segments corresponding to COM1, COM2 and COM3 are ON. LCD Segments corresponding to COM1, COM2, COM3 and COM5 are ON. LCD Segments corresponding to COM1, COM2, COM3 and COM4 are ON. LCD Segments corresponding to COM1 to COM5 are ON. 32/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Display Data and Output Pin Correspondence – continued 4. 1/4 duty Output Pin(Note23) S1/P1/G1 S2/P2/G2 S3/P3/G3 S4/P4/G4 S5/P5/G5 S6/P6/G6 S7/P7/G7 S8/P8/G8 S9/P9/G9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 KS1/S53 KS2/S54 KS3/S55 KS4/S56 KS5/S57 KS6/S58 KI1/S59 KI2/S60 KI3/S61 KI4/S62 KI5/S63 COM1 D1 D5 D9 D13 D17 D21 D25 D29 D33 D37 D41 D45 D49 D53 D57 D61 D65 D69 D73 D77 D81 D85 D89 D93 D97 D101 D105 D109 D113 D117 D121 D125 D129 D133 D137 D141 D145 D149 D153 D157 D161 D165 D169 D173 D177 D181 D185 D189 D193 D197 D201 D205 D209 D213 D217 D221 D225 D229 D233 D237 D241 D245 D249 www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 COM2 D2 D6 D10 D14 D18 D22 D26 D30 D34 D38 D42 D46 D50 D54 D58 D62 D66 D70 D74 D78 D82 D86 D90 D94 D98 D102 D106 D110 D114 D118 D122 D126 D130 D134 D138 D142 D146 D150 D154 D158 D162 D166 D170 D174 D178 D182 D186 D190 D194 D198 D202 D206 D210 D214 D218 D222 D226 D230 D234 D238 D242 D246 D250 COM3 D3 D7 D11 D15 D19 D23 D27 D31 D35 D39 D43 D47 D51 D55 D59 D63 D67 D71 D75 D79 D83 D87 D91 D95 D99 D103 D107 D111 D115 D119 D123 D127 D131 D135 D139 D143 D147 D151 D155 D159 D163 D167 D171 D175 D179 D183 D187 D191 D195 D199 D203 D207 D211 D215 D219 D223 D227 D231 D235 D239 D243 D247 D251 33/72 COM4 D4 D8 D12 D16 D20 D24 D28 D32 D36 D40 D44 D48 D52 D56 D60 D64 D68 D72 D76 D80 D84 D88 D92 D96 D100 D104 D108 D112 D116 D120 D124 D128 D132 D136 D140 D144 D148 D152 D156 D160 D164 D168 D172 D176 D180 D184 D188 D192 D196 D200 D204 D208 D212 D216 D220 D224 D228 D232 D236 D240 D244 D248 D252 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Display Data and Output Pin Correspondence – continued Output Pin COM8/S64 COM7/S65 COM6/S66 COM5/S67 S68 S69 OSC_IN/S70 COM1 D253 D257 D261 D265 D269 D273 D277 COM2 D254 D258 D262 D266 D270 D274 D278 COM3 D255 D259 D263 D267 D271 D275 D279 COM4 D256 D260 D264 D268 D272 D276 D280 (Note23) The Segment output Port function is assumed to be selected for the output pins – S1/P1/G1 to S9/P9/G9, KS1/S53 to KS6/S58, KI1/S59 to KI5/S63 and OSC_IN/S70. To illustrate further, the states of the S21 output pin is given in the table below. Display Data State of S21 output Pin D81 D82 D83 D84 0 0 0 0 LCD Segments corresponding to COM1 to COM4 are OFF. 0 0 0 1 LCD Segment corresponding to COM4 is ON. 0 0 1 0 LCD Segment corresponding to COM3 is ON. 0 0 1 1 LCD Segments corresponding to COM3 and COM4 are ON. 0 1 0 0 LCD Segment corresponding to COM2 is ON. 0 1 0 1 LCD Segments corresponding to COM2 and COM4 are ON. 0 1 1 0 LCD Segments corresponding to COM2 and COM3 are ON. 0 1 1 1 LCD Segments corresponding to COM2, COM3 and COM4 are ON. 1 0 0 0 LCD Segment corresponding to COM1 is ON. 1 0 0 1 LCD Segments corresponding to COM1 and COM4 are ON. 1 0 1 0 LCD Segments corresponding to COM1 and COM3 are ON. 1 0 1 1 LCD Segments corresponding to COM1, COM3 and COM4 are ON. 1 1 0 0 LCD Segments corresponding to COM1 and COM2 are ON. 1 1 0 1 LCD Segments corresponding to COM1, COM2, and COM4 are ON. 1 1 1 0 LCD Segments corresponding to COM1, COM2, and COM3 are ON. 1 1 1 1 LCD Segments corresponding to COM1 to COM4 are ON. www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 34/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Display Data and Output Pin Correspondence – continued 5. 1/3 duty Output Pin(Note24) S1/P1/G1 S2/P2/G2 S3/P3/G3 S4/P4/G4 S5/P5/G5 S6/P6/G6 S7/P7/G7 S8/P8/G8 S9/P9/G9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 KS1/S53 KS2/S54 KS3/S55 KS4/S56 KS5/S57 KS6/S58 KI1/S59 KI2/S60 KI3/S61 KI4/S62 KI5/S63 COM1 D1 D4 D7 D10 D13 D16 D19 D22 D25 D28 D31 D34 D37 D40 D43 D46 D49 D52 D55 D58 D61 D64 D67 D70 D73 D76 D79 D82 D85 D88 D91 D94 D97 D100 D103 D106 D109 D112 D115 D118 D121 D124 D127 D130 D133 D136 D139 D142 D145 D148 D151 D154 D157 D160 D163 D166 D169 D172 D175 D178 D181 D184 D187 www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 COM2 D2 D5 D8 D11 D14 D17 D20 D23 D26 D29 D32 D35 D38 D41 D44 D47 D50 D53 D56 D59 D62 D65 D68 D71 D74 D77 D80 D83 D85 D89 D92 D95 D98 D101 D104 D107 D110 D113 D116 D119 D122 D125 D128 D131 D134 D137 D140 D143 D146 D149 D152 D155 D158 D161 D164 D167 D170 D173 D176 D179 D182 D185 D188 COM3 D3 D6 D9 D12 D15 D18 D21 D24 D27 D30 D33 D36 D39 D42 D45 D48 D51 D54 D57 D60 D63 D66 D69 D72 D75 D78 D81 D84 D87 D90 D93 D96 D99 D102 D105 D108 D111 D114 D117 D120 D123 D126 D129 D132 D135 D138 D141 D144 D147 D150 D153 D156 D159 D162 D165 D168 D171 D174 D177 D180 D183 D186 D189 35/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Display Data and Output Pin Correspondence – continued Output Pin COM8/S64 COM7/S65 COM6/S66 COM5/S67 S68 S69 OSC_IN/S70 COM1 D190 D193 D196 D199 D202 D205 D208 COM2 D191 D194 D197 D200 D203 D206 D209 COM3 D192 D195 D198 D201 D204 D207 D210 (Note24) The Segment output Port function is assumed to be selected for the output pins – S1/P1/G1 to S9/P9/G9, KS1/S53 to KS6/S58, KI1/S59 to KI5/S63 and OSC_IN/S70. To illustrate further, the states of the S21 output pin is given in the table below. Display Data State of S21 output Pin D61 D62 D63 0 0 0 LCD Segments corresponding to COM1 to COM3 are OFF. 0 0 1 LCD Segment corresponding to COM3 is ON. 0 1 0 LCD Segment corresponding to COM2 is ON. 0 1 1 LCD Segments corresponding to COM2 and COM3 are ON. 1 0 0 LCD Segment corresponding to COM1 is ON. 1 0 1 LCD Segments corresponding to COM1 and COM3 are ON. 1 1 0 LCD Segments corresponding to COM1 and COM2 are ON. 1 1 1 LCD Segments corresponding to COM1 to COM3 are ON. www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 36/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Display Data and Output Pin Correspondence – continued 6. Static Output Pin(Note25) S1/P1/G1 S2/P2/G2 S3/P3/G3 S4/P4/G4 S5/P5/G5 S6/P6/G6 S7/P7/G7 S8/P8/G8 S9/P9/G9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 KS1/S53 KS2/S54 KS3/S55 KS4/S56 KS5/S57 KS6/S58 KI1/S59 KI2/S60 KI3/S61 KI4/S62 KI5/S63 COM1 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 37/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Display Data and Output Pin Correspondence – continued Output Pin COM8/S64 COM7/S65 COM6/S66 COM5/S67 S68 S69 OSC_IN/S70 COM1 D64 D65 D66 D67 D68 D69 D70 (Note25) The Segment output Port function is assumed to be selected for the output pins – S1/P1/G1 to S9/P9/G9, KS1/S53 to KS6/S58, KI1/S59 to KI5/S63 and OSC_IN/S70. To illustrate further, the states of the S21 output pin is given in the table below. Display Data State of S21 output Pin D21 0 LCD Segment corresponding to COM1 is OFF. 1 LCD Segment corresponding to COM1 is ON. www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 38/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Serial Data Output 1. When SCL is stopped at the low level(Note26) SCE SCL SDI 1 1 0 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 SDO X KD1 KD2 KD27 KD28 KD29 KD30 PA Output Data Figure 19. Serial Data Output Format (Note26) 1. X=Don’t care 2. B0 to B3, A0 to A3: Serial Interface address 2. When SCL is stopped at the high level(Note27) SCE SCL SDI 1 1 0 0 B0 B1 B2 B3 0 0 1 0 A0 A1 A2 A3 SDO KD1 KD2 KD3 KD28 KD29 KD30 PA X Output Data Figure 20. Serial Data Output Format (Note27) 1. X=Don’t care 2. B0 to B3, A0 to A3: Serial Interface address 3. Serial Interface address: 43H 4. KD1 to KD30: Key data 5. PA: Power-saving acknowledge data 6. If a key data read operation is executed when SDO is high, the read key data (KD1 to KD30) and Power-saving acknowledge data (PA) will be invalid. www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 39/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Output Data 1. KD1 to KD30: KEY DATA When a key matrix of up to 30 keys is formed from the KS1 to KS6 output pins and the KI1 to KI5 input pins and one of those keys is pressed, the key output data corresponding to that key will be set to 1. The table shows the relationship between those pins and the key data bits. Item KS1 KS2 KS3 KS4 KS5 KS6 KI1 KD1 KD6 KD11 KD16 KD21 KD26 KI2 KD2 KD7 KD12 KD17 KD22 KD27 KI3 KD3 KD8 KD13 KD18 KD23 KD28 KI4 KD4 KD9 KD14 KD19 KD24 KD29 KI5 KD5 KD10 KD15 KD20 KD25 KD30 2. PA: Power-saving Acknowledge Data This output data is set to the state of normal mode or Power-saving mode. PA is set to 1 in the Power-saving mode and to 0 in the normal mode. Power-saving Mode Power-saving mode is activated when least one of control data BU0 or BU1 or BU2 is set to 1. All Segment and Common outputs will go low. The oscillation circuit will stop (It can be restarted by a key press), thus reducing power consumption. This mode can be disabled when control data bits BU0, BU1 and BU2 are all set to 0. However, note that the S1/P1/G1 to S9/P9/G9 outputs can still be used as General-Purpose output ports according to the state of the P0 to P2 control data bits, even in Power-saving mode. (See Control Data Functions.) www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 40/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Key Scan Operation Functions 1. Key Scan Timing The key scan period is 4608T(s). To reliably determine the on/off state of the keys, the BU97550KV-M scans the keys twice and determines that a key has been pressed when the key data agrees. Then it outputs a key data read request (a low level on SDO) 9840T(s) after starting a key scan. If the key data does not agree and a key was pressed at that point, it scans the keys again. Thus the BU97550KV-M cannot detect a key press shorter than 9840T(s). KS1 * KS2 * KS3 * KS4 * KS5 * KS6 * 1 1 2 * 2 3 * 3 * 4 4 * 5 5 6 * 6 9216T[S] T= * 1 fosc Figure 21. Key Scan Timing(Note28) (Note28) In Power-saving mode, the “H” or “L” state of these pins is determined by the BU0 to BU2 bits in the control data. Key scan output signals are not output from pins that are set “L”. 2. In Normal Mode The pins KS1 to KS6 output are set “H”. When a key is pressed a key scan is started and the keys are scanned until all keys are released. Multiple key presses are recognized by determining whether multiple key data bits are set. If a key is pressed for longer than 9840T(s) (Where T=1/fosc) the BU97550KV-M outputs a key data read request (a low level on SDO) to the controller. The controller acknowledges this request and reads the key data. However, if SCE is high during a serial data transfer, SDO will be set high. After the controller reads the key data, the key data read request is cleared (SDO is set high) and the BU97550KV-M performs another key scan. Also note that SDO, being an open-drain output, requires a pull-up resistor (between 1kΩ to 10kΩ). Key Input 1 Key Input 2 Key scan 9840T[S] 9840T[S] 9840T[S] SCE Serial data transf er Serial data transf er Key address(43H) Serial data transf er Key address Key address SDI SDO Key data read Key data read Key data read request Key data read request Key data read Key data read request 1 T= f osc Figure 22. Key scan operation in normal mode www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 41/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Key Scan Operation Functions – continued 3. In Power-saving Mode The pins KS1 to KS6 output high or low level by the BU0 to BU2 bits in the control data. (See the control data Functions for details.) If a key on one of the lines corresponding to a KS1 to KS6 pin which is set high is pressed, the oscillator on the OSC_IN pin is started and a key scan is performed. Keys are scanned until all keys are released. Multiple key presses are recognized by determining whether multiple key data bits are set. If a key is pressed for longer than 9840T(s)(Where T=1/fosc) the BU97550KV-M outputs a key data read request (a low level on SDO) to the controller. The controller acknowledges this request and reads the key data. However, if SCE is high during a serial data transfer, SDO will be set high. After the controller reads the key data, the key data read request is cleared (SDO is set high) and the BU97550KV-M performs another key scan. However, this does not clear Power-saving mode. Also note that SDO, being an open-drain output, requires a pull-up resistor (between 1 kΩ to 10kΩ). Power-saving mode key scan example Example: BU0=0, BU1=0, BU2=1 (only KS6 high level output) (L)KS1 (L)KS2 (L)KS3 When any one of these keys is pressed, the oscillator on the OSC pin is started and the keys are scanned. (L)KS4 (L)KS5 (H) (L)KS6 (Note29) Kl1 Kl2 Kl3 Kl4 Kl5 (Note 29) These diodes are required to reliable recognize multiple key presses on the KS6 line when Power-saving mode state with only KS6 high, as in the above example. That is, these diodes prevent incorrect operations due to sneak currents in the KS6 key scan output signal when keys on the KS1 to KS5 lines are pressed at the same time. Key Input 2 (KS6 line) Key scan 9840T[S] 9840T[S] SCE Serial data transf er Serial data transf er Key address(43H) Serial data transf er Key address SDI SDO Key data read Key data read Key data read request Key data read request T= 1 f osc Figure 23. Key scan operation in Power-saving mode 4. Multiple Key Presses Although the BU97550KV-M is capable of key scanning without inserting diodes for dual key presses, triple key presses on the KI1 to KI5 input pin lines, or multiple key presses on the KS1 to KS6 output pin lines, multiple presses other than these cases may result in keys that were not pressed recognized as having been pressed. Therefore, a diode must be inserted in series with each key. Applications that do not recognize multiple key presses of three or more keys should check the key data for three or more 1 bit and ignore such data. www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 42/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Key Scan Operation Functions – continued 5. Controller Key Data Read Techniques When the controller receives a key data read request from BU97550KV-M, it performs a key data read acquisition operation using either the Timer Based Key Data Acquisition or the Interrupt Based Key Data Acquisition. 6. Timer Based Key Data Acquisition Technique Under the Timer Based Key Data Acquisition Technique, the controller uses a timer to determine the states of the keys (on or off) and read the key data. Please refer to the flowchart below. SCE = 「L」 NO SDO = 「L」 YES Key data read processing Key data read processing: Refer to “Serial Data Output” Figure 24. Flowchart In this technique, the controller uses a timer to determine key on/off states and read the key data. The controller must check the SDO state when SCE is low every t7 period without fail. If SDO is low, the controller recognizes that a key has been pressed and executes the key data read operation. The period t7 in this technique must satisfy the following condition. t7>t4+t5+t6 If a key data read operation is executed when SDO is high, the read key data (KD1 to KD30) and Power-saving acknowledge data (PA) will be invalid. Key on Key on Key Input 1 Key scan t3 t3 t4 t3 SCE t6 t6 t6 SDI t5 t5 t5 Key data read SDO Key data read request t7 Controller determination (key on) t7 Controller determination (key on) t7 t7 Controller determination (key on) Controller determination (key on) Controller determination (key on) t3: Key scan execution time when the key data agreed for two key scans. (9840T[s]) t4: Key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (19680T[s]) T = 1 / fosc t5: Key address (43H) transfer time t6: Key data read time Figure 25. Timer based key data read operation www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 43/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Key Scan Operation Functions – continued 7. Interrupt Based Key Data Acquisition Technique Under the Interrupt Based Key Data Acquisition Technique, the controller uses interrupts to determine the state of the keys (on or off) and read the key data. Please refer to the flow chart diagram below. SCE = 「L 」 SDO = 「L 」 NO YES Key data read processing Wait for at least t8 NO SDO = 「H 」 YES Key off Key data read processing: Refer to “Serial Data Output” Figure 26. Flowchart www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 44/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Key Scan Operation Functions – continued In this technique, the controller uses interrupts to determine key on/off states and read the key data. The controller must check the SDO state when SCE is low. If SDO is low, the controller recognizes that a key has been pressed and executes the key data read operation. After that the next key on/off determination is performed after the time t8 has elapsed by checking the SDO state when SCE is low and reading the key data. The period t8 in this technique must satisfy t8 > t4. If a key data read operation is executed when SDO is high, the read key data (KD1 to KD30) and power-saving acknowledge data (PA) will be invalid. Key on Key on Key Input 1 Key scan t3 t3 t4 t3 SCE t6 t6 t6 t6 SDI t5 t5 t5 t5 Key data read SDO Key data read request Controller determination (key on) Controller determination (key on) t8 t8 t8 t8 Controller determination (key on) Controller determination (key on) Controller determination (key on) Controller determination (key on) t3: Key scan execution time when the key data agreed for two key scans. (9840T[s]) t4: Key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (19680T[s]) T = 1 / fosc t5: Key address (43H) transfer time t6: Key data read time Figure 27. Interrupt Based Key Data Read Operation www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 45/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) LCD Driving Waveforms 1. Line Inversion 1/8-Duty 1/4-Bias Drive Scheme fo[Hz] VLCD VLCD1 VLCD2 COM1 VLCD3 0V VLCD VLCD1 VLCD2 COM2 VLCD3 0V VLCD VLCD1 VLCD2 COM3 VLCD3 0V VLCD VLCD1 VLCD2 COM4 VLCD3 0V VLCD VLCD1 VLCD2 COM5 VLCD3 0V VLCD VLCD1 VLCD2 COM6 VLCD3 0V VLCD VLCD1 VLCD2 COM7 VLCD3 0V VLCD VLCD1 VLCD2 COM8 VLCD3 0V VLCD LCD driver output w hen all LCD VLCD1 Segment corresponding to COM1, COM2, COM3 VLCD2 COM4, COM5, COM6, COM7 and COM8 are off VLCD3 0V VLCD LCD driver output w hen only LCD Segments VLCD1 corresponding to COM1 is on VLCD2 VLCD3 0V VLCD LCD driver output w hen only LCD Segments VLCD1 corresponding to COM2 is on. VLCD2 VLCD3 0V VLCD LCD driver output w hen only LCD Segments VLCD1 corresponding to COM3 is on. VLCD2 VLCD3 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM1 and COM3 are on VLCD2 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM2 and COM3 are on VLCD2 VLCD3 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM1, COM2 and COM3 are on VLCD2 VLCD3 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM1, COM2, COM3 VLCD2 and COM4 are on VLCD3 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM5, COM6, COM7 VLCD2 and COM8 are on VLCD3 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM1, COM2 ,COM3, COM4 VLCD2 COM5, COM6, COM7 and COM8 are on VLCD3 0V Figure 28. LCD Waveform (Line Inversion, 1/8 DUTY, 1/4 BIAS) www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 46/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) LCD Driving Waveforms – continued 2. Line Inversion 1/8-Duty 1/3-Bias Drive Scheme fo[Hz] VLCD VLCD1 VLCD2 COM1 0V VLCD VLCD1 VLCD2 COM2 0V VLCD VLCD1 VLCD2 COM3 0V VLCD VLCD1 VLCD2 COM4 0V VLCD VLCD1 VLCD2 COM5 0V VLCD VLCD1 VLCD2 COM6 0V VLCD VLCD1 VLCD2 COM7 0V VLCD VLCD1 VLCD2 COM8 0V VLCD LCD driver output w hen all LCD VLCD1 Segment corresponding to COM1, COM2, COM3 VLCD2 COM4, COM5, COM6, COM7, and COM8 are off 0V VLCD LCD driver output w hen only LCD Segments VLCD1 corresponding to COM1 is on VLCD2 0V VLCD LCD driver output w hen only LCD Segments VLCD1 corresponding to COM2 is on. VLCD2 0V VLCD LCD driver output w hen only LCD Segments VLCD1 corresponding to COM1 and COM2 are on. VLCD2 0V VLCD LCD driver output w hen only LCD Segments VLCD1 corresponding to COM3 is on. VLCD2 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM1 and COM3 are on VLCD2 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM2 and COM3 are on VLCD2 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM1, COM2 and COM3 are on VLCD2 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM1, COM2, COM3 VLCD2 and COM4 are on 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM5, COM6, COM7 VLCD2 and COM8 are on 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM1, COM2 ,COM3, COM4 VLCD2 COM5, COM6, COM7 and COM8 are on 0V Figure 29. LCD Waveform (Line Inversion, 1/8 DUTY, 1/3 BIAS) www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 47/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) LCD Driving Waveforms – continued 3. Line Inversion 1/8-Duty 1/2-Bias Drive Scheme fo[Hz] VLCD VLCD1 VLCD2 COM1 VLCD3 0V VLCD VLCD1 VLCD2 COM2 VLCD3 0V VLCD VLCD1 VLCD2 COM3 VLCD3 0V VLCD VLCD1 VLCD2 COM4 VLCD3 0V VLCD VLCD1 VLCD2 COM5 VLCD3 0V VLCD VLCD1 VLCD2 COM6 VLCD3 0V VLCD VLCD1 VLCD2 COM7 VLCD3 0V VLCD VLCD1 VLCD2 COM8 VLCD3 0V VLCD LCD driver output w hen all LCD VLCD1 Segment corresponding to COM1, COM2, COM3 VLCD2 COM4, COM5, COM6, COM7 and COM8 are off VLCD3 0V VLCD LCD driver output w hen only LCD Segments VLCD1 corresponding to COM1 is on VLCD2 VLCD3 0V VLCD LCD driver output w hen only LCD Segments VLCD1 corresponding to COM2 is on. VLCD2 VLCD3 0V VLCD LCD driver output w hen only LCD Segments VLCD1 corresponding to COM3 is on. VLCD2 VLCD3 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM2 and COM3 are on VLCD2 VLCD3 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM1, COM2 and COM3 are on VLCD2 VLCD3 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM1, COM2, COM3 VLCD2 and COM4 are on VLCD3 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM5, COM6, COM7 VLCD2 and COM8 are on VLCD3 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM1, COM2 ,COM3, COM4 VLCD2 COM5, COM6, COM7 and COM8 are on VLCD3 0V Figure 30. LCD Waveform (Line Inversion, 1/8 DUTY, 1/2 BIAS) www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 48/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) LCD Driving Waveforms – continued 4. Line Inversion 1/7-Duty 1/4-Bias Drive Scheme fo[Hz] VLCD VLCD1 VLCD2 COM1 VLCD3 0V VLCD VLCD1 VLCD2 COM2 VLCD3 0V VLCD VLCD1 VLCD2 COM3 VLCD3 0V VLCD VLCD1 VLCD2 COM4 VLCD3 0V VLCD VLCD1 VLCD2 COM5 VLCD3 0V VLCD VLCD1 VLCD2 COM6 VLCD3 0V VLCD VLCD1 VLCD2 COM7 VLCD3 0V VLCD LCD driver output w hen all LCD VLCD1 Segment corresponding to COM1, COM2, COM3 VLCD2 COM4, COM5, COM6 and COM7 are off VLCD3 0V VLCD LCD driver output w hen only LCD Segments VLCD1 corresponding to COM1 is on VLCD2 VLCD3 0V VLCD LCD driver output w hen only LCD Segments VLCD1 corresponding to COM2 is on. VLCD2 VLCD3 0V VLCD LCD driver output w hen only LCD Segments VLCD1 corresponding to COM1 and COM2 are on. VLCD2 VLCD3 0V VLCD LCD driver output w hen only LCD Segments VLCD1 corresponding to COM3 is on. VLCD2 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM1, COM2 and COM3 are on VLCD2 VLCD3 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM1, COM2, COM3 VLCD2 and COM4 are on VLCD3 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM5, COM6, VLCD2 and COM7 are on VLCD3 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM1, COM2 ,COM3, COM4 VLCD2 COM5, COM6, and COM7 are on VLCD3 0V Figure 31. LCD Waveform (Line Inversion, 1/7 DUTY, 1/4 BIAS) www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 49/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) LCD Driving Waveforms – continued 5. Line Inversion 1/5-Duty 1/3-Bias Drive Scheme fo[Hz] VLCD VLCD1 VLCD2 COM1 0V VLCD VLCD1 VLCD2 COM2 0V VLCD VLCD1 VLCD2 COM3 0V VLCD VLCD1 VLCD2 COM4 0V VLCD VLCD1 VLCD2 COM5 0V VLCD LCD driver output w hen all LCD VLCD1 Segment corresponding to COM1, VLCD2 COM2, COM3, COM4 and COM5 are off 0V VLCD LCD driver output w hen only LCD Segments VLCD1 corresponding to COM1 is on VLCD2 0V VLCD LCD driver output w hen only LCD Segments VLCD1 corresponding to COM2 is on. VLCD2 0V VLCD LCD driver output w hen only LCD Segments VLCD1 corresponding to COM1 and COM2 are on. VLCD2 0V VLCD LCD driver output w hen only LCD Segments VLCD1 corresponding to COM3 is on. VLCD2 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM1 and COM3 are on VLCD2 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM2 and COM3 are on VLCD2 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM1, COM2 and COM3 are on VLCD2 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM1, COM2, COM3 VLCD2 and COM4 are on 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM1, COM2 ,COM3 VLCD2 COM4 and COM5 are on 0V Figure 32. LCD Waveform (Line Inversion, 1/5 DUTY, 1/3 BIAS) www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 50/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) LCD Driving Waveforms – continued 6. Line Inversion 1/5-Duty 1/2-Bias Drive Scheme fo[Hz] VLCD VLCD1, VLCD2 COM1 0V VLCD VLCD1, VLCD2 COM2 0V VLCD VLCD1, VLCD2 COM3 0V VLCD VLCD1, VLCD2 COM4 0V VLCD VLCD1, VLCD2 COM5 0V LCD driver output w hen all LCD VLCD Segment corresponding to COM1, VLCD1, VLCD2 COM2, COM3, COM4 and COM5 are off 0V VLCD LCD driver output w hen only LCD Segments VLCD1, VLCD2 corresponding to COM1 is on 0V VLCD LCD driver output w hen only LCD Segments VLCD1, VLCD2 corresponding to COM2 is on. 0V VLCD LCD driver output w hen only LCD Segments VLCD1, VLCD2 corresponding to COM1 and COM2 are on. 0V VLCD LCD driver output w hen only LCD Segments VLCD1, VLCD2 corresponding to COM3 is on. 0V VLCD LCD driver output w hen LCD Segments VLCD1, VLCD2 corresponding to COM1 and COM3 are on 0V VLCD LCD driver output w hen LCD Segments VLCD1, VLCD2 corresponding to COM2 and COM3 are on 0V VLCD LCD driver output w hen LCD Segments VLCD1, VLCD2 corresponding to COM1, COM2 and COM3 are on 0V VLCD LCD driver output w hen LCD Segments VLCD1, VLCD2 corresponding to COM4 is on 0V VLCD LCD driver output w hen LCD Segments VLCD1, VLCD2 corresponding to COM2 and COM4 are on 0V VLCD LCD driver output w hen LCD Segments VLCD1, VLCD2 corresponding to COM1, COM2, COM3 0V and COM4 are on VLCD VLCD1, VLCD2 0V LCD driver output w hen LCD Segments corresponding to COM1, COM2, COM3, COM4 and COM5 are on Figure 33. LCD Waveform (Line Inversion, 1/5 DUTY, 1/2 BIAS) www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 51/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) LCD Driving Waveforms – continued 7. Line Inversion 1/4-Duty 1/3-Bias Drive Scheme fo[Hz] VLCD VLCD1 VLCD2 COM1 0V VLCD VLCD1 VLCD2 COM2 0V VLCD VLCD1 VLCD2 COM3 0V VLCD VLCD1 VLCD2 COM4 0V VLCD LCD driver output w hen all LCD VLCD1 Segment corresponding to COM1, VLCD2 COM2, COM3 and COM4 are off 0V VLCD LCD driver output w hen only LCD Segments VLCD1 corresponding to COM1 is on VLCD2 0V VLCD LCD driver output w hen only LCD Segments VLCD1 corresponding to COM2 is on. VLCD2 0V VLCD LCD driver output w hen only LCD Segments VLCD1 corresponding to COM1 and COM2 are on. VLCD2 0V VLCD LCD driver output w hen only LCD Segments VLCD1 corresponding to COM3 is on. VLCD2 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM1 and COM3 are on VLCD2 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM2 and COM3 are on VLCD2 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM1, COM2 and COM3 are on VLCD2 0V LCD driver output w hen only LCD Segments VLCD1 corresponding to COM4 is on. VLCD2 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM2 and COM4 are on VLCD2 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM1, COM2, COM3 VLCD2 and COM4 are on 0V Figure 34. LCD Waveform (Line Inversion, 1/4 DUTY, 1/3 BIAS) www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 52/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) LCD Driving Waveforms – continued 8. Line Inversion 1/4-Duty 1/2-Bias Drive Scheme fo[Hz] VLCD VLCD1, VLCD2 COM1 0V VLCD VLCD1, VLCD2 COM2 0V VLCD VLCD1, VLCD2 COM3 0V VLCD VLCD1, VLCD2 COM4 0V LCD driver output w hen all LCD VLCD Segment corresponding to COM1, VLCD1, VLCD2 COM2, COM3 and COM4 are off 0V VLCD LCD driver output w hen only LCD Segments VLCD1, VLCD2 corresponding to COM1 is on 0V VLCD LCD driver output w hen only LCD Segments VLCD1, VLCD2 corresponding to COM2 is on. 0V VLCD LCD driver output w hen only LCD Segments VLCD1, VLCD2 corresponding to COM1 and COM2 are on. 0V VLCD LCD driver output w hen only LCD Segments VLCD1, VLCD2 corresponding to COM3 is on. 0V VLCD LCD driver output w hen LCD Segments VLCD1, VLCD2 corresponding to COM1 and COM3 are on 0V VLCD LCD driver output w hen LCD Segments VLCD1, VLCD2 corresponding to COM2 and COM3 are on 0V VLCD LCD driver output w hen LCD Segments VLCD1, VLCD2 corresponding to COM1, COM2 and COM3 are on 0V VLCD LCD driver output w hen LCD Segments VLCD1, VLCD2 corresponding to COM4 is on 0V VLCD LCD driver output w hen LCD Segments VLCD1, VLCD2 corresponding to COM2 and COM4 are on 0V VLCD LCD driver output w hen LCD Segments VLCD1, VLCD2 corresponding to COM1, COM2, COM3 0V and COM4 are on Figure 35. LCD Waveform (Line Inversion, 1/4 DUTY, 1/2 BIAS) www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 53/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) LCD Driving Waveforms – continued 9. Line Inversion 1/3-Duty 1/3-Bias Drive Scheme fo[Hz] VLCD VLCD1 VLCD2 COM1 0V VLCD VLCD1 VLCD2 COM2 0V VLCD VLCD1 VLCD2 COM3 0V VLCD LCD driver output w hen all LCD VLCD1 Segment corresponding to COM1, VLCD2 COM2 and COM3 are off 0V VLCD LCD driver output w hen only LCD Segments VLCD1 corresponding to COM1 is on VLCD2 0V VLCD LCD driver output w hen only LCD Segments VLCD1 corresponding to COM2 is on. VLCD2 0V VLCD LCD driver output w hen only LCD Segments VLCD1 corresponding to COM1 and COM2 are on. VLCD2 0V VLCD LCD driver output w hen only LCD Segments VLCD1 corresponding to COM3 is on. VLCD2 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM1 and COM3 are on VLCD2 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM2 and COM3 are on VLCD2 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM1, COM2 and COM3 are on VLCD2 0V Figure 36. LCD Waveform (Line Inversion, 1/3 DUTY, 1/3 BIAS) (Note30) (Note30) COM4 function is same as COM1 at 1/3 duty. www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 54/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) LCD Driving Waveforms – continued 10. Line Inversion 1/3-Duty 1/2-Bias Drive Scheme fo[Hz] VLCD VLCD1, VLCD2 COM1 0V VLCD VLCD1, VLCD2 COM2 0V VLCD VLCD1, VLCD2 COM3 0V LCD driver output w hen all LCD VLCD Segment corresponding to COM1, VLCD1, VLCD2 COM2 and COM3 are off 0V VLCD LCD driver output w hen only LCD Segments VLCD1, VLCD2 corresponding to COM1 is on 0V VLCD LCD driver output w hen only LCD Segments VLCD1, VLCD2 corresponding to COM2 is on. 0V VLCD LCD driver output w hen only LCD Segments VLCD1, VLCD2 corresponding to COM1 and COM2 are on. 0V VLCD LCD driver output w hen only LCD Segments VLCD1, VLCD2 corresponding to COM3 is on. 0V VLCD LCD driver output w hen LCD Segments VLCD1, VLCD2 corresponding to COM1 and COM3 are on 0V VLCD LCD driver output w hen LCD Segments VLCD1, VLCD2 corresponding to COM2 and COM3 are on 0V VLCD LCD driver output w hen LCD Segments VLCD1, VLCD2 corresponding to COM1, COM2 and COM3 are on 0V Figure 37. LCD Waveform (Line Inversion, 1/3 DUTY, 1/2 BIAS) (Note31) (Note31) COM4 function is same as COM1 at 1/3 duty. www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 55/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) LCD Driving Waveforms – continued 11. Line Inversion Static Drive Scheme fo[Hz] VLCD COM1 0V VLCD LCD driver output w hen all LCD Segments corresponding to COM1 is off 0V VLCD LCD driver output w hen all LCD Segments corresponding to COM1 is on 0V Figure 38. LCD Waveform (Line Inversion, Static) (Note32) (Note32) COM2, COM3 and COM4 function are same as COM1 at Static. www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 56/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) LCD Driving Waveforms – continued 12. Frame Inversion, 1/8-Duty 1/4-Bias Drive Scheme fo[Hz] VLCD VLCD1 VLCD2 COM1 VLCD3 0V VLCD VLCD1 VLCD2 COM2 VLCD3 0V VLCD VLCD1 VLCD2 COM3 VLCD3 0V VLCD VLCD1 VLCD2 COM4 VLCD3 0V VLCD VLCD1 VLCD2 COM5 VLCD3 0V VLCD VLCD1 VLCD2 COM6 VLCD3 0V VLCD VLCD1 VLCD2 COM7 VLCD3 0V VLCD VLCD1 VLCD2 COM8 VLCD3 0V VLCD LCD driver output w hen all LCD VLCD1 Segment corresponding to COM1, COM2, COM3, VLCD2 COM4 COM5, COM6 COM7 and COM8 are off VLCD3 0V VLCD LCD driver output w hen only LCD Segments VLCD1 corresponding to COM1 is on VLCD2 VLCD3 0V VLCD LCD driver output w hen only LCD Segments VLCD1 corresponding to COM2 is on. VLCD2 VLCD3 0V VLCD LCD driver output w hen only LCD Segments VLCD1 corresponding to COM1 and COM2 are on. VLCD2 VLCD3 0V VLCD LCD driver output w hen only LCD Segments VLCD1 corresponding to COM3 is on. VLCD2 VLCD3 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM1, COM2 and COM3 are on VLCD2 VLCD3 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM1, COM2, COM3 VLCD2 and COM4 are on VLCD3 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM5, COM6, COM7 VLCD2 and COM8 are on VLCD3 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM1, COM2, COM3, COM4 VLCD2 COM5, COM6, COM7 and COM8 are on VLCD3 0V Figure 39. LCD Waveform (Frame Inversion, 1/8 DUTY, 1/4BIAS) www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 57/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) LCD Driving Waveforms – continued 13. Frame Inversion 1/5-Duty 1/3-Bias Drive Scheme fo[Hz] VLCD VLCD1 VLCD2 COM1 0V VLCD VLCD1 VLCD2 COM2 0V VLCD VLCD1 VLCD2 COM3 0V VLCD VLCD1 VLCD2 COM4 0V VLCD VLCD1 VLCD2 COM5 0V VLCD LCD driver output w hen all LCD VLCD1 Segment corresponding to COM1, VLCD2 COM2, COM3, COM4 and COM5 are off 0V VLCD LCD driver output w hen only LCD Segments VLCD1 corresponding to COM1 is on VLCD2 0V VLCD LCD driver output w hen only LCD Segments VLCD1 corresponding to COM2 is on. VLCD2 0V VLCD LCD driver output w hen only LCD Segments VLCD1 corresponding to COM1 and COM2 are on. VLCD2 0V VLCD LCD driver output w hen only LCD Segments VLCD1 corresponding to COM3 is on. VLCD2 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM1 and COM3 are on VLCD2 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM2 and COM3 are on VLCD2 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM1, COM2 and COM3 are on VLCD2 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM1, COM2, COM3 VLCD2 and COM4 are on 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM1, COM2, COM3, VLCD2 COM4 and COM5 are on 0V Figure 40. LCD Waveform (Frame Inversion, 1/5 DUTY, 1/3BIAS) www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 58/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) LCD Driving Waveforms – continued 14. Frame Inversion 1/5-Duty 1/2-Bias Drive Scheme fo[Hz] VLCD VLCD1, VLCD2 COM1 0V VLCD VLCD1, VLCD2 COM2 0V VLCD VLCD1, VLCD2 COM3 0V VLCD VLCD1, VLCD2 COM4 0V VLCD VLCD1, VLCD2 COM5 0V LCD driver output w hen all LCD VLCD Segment corresponding to COM1, VLCD1, VLCD2 COM2, COM3, COM4 and COM5 are off 0V VLCD LCD driver output w hen only LCD Segments VLCD1, VLCD2 corresponding to COM1 is on 0V VLCD LCD driver output w hen only LCD Segments VLCD1, VLCD2 corresponding to COM2 is on. 0V VLCD LCD driver output w hen only LCD Segments VLCD1, VLCD2 corresponding to COM1 and COM2 are on. 0V VLCD LCD driver output w hen only LCD Segments VLCD1, VLCD2 corresponding to COM3 is on. 0V VLCD LCD driver output w hen LCD Segments VLCD1, VLCD2 corresponding to COM1 and COM3 are on 0V VLCD LCD driver output w hen LCD Segments VLCD1, VLCD2 corresponding to COM2 and COM3 are on 0V VLCD LCD driver output w hen LCD Segments VLCD1, VLCD2 corresponding to COM1, COM2 and COM3 are on 0V VLCD LCD driver output w hen LCD Segments VLCD1, VLCD2 corresponding to COM4 is on 0V VLCD LCD driver output w hen LCD Segments VLCD1, VLCD2 corresponding to COM2 and COM4 are on 0V VLCD LCD driver output w hen LCD Segments VLCD1, VLCD2 corresponding to COM1, COM2, COM3 0V and COM4 are on VLCD VLCD1, VLCD2 0V LCD driver output w hen LCD Segments corresponding to COM1, COM2, COM3, COM4 and COM5 are on Figure 41. LCD Waveform (Frame Inversion, 1/5 DUTY, 1/2BIAS) www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 59/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) LCD Driving Waveforms – continued 15. Frame Inversion 1/4-Duty 1/3-Bias Drive Scheme fo[Hz] VLCD VLCD1 VLCD2 COM1 0V VLCD VLCD1 VLCD2 COM2 0V VLCD VLCD1 VLCD2 COM3 0V VLCD VLCD1 VLCD2 COM4 0V VLCD LCD driver output w hen all LCD VLCD1 Segment corresponding to COM1, VLCD2 COM2, COM3 and COM4 are off 0V VLCD LCD driver output w hen only LCD Segments VLCD1 corresponding to COM1 is on VLCD2 0V VLCD LCD driver output w hen only LCD Segments VLCD1 corresponding to COM2 is on. VLCD2 0V VLCD LCD driver output w hen only LCD Segments VLCD1 corresponding to COM1 and COM2 are on. VLCD2 0V VLCD LCD driver output w hen only LCD Segments VLCD1 corresponding to COM3 is on. VLCD2 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM1 and COM3 are on VLCD2 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM2 and COM3 are on VLCD2 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM1, COM2 and COM3 are on VLCD2 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM1, COM2, COM3 VLCD2 and COM4 are on 0V Figure 42. LCD Waveform (Frame Inversion, 1/4 DUTY, 1/3BIAS) www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 60/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) LCD Driving Waveforms – continued 16. Frame Inversion 1/4-Duty 1/2-Bias Drive Scheme fo[Hz] VLCD VLCD1, VLCD2 COM1 0V VLCD VLCD1, VLCD2 COM2 0V VLCD VLCD1, VLCD2 COM3 0V VLCD VLCD1, VLCD2 COM4 0V LCD driver output w hen all LCD VLCD Segment corresponding to COM1, VLCD1, VLCD2 COM2, COM3 and COM4 are off 0V VLCD LCD driver output w hen only LCD Segments VLCD1, VLCD2 corresponding to COM1 is on 0V VLCD LCD driver output w hen only LCD Segments VLCD1, VLCD2 corresponding to COM2 is on. 0V VLCD LCD driver output w hen only LCD Segments VLCD1, VLCD2 corresponding to COM1 and COM2 are on. 0V VLCD LCD driver output w hen only LCD Segments VLCD1, VLCD2 corresponding to COM3 is on. 0V VLCD LCD driver output w hen LCD Segments VLCD1, VLCD2 corresponding to COM1 and COM3 are on 0V VLCD LCD driver output w hen LCD Segments VLCD1, VLCD2 corresponding to COM2 and COM3 are on 0V VLCD LCD driver output w hen LCD Segments VLCD1, VLCD2 corresponding to COM1, COM2 and COM3 are on 0V VLCD LCD driver output w hen LCD Segments VLCD1, VLCD2 corresponding to COM4 is on 0V VLCD LCD driver output w hen LCD Segments VLCD1, VLCD2 corresponding to COM2 and COM4 are on 0V VLCD LCD driver output w hen LCD Segments VLCD1, VLCD2 corresponding to COM1, COM2, COM3 0V and COM4 are on Figure 43. LCD Waveform (Frame Inversion, 1/4 DUTY, 1/2BIAS) www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 61/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) LCD Driving Waveforms – continued 17. Frame Inversion 1/3-Duty 1/3-Bias Drive Scheme fo[Hz] VLCD VLCD1 VLCD2 COM1 0V VLCD VLCD1 VLCD2 COM2 0V VLCD VLCD1 VLCD2 COM3 0V VLCD LCD driver output w hen all LCD VLCD1 Segment corresponding to COM1, VLCD2 COM2, and COM3 are off 0V VLCD LCD driver output w hen only LCD Segments VLCD1 corresponding to COM1 is on VLCD2 0V VLCD LCD driver output w hen only LCD Segments VLCD1 corresponding to COM2 is on. VLCD2 0V VLCD LCD driver output w hen only LCD Segments VLCD1 corresponding to COM1 and COM2 are on. VLCD2 0V VLCD LCD driver output w hen only LCD Segments VLCD1 corresponding to COM3 is on. VLCD2 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM1 and COM3 are on VLCD2 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM2 and COM3 are on VLCD2 0V VLCD LCD driver output w hen LCD Segments VLCD1 corresponding to COM1, COM2 and COM3 are on VLCD2 0V Figure 44. LCD Waveform (Frame Inversion, 1/3 DUTY, 1/3BIAS) (Note33) (Note33) COM4 function is same as COM1 at 1/3 duty. www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 62/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) LCD Driving Waveforms – continued 18. Frame Inversion 1/3-Duty 1/2-Bias Drive Scheme fo[Hz] VLCD VLCD1, VLCD2 COM1 0V VLCD VLCD1, VLCD2 COM2 0V VLCD VLCD1, VLCD2 COM3 0V LCD driver output w hen all LCD VLCD Segment corresponding to COM1, VLCD1, VLCD2 COM2, and COM3 are off 0V VLCD LCD driver output w hen only LCD Segments VLCD1, VLCD2 corresponding to COM1 is on 0V VLCD LCD driver output w hen only LCD Segments VLCD1, VLCD2 corresponding to COM2 is on. 0V VLCD LCD driver output w hen only LCD Segments VLCD1, VLCD2 corresponding to COM1 and COM2 are on. 0V VLCD LCD driver output w hen only LCD Segments VLCD1, VLCD2 corresponding to COM3 is on. 0V VLCD LCD driver output w hen LCD Segments VLCD1, VLCD2 corresponding to COM1 and COM3 are on 0V VLCD LCD driver output w hen LCD Segments VLCD1, VLCD2 corresponding to COM2 and COM3 are on 0V VLCD LCD driver output w hen LCD Segments VLCD1, VLCD2 corresponding to COM1, COM2 and COM3 are on 0V Figure 45. LCD Waveform (Frame Inversion, 1/3 DUTY, 1/2 BIAS) (Note34) (Note34) COM4 function is same as COM1 at 1/3 duty. www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 63/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) LCD Driving Waveforms – continued 19. Frame Inversion Static Drive Scheme fo[Hz] VLCD COM1 0V VLCD LCD driver output w hen all LCD Segments corresponding to COM1 is off 0V VLCD LCD driver output w hen all LCD Segments corresponding to COM1 is on 0V Figure 46. LCD Waveform (Frame Inversion, Static) (Note35) (Note35) COM2, COM3 and COM4 function are same as COM1 at Static. www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 64/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Oscillation Stabilization Time of the Internal Oscillation Circuit It must be noted that the oscillation of the internal oscillation circuit is unstable for a maximum of 100μs (oscillation stabilization time) after oscillation has started. Internal oscillation circuit Oscillation stabilization time (100 [µs] Max.) Oscillation stopped Oscillation operation (under normal conditions) Oscillation starts when control data OC = "0" and BU0 to BU2="000" Figure 47. Oscillation Stabilization Time Power-saving mode operation in external clock mode After receiving [BU0,BU1,BU2]=[1,1,1], BU97550KV-M enter to Power-saving mode synchronized with frame then Segment and Common ports output VSS level. Therefore, in external clock mode, it is necessary to input the external clock based on each frame frequency setting after sending [BU0,BU1,BU2]=[1,1,1]. For the required number of clock, refer to “Control Data Functions 6. FC0, FC1, FC2 and FC3”. For example, please input the external clock as below. [FC0,FC1,FC2,FC3]=[0,0,0,0]: In case of fosc/12288 setting, it needs over 12288clk, [FC0,FC1,FC2,FC3]=[0,1,0,1]: In case of fosc/4608 setting, it needs over 4608clk, [FC0,FC1,FC2,FC3]=[1,1,1,1]: In case of fosc/1536 setting, it needs over 1536clk Please refer to the timing chart below. SCE SCL SDI 1 0 0 1 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 Dev ice Code 8bits D1 D2 SC BU0 BU1 Display Data/ Control Data BU2 0 0 0 DD 3 bits OSC To input external clock at least 1 f rame or more SEG VSS COM1 VSS COM2 VSS COM3 VSS COM4 VSS Output at Normal mode Output at Power-sav ing mode(VSS lev el) Power sav ing Last Display f lame of Sirial data www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 65/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Voltage Detection Type Reset Circuit (VDET) The Voltage Detection Type Reset Circuit generates an output signal that resets the system when power is applied for the first time and when the power supply voltage drops (that is, for example, the power supply voltage is less than or equal to the power down detection voltage (VDET = 1.8V Typ). To ensure that this reset function works properly, it is recommended that a capacitor be connected to the power supply line so that both the power supply voltage (VDD) rise time when power is first applied and the power supply voltage (VDD) fall time when the voltage drops are at least 1ms. To refrain from data transmission is strongly recommended while power supply is rising up or falling down to prevent from the occurrence of disturbances on transmission and reception. t1 VDD t2 VDD Min VDD Min t3 VDD = 1.0V Figure 48. VDET Detection Timing Power supply voltage VDD fall time: t1 > 1ms Power supply voltage VDD rise time: t2 > 1ms Internal reset power supply retain time: t3 > 1ms When it is difficult to keep above conditions, it is possibility to cause meaningless display due to no IC initialization. Please execute the IC initialization as quickly as possible after Power-On to reduce such an affect. See the IC initialization flow as below. But since commands are not received when the power is OFF, the IC initialization flow is not the same function as VDET. Set [BU0,BU1,BU2]=[1,1,1](power-saving mode) and SC=1(Display Off) as quickly as possible after Power-On. BU97550KV-M can receive commands in 0ns after Power-On(VDD level is 90%). (Note1) t1≥0, t2≥0, tc: Min 10µs When VDD level is over 90%, there may be cases where command is not received correctly in unstable VDD. (Note2) Display data are undefined. Regarding default value, refer to Reset Condition. www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 66/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Reset Condition When BU97550KV-M is initialized, the internal status after power supply has been reset as the following table. Instruction Key Scan Mode S1/P1/G1 to S9/P9/G9 Pin Inversion Mode LCD Bias LCD Duty DISPLAY Frequency Display Clock Mode LCD Display Power Mode PWM/GPO output PWM Frequency At Reset Condition [KM0,KM1,KM2]=[1,1,1]:Key scan no use [P0,P1,P2,P3]=[0,0,0,0]:all Segment output FL=0:Line Inversion [DR0,DR1]=[0,0]:1/3 bias [DT0,DT1,DT2]=[0,1,0]:1/4 duty [FC0,FC1,FC2,FC3]=[0,0,0,0]:fosc/12288 OC=0:Internal oscillator SC=1:OFF [BU0,BU1,BU2]=[1,1,1]:Power saving mode PGx=0:PWM output(x=1 to 9) [PF0,PF1,PF2,PF3]=[0,0,0,0]: fosc /4096 PWM Duty [Wn0 to Wn8]=[0,0,0,0,0,0,0,0,0]:0/256)xTp (n=1 to 9,Tp=1/fp) Display Contrast Setting [CT0,CT1,CT2,CT3]=[0,0,0,0]:VLCD Level is 1.00*VDD www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 67/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Operational Notes 1. Reverse Connection of Power Supply Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when connecting the power supply, such as mounting an external diode between the power supply and the IC’s power supply pins. 2. Power Supply Lines Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and aging on the capacitance value when using electrolytic capacitors. 3. Ground Voltage Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition. 4. Ground Wiring Pattern When using both small-signal and large-current ground traces, the two ground traces should be routed separately but connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal ground caused by large currents. Also ensure that the ground traces of external components do not cause variations on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance. 5. Thermal Consideration Should by any chance the power dissipation rating be exceeded the rise in temperature of the chip may result in deterioration of the properties of the chip. The absolute maximum rating of the Pd stated in this specification is when the IC is mounted on a 70mm x 70mm x 1.6mm glass epoxy board. In case of exceeding this absolute maximum rating, increase the board size and copper area to prevent exceeding the Pd rating. 6. Recommended Operating Conditions These conditions represent a range within which the expected characteristics of the IC can be approximately obtained. The electrical characteristics are guaranteed under the conditions of each parameter. 7. Inrush Current When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and routing of connections. 8. Operation Under Strong Electromagnetic Field Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction. 9. Testing on Application Boards When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply should always be turned off completely before connecting or removing it from the test setup during the inspection process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during transport and storage. 10. Inter-pin Short and Mounting Errors Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin. Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and unintentional solder bridge deposited in between pins during assembly to name a few. www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 68/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Operational Notes – continued 11. Unused Input Pins Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the power supply or ground line. 12. Regarding the Input Pin of the IC In the construction of this IC, P-N junctions are inevitably formed creating parasitic diodes or transistors. The operation of these parasitic elements can result in mutual interference among circuits, operational faults, or physical damage. Therefore, conditions which cause these parasitic elements to operate, such as applying a voltage to an input pin lower than the ground voltage should be avoided. Furthermore, do not apply a voltage to the input pins when no power supply voltage is applied to the IC. Even if the power supply voltage is applied, make sure that the input pins have voltages within the values specified in the electrical characteristics of this IC. www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 69/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Ordering Information B U 9 7 5 5 0 Part Number K V Package KV : VQFP80 - ME2 Product Rank M: for Automotive Packaging Specification E2: Embossed tape and reel (VQFP80) Marking Diagram VQFP80 (TOP VIEW) Part Number Marking Lot Number Marking BU97550KV 1PIN MARK www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 70/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Physical Dimension, Tape and Reel Information VQFP80 Package Name 1PIN MARK www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 71/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 BU97550KV-M MAX 528 Segment(66SEG x 8COM) Revision History Date Revision 30.Mar.2015 09.Jul.2015 001 002 21.Mar.2017 003 18 Jun 2019 004 Changes New Release Modified Absolute Maximum Ratings(6.5V to 7.0V) table in Page 3. Modified comment of figure.48 in Page 64. Page.3 Delete temperature condition in Absolute Maximum Ratings Page.4 Add tr,tf item in Oscillation Characteristics Page.7 Modify Figure.6 I/O Equivalent Circuit Page.22 Add notice of External Clock input timing function Page.25 Add The relationship of LCD display contrast setting and VLCD voltage Page.65Add notice of Power-saving mode operation in external clock mode Page.66 Add notice in Voltage Detection Type Reset Circuit (VDET) Change from “1/1 duty” to “Static” Add Reset condition in each Control Data Function Change “Sleep mode” to” Power-saving mode” Correction of errors Page. 9,11,13,15,17 and 19 Add Description www.rohm.com © 2015 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 72/72 TSZ02201-0P4P0D300980-1-2 18.Jul.2019 Rev.004 Notice Precaution on using ROHM Products 1. If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment (Note 1), aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific Applications. (Note1) Medical Equipment Classification of the Specific Applications JAPAN USA EU CHINA CLASSⅢ CLASSⅡb CLASSⅢ CLASSⅢ CLASSⅣ CLASSⅢ 2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which a failure or malfunction of our Products may cause. The following are examples of safety measures: [a] Installation of protection circuits or other protective devices to improve system safety [b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure 3. Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our Products under any special or extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of product performance, reliability, etc, prior to use, must be necessary: [a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents [b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust [c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2 [d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves [e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items [f] Sealing or coating our Products with resin or other coating materials [g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used. However, recommend sufficiently about the residue.); or Washing our Products by using water or water-soluble cleaning agents for cleaning residue after soldering [h] Use of the Products in places subject to dew condensation 4. The Products are not subject to radiation-proof design. 5. Please verify and confirm characteristics of the final or mounted products in using the Products. 6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied, confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect product performance and reliability. 7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in the range that does not exceed the maximum junction temperature. 8. Confirm that operation temperature is within the specified range described in the product specification. 9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in this document. Precaution for Mounting / Circuit board design 1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product performance and reliability. 2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products, please consult with the ROHM representative in advance. For details, please refer to ROHM Mounting specification Notice-PAA-E © 2015 ROHM Co., Ltd. All rights reserved. Rev.004 Precautions Regarding Application Examples and External Circuits 1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the characteristics of the Products and external components, including transient characteristics, as well as static characteristics. 2. You agree that application notes, reference designs, and associated data and information contained in this document are presented only as guidance for Products use. Therefore, in case you use such information, you are solely responsible for it and you must exercise your own independent verification and judgment in the use of such information contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of such information. Precaution for Electrostatic This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron, isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control). Precaution for Storage / Transportation 1. Product performance and soldered connections may deteriorate if the Products are stored in the places where: [a] the Products are exposed to sea winds or corrosive gases, including Cl 2, H2S, NH3, SO2, and NO2 [b] the temperature or humidity exceeds those recommended by ROHM [c] the Products are exposed to direct sunshine or condensation [d] the Products are exposed to high Electrostatic 2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is exceeding the recommended storage time period. 3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads may occur due to excessive stress applied when dropping of a carton. 4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of which storage time is exceeding the recommended storage time period. Precaution for Product Label A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only. Precaution for Disposition When disposing Products please dispose them properly using an authorized industry waste company. Precaution for Foreign Exchange and Foreign Trade act Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign trade act, please consult with ROHM in case of export. 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Provided, however, that ROHM will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to manufacture or sell products containing the Products, subject to the terms and conditions herein. Other Precaution 1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM. 2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written consent of ROHM. 3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the Products or this document for any military purposes, including but not limited to, the development of mass-destruction weapons. 4. The proper names of companies or products described in this document are trademarks or registered trademarks of ROHM, its affiliated companies or third parties. Notice-PAA-E © 2015 ROHM Co., Ltd. All rights reserved. Rev.004 Datasheet General Precaution 1. Before you use our Products, you are requested to carefully read this document and fully understand its contents. ROHM shall not be in any way responsible or liable for failure, malfunction or accident arising from the use of any ROHM’s Products against warning, caution or note contained in this document. 2. All information contained in this document is current as of the issuing date and subject to change without any prior notice. Before purchasing or using ROHM’s Products, please confirm the latest information with a ROHM sales representative. 3. The information contained in this document is provided on an “as is” basis and ROHM does not warrant that all information contained in this document is accurate and/or error-free. ROHM shall not be in any way responsible or liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccuracy or errors of or concerning such information. Notice – WE © 2015 ROHM Co., Ltd. All rights reserved. Rev.001