Datasheet
Low Duty LCD Segment Driver
for Automotive application
BU97601FV-M
MAX 116 Segments (29SEG x 4COM)
General Description
Key Specifications
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The BU97601FV-M is a 1/4, 1/3, 1/2 duty or Static
general-purpose LCD driver that can be used for
automotive applications and can drive up to 116 LCD
Segments.
This product can support VA LCD displays, which has
better optical performance with higher LCD voltage
driving and higher frame frequency driving.
It can control up to 16 general-purpose outputs / 16
PWM output ports for LED backlighting and LED button
illumination realizing less flicker by various frequency
setting function.
It can also support a key scan function that detects a
maximum of 20 key inputs to reduce PCB wiring and to
minimize microcontroller size and cost.
It can support LCD contrast adjustment by its EVR
function and TTL compatible input interface is also
available, these are well-suited for wide-voltage range of
MCUs.
Supply Voltage Range:
+2.7 V to +6.0 V
Operating Temperature Range:
-40 °C to +85 °C
Max Segments:
116 Segments
Display Duty
Static, 1/2, 1/3, 1/4 Selectable
Bias:
1/2, 1/3 Selectable
Interface:
3wire Serial Interface
Special Characteristics
◼ Electrostatic Discharge Voltage(HBM):
◼ Latch-up Current:
±2000 V
±100 mA
Applications
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Features
◼ AEC-Q100 Qualified (Note)
◼ 1/4, 1/3, 1/2 duty or Static Setting Selectable
1/4 duty: Max 116 Segments,
1/3 duty: Max 87 Segments
1/2 duty: Max 58 Segments,
Static: Max 29 Segments
◼ 1/3 or 1/2 Bias Setting Selectable
◼ Support wide range of operation voltage from 2.7 V to
6.0 V, which can support TN LCD and VA LCD
display.
◼ Integrated LCD Voltage Driving Circuit
◼ Integrated Oscillation Circuit for LCD Frame
Frequency
◼ Line or Frame Inversion Driving Selectable
◼ Max 16ch External PWM Outputs
(SEG outputs/general purpose outputs selectable)
◼ Max 6ch Internal PWM Outputs
(SEG outputs/general purpose outputs/external PWM
outputs selectable)
◼ Support 256 Step PWM Function to Realize Backlight
Button LED Illumination
◼ Support LCD Frame Frequency from 50 Hz to 685 Hz,
Total 128-setting
◼ Support PWM Frequency from 146 Hz to 2.34 kHz,
Total 16-setting
◼ Support 3 Wire Serial Interface + KEYOUT
◼ Support TTL Level Input to Connect 3.3 V MCU
Directly
◼ Support Max 20 Keys Input Detection
(SEG selectable)
◼ Integrated EVR Function to Adjust LCD Contrast
◼ Integrated Voltage Detected Type Power on Reset
Circuit
◼ No External Components Required
◼ Low Power Consumption Design
Instrument Clusters
Climate Controls
Car Audios
Car Radios
Metering
White Goods
Healthcare Products
Battery Operated Products
etc.
Package
W (Typ) x D (Typ) x H (Max)
SSOP-B40
13.6 mm x 7.8 mm x 2.0 mm
(Note) Grade 3
〇Product structure : Silicon monolithic integrated circuit
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〇This product is not designed protection against radioactive rays.
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BU97601FV-M
Datasheet
MAX 116 Segments (29SEG x 4COM)
Typical Application Circuit
Key matrix
(P1/G1)
(P6/G6)
(P16/G16)
KS1/S23
|
KS5/S27
+5 V
KI1/S32
|
KI4/S35
(General purpose/PWM ports)
(For use control of backlight)
COM1
COM2
COM3
COM4
S5/P1/G1
S6/P2/G2
VDD
(Note)
S10/P6/G6
S11/P7/G7
INHb
From
Controller
SCE
LCD Panel
(Up to 116
Segments)
SCL
SDI
To Controller
S20/P16/G16
SDO
S21
S22
PWMIN/S36
From
Controller
OSCIN/S37
(Note) Insert capacitors between VDD and VSS C > 0.1 µF.
Figure 1. Typical Application Circuit
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20
21
KI3/S34
KI2/S33
KI1/S32
COM2
KS2/S24
KS5/S27
COM3
KS1/S23
KI4/S35
COM4
S22
KS4/S26
VDD
S21
COM1
VSS
S20/P16/G16
KS3/S25
PWMIN/S36
S19/P15/G15
SCE
S17/P13/G13
OSCIN/S37
SCL
S16/P12/G12
S18/P14/G14
SDI
INHb
S13/P9/G9
S15/P11/G11
S5/P1/G1
S12/P8/G8
SDO
S6/P2/G2
S11/P7/G7
S14/P10/G10
S7/P3/G3
S10/P6/G6
40
S8/P4/G4
1
S9/P5/G5
BU97601FV-M
MAX 116 Segments (29SEG x 4COM)
Datasheet
Block Diagram
Figure 2. Block Diagram
Pin Arrangement
Figure 3. Pin Configuration (TOP VIEW)
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BU97601FV-M
Datasheet
MAX 116 Segments (29SEG x 4COM)
Absolute Maximum Ratings(VSS = 0.0 V)
Parameter
Maximum Supply Voltage
Symbol
VDD
VIN1
Input Voltage
VIN2
Pd
Topr
Tstg
Allowable Loss
Operating Temperature
Storage Temperature
Conditions
VDD
SCE, SCL, SDI, INHb, PWMIN(Note 1),
OSCIN(Note 2)
KI1 to KI4(Note 3)
Ratings
-0.3 to +7.0
Unit
V
-0.3 to +7.0
V
-0.3 to +7.0
0.70(Note 4)
-40 to +85
-55 to +125
V
W
°C
°C
(Note 1) In case of External PWM setting.
(Note 2) In case of External clock mode setting.
(Note 3) In case of Key scan setting
(Note 4) Delete by 7.00 mW/°C when operating above Ta = 25 °C (when mounted in ROHM’s standard board).
Caution: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated over the
absolute maximum ratings.
Recommended Operating Conditions (Ta = -40 °C to +85 °C, VSS = 0.0 V)
Parameter
Supply Voltage
Symbol
Conditions
Min
2.7
VDD
Ratings
Typ
5.0
Max
6.0
Limit
Typ
Max
Unit
V
Electrical Characteristics (Ta = -40 to +85 °C, VDD = 2.7 V to 6.0 V, VSS = 0.0 V)
Parameter
Hysteresis
Symbol
Pin
VH1
SCE, SCL, SDI, INHb,
PWMIN(Note1),
OSCIN(Note 2)
KI1 to KI4(Note 3)
VDD
VH2
Power-on
Detection Voltage
“H” Level Input
Voltage
VDET
VIH1
VIF
SCE, SCL, SDI, INHb,
PWMIN(Note1),
OSCIN(Note 2)
SCE, SCL, SDI, INHb,
PWMIN(Note 1),
OSCIN(Note 2)
KI1 to KI4(Note 3)
SCE,SCL,SDI,INHb,
PWMIN(Note 1),
OSCIN(Note 2),
KI1 to KI4(Note 3)
KI1 to KI4(Note 3)
RPD
KI1 to
KI4(Note 3)
IOFFH
SDO
VIH2
“L” Level Input
Voltage
VIH3
VIL1
Input Floating
Voltage
Pull-down
Resistance
Output Off
Leakage
Current
“H” Level Input
Current
“L” Level Input
Current
IIL1
“H” Level
Output Voltage
VOH1
VOH2
“L” Level
Output Voltage
IIH1
SCE, SCL, SDI, INHb,
PWMIN(Note 1),
OSCIN(Note 2)
SCE, SCL, SDI, INHb,
PWMIN(Note 1),
OSCIN(Note 2)
S1 to S37
COM1 to COM4
P16/G16(Note 5)
VOH3
P1/G1 to
VOH4
VOL1
VOL2
VOL3
VOL4
VOL5
KS1 to KS5(Note 3)
S1 to S37
COM1 to COM4
P1/G1 to P16/G16(Note 5)
KS1 to KS5(Note 3)
SDO
Conditions
Min
Unit
-
0.03VD
D
-
V
-
0.1VDD
-
V
1.3
1.8
2.2
V
0.4VDD
-
VDD
V
0.8VDD
-
VDD
V
0.7VDD
-
VDD
V
0
-
0.2VDD
V
-
-
0.05VDD
V
50
100
250
kΩ
VO = 6.0 V
-
-
6.0
µA
VI = 5.5 V
-
-
5.0
µA
-5.0
-
-
µA
VDD-0.9
-
-
VDD-0.9
-
-
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
VDD = 5.0 V
VI = 0 V
IO = -20 µA, VLCD = 1.00*VDD
IO = -100 µA,
VLCD = 1.00*VDD
IO = -1 mA
IO = -500 µA
IO = 20 µA
IO = 100 µA
IO = 1 mA
IO = 25 µA
IO = 1 mA
VDD-0.
9
VDD-1.0 VDD-0.5 VDD-0.2
0.9
0.9
0.9
0.2
0.5
1.5
0.1
0.5
V
V
(Note 5) General –purpose / PWM outputs setting.
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Datasheet
MAX 116 Segments (29SEG x 4COM)
Electrical Characteristics – continued
Parameter
Middle Level
Output Voltage
Symbol
VMID1
VMID2
VMID3
VMID4
VMID5
Current
Consumption
IDD1
IDD2
IDD3
Pin
COM1 to COM4
S1 to S37
S1 to S37
COM1 to COM4
COM1 to COM4
VDD
VDD
VDD
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Conditions
1/2 bias
IO = ±100 µA
VLCD = 1.00*VDD
1/3 bias
IO = ±20 µA
VLCD = 1.00*VDD
1/3 bias
IO = ±20 µA
VLCD = 1.00*VDD
1/3 bias
IO = ±100 µA
VLCD = 1.00*VDD
1/3 bias
IO = ±100 µA
VLCD = 1.00*VDD
Power-saving mode
VDD = 5.0 V
Output open,
1/2 bias
Frame frequency = 80 Hz
VLCD = 1.00*VDD
VDD = 5.0 V
Output open,
1/3 bias
Frame frequency = 80 Hz
VLCD = 1.00*VDD
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Min
Limit
Typ
Max
Unit
1/2VDD
-0.9
-
1/2VDD
+0.9
2/3VDD
-0.9
-
2/3VDD
+0.9
1/3VDD
-0.9
-
1/3VDD
+0.9
2/3VDD
-0.9
-
2/3VDD
+0.9
1/3VDD
-0.9
-
1/3VDD
+0.9
-
-
15
µA
-
100
210
µA
-
120
250
µA
V
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Datasheet
MAX 116 Segments (29SEG x 4COM)
Oscillation Characteristics (Ta = -40 °C to +85 °C, VDD = 2.7 V to 6.0 V, VSS = 0.0 V)
Parameter
Symbol
Pin
Conditions
Oscillator Frequency 1
Oscillator Frequency 2
External Clock
Frequency(Note 1)
External Clock Rise Time
External Clock Fall Time
External Clock Duty
fOSC1
fOSC2
fOSC3
-
VDD = 2.7 V to 6.0 V
VDD = 5 V
tr
tf
tdty
External clock mode
(OC = 1)
OSCIN
Min
360
540
Limit
Typ
600
Max
720
660
30
-
1000
kHz
30
160
160
50
70
ns
ns
%
Unit
kHz
kHz
(Note 1) Frame frequency is decided external frequency and dividing ratio of FC0, FC1, FC2, FC3, FC4, FC5, FC6 setting.
[Reference Data]
700
650
VDD = 6.0 V
fosc[kHz]
600
VDD = 5.0 V
VDD = 3.3 V
550
VDD = 2.7 V
500
450
400
350
300
-40
-20
0
20
40
60
80
100
Temperature[°C]
Figure 4. Oscillator Frequency Typical Temperature Characteristics
External PWM Clock Characteristics (Ta = -40 °C to +85 °C, VDD = 2.7 V to 6.0 V, VSS = 0.0 V)
Parameter
External PWM
Frequency
External PWM Input
Rise Time
External PWM Input
Fall Time
External PWM Pulse
Width
Symbol
Pin
Conditions
fPWM
trPWM
PWMIN
Min
Limit
Typ
Max
30
-
5000
Hz
-
160
-
ns
-
160
-
ns
780
-
-
ns
Unit
External PWM mode(Note 2)
tfPWM
pwPWM
(Note 2) About External PWM mode setting, please refer to “Control Data Functions”.
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Datasheet
MAX 116 Segments (29SEG x 4COM)
MPU Interface Characteristics (Ta = -40 °C to +85 °C, VDD = 2.7 V to 6.0 V, VSS = 0.0 V)
Parameter
Symbol
Data Setup Time
Data Hold Time
SCE Wait Time
SCE Setup Time
SCE Hold Time
Clock Cycle Time
High-level Clock Pulse
Width
Low-level Clock Pulse
Width (Write)
Low-level Clock Pulse
Width (Read)
Rise Time
Fall Time
INH Switching Time
SDO Output Delay
Time
tDS
tDH
tCP
tCS
tCH
SDO Rise Time
Pin
tCCYC
tCHW
SCL, SDI
SCL, SDI
SCE, SCL
SCE, SCL
SCE, SCL
SCL
SCL
tCLWW
SCL
tCLWR
SCL
Conditions
Min
120
120
120
120
120
320
RPU = 4.7 kΩ
CL = 10 pF(Note)
tr
tf
tc
tDC
SCE, SCL, SDI,
SCE, SCL, SDI,
INHb, SCE
SDO
tDR
SDO
Limit
Typ
-
Max
-
Unit
ns
ns
ns
ns
ns
ns
120
-
-
ns
120
-
-
ns
1.6
-
-
µs
10
160
160
-
-
ns
ns
µs
-
-
1.5
µs
-
-
1.5
µs
RPU = 4.7 kΩ
CL = 10 pF(Note)
RPU = 4.7 kΩ
CL = 10 pF(Note)
(Note) Since SDO is an open-drain output, ”tDC” and “tDR” depend on the resistance of the pull-up resistor RPU and the load capacitance CL.
RPU: 1 kΩ ≤ RPU ≤ 10 kΩ is recommended.
CL: A parasitic capacitance to VSS in an application circuit. Any component is not necessary to be attached.
Power supply for I/O level
RPU
SDO
Host
CL
1. When SCL is stopped at the low level
VIH1
SCE
VIL1
tCCYC
tCHW
tCLWW
tCLWR
VIH1
SCL
VIL1
tr
SDI
tCH
tcs
tf
VIH1
VIL1
tDS
tDH
SDO
VOL5
tDC
tDR
2. When SCL is stopped at the high level
VIH1
SCE
VIL1
tCCYC
tCHW
tCLWW
SCL
tCLWR
VIH1
VIL1
SDI
tCP
tr
tf
tCH
VIH1
VIL1
tDS
tDH
SDO
VOL5
tDC
tDR
Figure 5. Serial Interface Timing
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Datasheet
MAX 116 Segments (29SEG x 4COM)
Pin Description
Symbol
Pin No.
Function
Active
I/O
S5/P1/G1 to
S10/P6/G6
1 to 2
37 to 40
-
O
S11/P7/G7 to
S20/P16/G16
3 to 12
-
O
OPEN
S21 to S22
13 to14
-
O
OPEN
KS1/S23 to
KS5/S27
15 to 19
-
O
OPEN
KI1/S32 to
KI4/S35
20 to 23
-
I
VSS
COM1 to
COM4
PWMIN/S36
24 to 27
Segment output for displaying the display data transferred by
serial data input. The S5/P1/G1 to S10/P6/G6 pins can also be
used as General –purpose / PWM outputs when set by the
control data.
Segment output for displaying the display data transferred by
serial data input. The S11/P7/G7 to S20/P16/G16 pins can
also be used as General –purpose outputs / PWM outputs (by
External PWM only) when set by the control data.
Segment output for displaying the display data transferred by
serial data input.
Key scan outputs.
Although normal key scan timing lines require diodes to be
inserted in the timing lines to prevent shorts, since these
outputs are unbalanced CMOS transistor outputs, these
outputs will not be damaged by shorting when these outputs
are used to form a key matrix. The KS1/S23 to KS5/S27 pins
can be used as segment outputs when specified by the control
data.
Key scan inputs. These pins have built-in pull-down resistors.
The KI1/S32 to KI4/S35 pins can be used as segment outputs
when specified by the control data.
Common driver output pins.
The frame frequency is fo[Hz].
Segment output for displaying the display data transferred by
serial data input. The pin PWMIN/S36 can be used external
PWM input pin or segment output when set by the control
data.
Segment output for displaying the display data transferred by
serial data input. The pin OSCIN/S37 can be used as external
frequency input pin or segment output when set by the control
data.
Serial data transfer inputs. Must be connected to the
controller.
SCE: Chip enable
SCL: Synchronization clock
SDI: Transfer data
Output data
Display off control input.
When INHb = low (VSS), Display forced off
S5/P1/G1 to S10/P6/G6 = low (VSS)
S11/P7/G7 to S20/P16/G16 = low (VSS)
S21 to S22 = low (VSS)
KS1/S23 to KS5/S27 = low (VSS)
KI1/S32 to KI4/S35 = low (VSS)
PWMIN/S36 = low (VSS)
OSCIN/S37 = low (VSS)
COM1 to COM4 = low (VSS)
Stop the LCD drive bias voltage generation divider resistors.
Stop the internal oscillation circuit.
When INHb = high (VDD), Display on
However, serial data transfer is possible when the display is
forced off.
Power supply pin of the IC
A power voltage of 2.7 V to 6.0 V must be applied to this pin.
Power supply pin. Must be connected to ground.
Handling
when
unused
OPEN
-
O
O
OPEN
OPEN
-
I
VSS
O
OPEN
I
VSS
O
OPEN
OSCIN/S37
SCE
SCL
SDI
30
31
32
33
34
SDO
INHb(Note)
35
36
VDD
28
VSS
29
-
VSS
H
-
I
I
I
L
O
I
OPEN
VDD
-
-
-
-
-
-
↑
(Note) Regarding the details of INHb terminal and the control of each output, refer to “INHb Pin and Display Control”.
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MAX 116 Segments (29SEG x 4COM)
Datasheet
I/O Equivalence Circuit
VDD
VDD
SCE/SDI/SCL/INHb
VSS
VSS
VDD
VDD
S21 to S22,
COM1 to COM4
PWMIN/S36,
OSCIN/S37
VSS
VSS
VDD
VDD
KI1/S32 to KI4/S35
S5/P1/G1 to S20/P16/G16,
KS1/S23 to KS5/S27
VSS
VSS
VDD
SDO
VSS
Figure 6. I/O Equivalence Circuit
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Datasheet
MAX 116 Segments (29SEG x 4COM)
Serial Data Transfer Formats
1. 1/4 Duty
(1) When SCL is stopped at the low level
SCE
SCL
SDI
0
1
1
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
D1
D2
D32
Device Code
8bits
0
1
1
B0
B1
B2
0
0
0
1
0
B3
A0
A1
A2
A3
D38
0
1
1
0
0
0
1
0
B1
B2
B3
A0
A1
A2
A3
1
1
B2
D35
D36
0
D37
0
0
0
0
0
0
0
KM0 KM1 KM2
P0
D70
D71
D72
D73
0
D74
0
EP1
EP2
EP3
EP4
EP5
EP6
EP7
EP8
EP9
0
0
0
1
0
B3
A0
A1
A2
A3
D112
D113
P2
P3
P4
FL
DR
DT0
EP10 EP11 EP12 EP13 EP14 EP15 EP16 PG1
DT1
FC0
FC1
FC2
FC3
FC4
FC5
FC6
OC
SC
BU0
BU1
BU2
0
0
0
0
0
W10 W11 W12 W13 W14 W15 W16
W17 W18
W20 W21 W22 W23 W24
PG2
PG3
PG4
PG5
PG6
PF0
PF1
PF2
PF3
CT0
CT1
CT2
CT3
D143 D144 D145 D146 D147 D148
0
0
0
0
0
W40 W41 W42 W43 W44 W45 W46
W47 W48
W50 W51 W52 W53 W54
Control Data
33bits
0
0
1
DD
2 bits
W25 W26 W27 W28 W30 W31 W32 W33 W34 W35 W36 W37 W38
1
0
DD
2 bits
Control Data
33bits
Display Data
37bits
0
DD
2 bits
Control Data
33bits
Display Data
37bits
Device Code
8bits
P1
Control Data
33bits
D106 D107 D108 D109 D110 D111
D76
D75
Device Code
8bits
B1
D34
Display Data
37bits
B0
0
D69
D39
Device Code
8bits
B0
D33
Display Data
37bits
W55 W56 W57 W58 W60 W61 W62 W63 W64 W65 W66 W67 W68
1
DD
2 bits
1
(Note)
Figure 7. 3-SPI Data Transfer Format
(Note) DD is direction data.
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© 2016 ROHM Co., Ltd. All rights reserved.
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Datasheet
MAX 116 Segments (29SEG x 4COM)
Serial Data Transfer Formats – continued
(2) When SCL is stopped at the high level
SCE
SCL
SDI
0
1
1
B0
B1
B2
0
0
0
1
0
B3
A0
A1
A2
A3
D1
D2
D32
0
1
1
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
D38
0
1
1
B1
B2
D69
D39
D34
D35
D36
D37
0
0
0
0
0
0
0
0
KM0 KM1 KM2
P0
0
0
0
1
0
B3
A0
A1
A2
A3
D75
D70
D71
D72
D73
D74
0
0
EP1
EP2
EP3
EP4
EP5
EP6
EP7
EP8
EP9
0
1
1
0
0
0
1
0
B1
B2
B3
A0
A1
A2
A3
D112
Device Code
8bits
D113
P3
P4
FL
DR
DT0
EP10 EP11 EP12 EP13 EP14 EP15 EP16 PG1
0
0
0
0
0
W10 W11 W12 W13 W14 W15 W16
Display Data
37bits
B0
P2
DT1
FC0
FC1
FC2
FC3
FC4
FC5
FC6
OC
SC
BU0
BU1
BU2
W17 W18
W20 W21 W22 W23 W24
PG2
PG3
PG4
PG5
PG6
PF0
PF1
PF2
PF3
CT0
CT1
CT2
CT3
D143 D144 D145 D146 D147 D148
0
0
0
0
0
W40 W41 W42 W43 W44 W45 W46
W47 W48
W50 W51 W52 W53 W54
0
0
1
DD
2 bits
W25 W26 W27 W28 W30 W31 W32 W33 W34 W35 W36 W37 W38
1
0
DD
2 bits
Control Data
33bits
W55 W56 W57 W58 W60 W61 W62 W63 W64 W65 W66 W67 W68
1
1
DD
2 bits
Control Data
33bits
Display Data
37bits
0
DD
2 bits
Control Data
33bits
D106 D107 D108 D109 D110 D111
D76
Device Code
8bits
P1
Control Data
33bits
Display Data
37bits
Device Code
8bits
B0
D33
Display Data
37bits
Device Code
8bits
(Note)
Figure 8. 3-SPI Data Transfer Formatv
(Note) DD is direction data.
Device code･･････････････････“46H”
KM0 to KM2･･･････････････････Key Scan output port/Segment output port switching control data
D1 to D148････････････････････Display data (D1-D16 and D109-D124 are not available)
P0 to P4･･････････････････････Segment / PWM / General Purpose output port switching control data
FL････････････････････････････Line Inversion or Frame Inversion switching control data
DR･･･････････････････････････1/3 bias drive or 1/2 bias drive switching control data
DT0 to DT1･･･････････････････1/4 duty drive, 1/3 duty drive, 1/2 duty drive or Static drive switching control data
FC0 to FC6･･･････････････････Common/Segment output waveform frame frequency switching control data
OC･･････････････････････････Internal oscillator operating mode/External clock operating mode switching control data
SC･･････････････････････････Segment on/off switching control data
BU0 to BU2･･････････････････Normal mode/power-saving mode switching control data
PG1 to PG6･･････････････････PWM/General Purpose Output (GPO) switching control data
EP1 to EP16･････････････････Internal PWM/External PWM switching control data (EP1 to EP6),
GPO/External PWM switching control data (EP7 to EP16)
PF0 to PF3･･･････････････････PWM output waveform frame frequency switching control data.
CT0 to CT3･･･････････････････LCD display contrast switching control data.
W10 to W18, W20 to W28, W30 to W38, W40 to W48, W50 to W58, W60 to W68
･････････････････････････････PWM output duty switching control data
When it is coincident with device code, BU97601FV-M capture display data and control data at falling edge of SCE.
So, please transfer the bit number of send display data and control data as specified number in the above figure.
Specified number of bits is 80bit (Device code: 8bit, Display data and Control data: 70bit, DD: 2bit).
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BU97601FV-M
Datasheet
MAX 116 Segments (29SEG x 4COM)
Serial Data Transfer Formats – continued
2. 1/3 Duty
(1) When SCL is stopped at the low level
SCE
SCL
SDI
0
1
1
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
D1
D2
Device Code
8bits
0
1
1
B0
B1
B2
0
0
0
1
0
B3
A0
A1
A2
A3
D38
D39
0
1
1
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
D75
D76
1
1
B1
B2
D34
D35
D36
D37
0
0
0
0
0
0
0
0
KM0 KM1 KM2
P0
D69
0
0
0
1
0
B3
A0
A1
A2
A3
0
0
P1
P2
P3
P4
FL
DR
DT0
DT1
FC0
FC1
FC2
FC3
FC4
FC5
FC6
OC
SC
BU0
BU1
BU2
D70
D71
D72
D73
D74
0
0
EP1
EP2
EP3
EP4
EP5
EP6
EP7
EP8
EP9
EP10 EP11 EP12 EP13 EP14 EP15 EP16 PG1
PG2
PG3
PG4
PG5
PG6
PF0
PF1
PF2
PF3
CT0
CT1
CT2
CT3
0
0
0
0
0
W10 W11 W12 W13 W14 W15 W16
W17 W18
W20 W21 W22 W23 W24
W25 W26 W27 W28 W30 W31 W32 W33 W34 W35 W36 W37 W38
0
0
0
0
0
0
0
0
0
0
0
0
W40 W41 W42 W43 W44 W45 W46
W47 W48
W50 W51 W52 W53 W54
Control Data
70bits
0
1
1
0
DD
2 bits
Control Data
33bits
Device Code
8bits
0
DD
2 bits
Control Data
33bits
D106 D107 D108 D109 D110 D111
0
DD
2 bits
Control Data
33bits
Display Data
37bits
Device Code
8bits
0
D33
Display Data
37bits
Device Code
8bits
B0
D32
Display Data
37bits
W55 W56 W57 W58 W60 W61 W62 W63 W64 W65 W66 W67 W68
1
DD
2 bits
1
(Note)
Figure 9. 3-SPI Data Transfer Format
(Note) DD is direction data.
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© 2016 ROHM Co., Ltd. All rights reserved.
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BU97601FV-M
Datasheet
MAX 116 Segments (29SEG x 4COM)
Serial Data Transfer Formats – continued
(2) When SCL is stopped at the high level
SCE
SCL
SDI
0
1
1
B0
B1
B2
0
0
0
1
0
B3
A0
A1
A2
A3
D1
D2
0
1
1
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
D38
D39
0
1
1
B1
B2
D33
D34
D35
D36
D37
0
0
0
0
0
0
0
0
KM0 KM1 KM2
P0
D69
0
0
0
1
0
B3
A0
A1
A2
A3
D75
D76
D70
D71
D72
D73
D74
0
0
EP1
EP2
EP3
EP4
EP5
EP6
EP7
EP8
EP9
0
1
1
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
0
0
P2
P3
P4
FL
DR
DT0
EP10 EP11 EP12 EP13 EP14 EP15 EP16 PG1
DT1
FC0
FC1
FC2
FC3
FC4
FC5
FC6
OC
SC
BU0
BU1
BU2
D106 D107 D108 D109 D110 D111
0
0
0
0
0
W10 W11 W12 W13 W14 W15 W16
W17 W18
W20 W21 W22 W23 W24
PG2
PG3
PG4
PG5
PG6
PF0
PF1
PF2
PF3
CT0
CT1
CT2
CT3
0
0
0
0
0
0
0
0
0
0
0
W40 W41 W42 W43 W44 W45 W46
W47 W48
W50 W51 W52 W53 W54
W25 W26 W27 W28 W30 W31 W32 W33 W34 W35 W36 W37 W38
0
1
1
0
DD
2 bits
W55 W56 W57 W58 W60 W61 W62 W63 W64 W65 W66 W67 W68
1
1
DD
2 bits
Control Data
70bits
Device Code
8bits
0
DD
2 bits
Control Data
33bits
0
0
DD
2 bits
Control Data
33bits
Display Data
37bits
Device Code
8bits
P1
Control Data
33bits
Display Data
37bits
Device Code
8bits
B0
D32
Display Data
37bits
Device Code
8bits
(Note)
Figure 10. 3-SPI Data Transfer Format
(Note) DD is direction data.
Device code･･････････････････“46H”
KM0 to KM2･･･････････････････Key Scan output port/Segment output port switching control data
D1 to D111････････････････････Display data (D1-D12 and D82-D93 are not available)
P0 to P4･･････････････････････Segment / PWM / General Purpose output port switching control data
FL････････････････････････････Line Inversion or Frame Inversion switching control data
DR･･･････････････････････････1/3 bias drive or 1/2 bias drive switching control data
DT0 to DT1･･･････････････････1/4 duty drive, 1/3 duty drive, 1/2 duty drive or Static drive switching control data
FC0 to FC6･･･････････････････Common/Segment output waveform frame frequency switching control data
OC･･････････････････････････Internal oscillator operating mode/External clock operating mode switching control data
SC･･････････････････････････Segment on/off switching control data
BU0 to BU2･･････････････････Normal mode/power-saving mode switching control data
PG1 to PG6･･････････････････PWM/General Purpose Output (GPO) switching control data
EP1 to EP16･････････････････Internal PWM/External PWM switching control data (EP1 to EP6),
GPO/External PWM switching control data (EP7 to EP16)
PF0 to PF3･･･････････････････PWM output waveform frame frequency switching control data.
CT0 to CT3･･･････････････････LCD display contrast switching control data.
W10 to W18, W20 to W28, W30 to W38, W40 to W48, W50 to W58, W60 to W68
･････････････････････････････PWM output duty switching control data
When it is coincident with device code, BU97601FV-M capture display data and control data at falling edge of SCE.
So, please transfer the bit number of send display data and control data as specified number in the above figure.
Specified number of bits is 80bit (Device code: 8bit, Display data and Control data: 70bit, DD: 2bit).
www.rohm.com
© 2016 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
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05.Jan.2021 Rev.003
BU97601FV-M
Datasheet
MAX 116 Segments (29SEG x 4COM)
Serial Data Transfer Formats – continued
3. 1/2 Duty
(1) When SCL is stopped at the low level
SCE
SCL
SDI
0
1
1
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
D1
D2
Device Code
8bits
0
1
1
B0
B1
B2
D32
D33
D34
D35
D36
D37
0
0
0
0
0
0
0
0
KM0 KM1 KM2
P0
0
0
0
1
0
B3
A0
A1
A2
A3
D38
D39
D69
D70
D71
D72
D73
D74
0
0
EP1
EP2
EP3
EP4
EP5
EP6
EP7
EP8
EP9
0
1
1
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
0
0
0
0
1
1
B1
B2
P3
P4
FL
DR
DT0
DT1
FC0
FC1
FC2
FC3
FC4
FC5
FC6
OC
SC
BU0
BU1
BU2
0
0
0
0
0
0
0
0
0
0
0
W10 W11 W12 W13 W14 W15 W16
W17 W18
W20 W21 W22 W23 W24
PG2
PG3
PG4
PG5
PG6
PF0
PF1
PF2
PF3
CT0
CT1
CT2
CT3
0
0
0
1
0
B3
A0
A1
A2
A3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W40 W41 W42 W43 W44 W45 W46
W47 W48
W50 W51 W52 W53 W54
Control Data
70bits
0
0
1
DD
2 bits
W25 W26 W27 W28 W30 W31 W32 W33 W34 W35 W36 W37 W38
1
0
DD
2 bits
Control Data
70bits
Device Code
8bits
0
DD
2 bits
Control Data
33bits
Device Code
8bits
B0
P2
EP10 EP11 EP12 EP13 EP14 EP15 EP16 PG1
Display Data
37bits
Device Code
8bits
P1
Control Data
33bits
Display Data
37bits
W55 W56 W57 W58 W60 W61 W62 W63 W64 W65 W66 W67 W68
1
DD
2 bits
1
(Note)
Figure 11. 3-SPI Data Transfer Format
(Note) DD is direction data.
www.rohm.com
© 2016 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
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05.Jan.2021 Rev.003
BU97601FV-M
Datasheet
MAX 116 Segments (29SEG x 4COM)
Serial Data Transfer Formats – continued
(2) When SCL is stopped at the high level
SCE
SCL
SDI
0
1
1
B0
B1
B2
0
0
0
1
0
B3
A0
A1
A2
A3
D1
D2
0
1
1
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
D38
D39
0
1
1
B1
B2
D33
D34
D35
D36
D37
0
0
0
0
0
0
0
0
KM0 KM1 KM2
P0
D69
0
0
0
1
0
B3
A0
A1
A2
A3
0
0
0
P1
P2
P3
P4
FL
DR
DT0
DT1
FC0
FC1
FC2
FC3
FC4
FC5
FC6
OC
SC
BU0
BU1
BU2
D70
D71
D72
D73
D74
0
0
EP1
EP2
EP3
EP4
EP5
EP6
EP7
EP8
EP9
EP10 EP11 EP12 EP13 EP14 EP15 EP16 PG1
PG2
PG3
PG4
PG5
PG6
PF0
PF1
PF2
PF3
CT0
CT1
CT2
CT3
0
0
0
0
0
0
0
0
0
0
0
W10 W11 W12 W13 W14 W15 W16
W17 W18
W20 W21 W22 W23 W24
W25 W26 W27 W28 W30 W31 W32 W33 W34 W35 W36 W37 W38
0
1
1
0
0
0
1
0
B1
B2
B3
A0
A1
A2
A3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W40 W41 W42 W43 W44 W45 W46
W47 W48
W50 W51 W52 W53 W54
W55 W56 W57 W58 W60 W61 W62 W63 W64 W65 W66 W67 W68
1
1
0
1
1
DD
2 bits
Control Data
70bits
Device Code
8bits
0
DD
2 bits
Control Data
70bits
B0
0
DD
2 bits
Control Data
33bits
Device Code
8bits
0
DD
2 bits
Control Data
33bits
Display Data
37bits
Device Code
8bits
B0
D32
Display Data
37bits
Device Code
8bits
(Note)
Figure 12. 3-SPI Data Transfer Format
(Note) DD is direction data.
Device code･･････････････････“46H”
KM0 to KM2･･･････････････････Key Scan output port/Segment output port switching control data
D1 to D74･････････････････････Display data (D1-D8 and D55-D62 are not available)
P0 to P4･･････････････････････Segment / PWM / General Purpose output port switching control data
FL････････････････････････････Line Inversion or Frame Inversion switching control data
DR･･･････････････････････････1/3 bias drive or 1/2 bias drive switching control data
DT0 to DT1･･･････････････････1/4 duty drive, 1/3 duty drive, 1/2 duty drive or Static drive switching control data
FC0 to FC6･･･････････････････Common/Segment output waveform frame frequency switching control data
OC･･････････････････････････Internal oscillator operating mode/External clock operating mode switching control data
SC･･････････････････････････Segment on/off switching control data
BU0 to BU2･･････････････････Normal mode/power-saving mode switching control data
PG1 to PG6･･････････････････PWM/General Purpose Output (GPO) switching control data
EP1 to EP16･････････････････Internal PWM/External PWM switching control data (EP1 to EP6),
GPO/External PWM switching control data (EP7 to EP16)
PF0 to PF3･･･････････････････PWM output waveform frame frequency switching control data.
CT0 to CT3･･･････････････････LCD display contrast switching control data.
W10 to W18, W20 to W28, W30 to W38, W40 to W48, W50 to W58, W60 to W68
･････････････････････････････PWM output duty switching control data
When it is coincident with device code, BU97601FV-M capture display data and control data at falling edge of SCE.
So, please transfer the bit number of send display data and control data as specified number in the above figure.
Specified number of bits is 80bit (Device code: 8bit, Display data and Control data: 70bit, DD: 2bit).
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Datasheet
MAX 116 Segments (29SEG x 4COM)
Serial Data Transfer Formats – continued
4. Static
(1) When SCL is stopped at the low level
SCE
SCL
SDI
0
1
1
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
D1
D2
Device Code
8bits
0
1
1
B0
B1
B2
D32
D33
D34
D35
D36
D37
0
0
0
0
0
0
0
0
KM0 KM1 KM2
P0
0
0
0
1
0
B3
A0
A1
A2
A3
0
0
0
0
0
0
0
0
0
0
EP1
EP2
EP3
EP4
EP5
EP6
EP7
EP8
EP9
0
1
1
0
0
0
1
0
B1
B2
B3
A0
A1
A2
A3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W10 W11 W12 W13 W14 W15 W16
1
1
B2
P4
FL
DR
DT0
DT1
FC0
FC1
FC2
FC3
FC4
FC5
FC6
OC
SC
BU0
BU1
BU2
W17 W18
W20 W21 W22 W23 W24
0
0
0
1
0
B3
A0
A1
A2
A3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W40 W41 W42 W43 W44 W45 W46
W47 W48
W50 W51 W52 W53 W54
Control Data
70bits
Device Code
8bits
0
0
DD
2 bits
PG2
PG3
PG4
PG5
PG6
PF0
PF1
PF2
PF3
CT0
CT1
CT2
CT3
0
1
DD
2 bits
W25 W26 W27 W28 W30 W31 W32 W33 W34 W35 W36 W37 W38
1
0
DD
2 bits
Control Data
70bits
Device Code
8bits
B1
P3
Control Data
70bits
B0
0
P2
EP10 EP11 EP12 EP13 EP14 EP15 EP16 PG1
Device Code
8bits
B0
P1
Control Data
33bits
Display Data
37bits
W55 W56 W57 W58 W60 W61 W62 W63 W64 W65 W66 W67 W68
1
DD
2 bits
1
(Note)
Figure 13. 3-SPI Data Transfer Format
(Note) DD is direction data.
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Datasheet
MAX 116 Segments (29SEG x 4COM)
Serial Data Transfer Formats – continued
(2) When SCL is stopped at the high level
SCE
SCL
SDI
0
1
1
B0
B1
B2
0
0
0
1
0
B3
A0
A1
A2
A3
D1
D2
D32
D33
D34
D35
D36
D37
0
0
0
0
0
0
0
0
KM0 KM1 KM2
P0
0
1
1
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
0
0
0
0
0
0
0
0
0
0
EP1
EP2
EP3
EP4
EP5
EP6
EP7
EP8
EP9
0
1
1
B1
B2
P2
P3
P4
FL
DR
DT0
EP10 EP11 EP12 EP13 EP14 EP15 EP16 PG1
DT1
FC0
FC1
FC2
FC3
FC4
FC5
FC6
OC
SC
BU0
BU1
BU2
0
0
0
1
0
B3
A0
A1
A2
A3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W10 W11 W12 W13 W14 W15 W16
PG2
PG3
PG4
PG5
PG6
PF0
PF1
PF2
PF3
CT0
CT1
CT2
CT3
W17 W18
W20 W21 W22 W23 W24
0
1
1
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W40 W41 W42 W43 W44 W45 W46
W47 W48
W50 W51 W52 W53 W54
W25 W26 W27 W28 W30 W31 W32 W33 W34 W35 W36 W37 W38
0
1
1
0
DD
2 bits
W55 W56 W57 W58 W60 W61 W62 W63 W64 W65 W66 W67 W68
1
1
DD
2 bits
Control Data
70bits
Device Code
8bits
0
DD
2 bits
Control Data
70bits
Device Code
8bits
0
DD
2 bits
Control Data
70bits
Device Code
8bits
B0
P1
Control Data
33bits
Display Data
37bits
Device Code
8bits
(Note)
Figure 14. 3-SPI Data Transfer Format
(Note) DD is direction data.
Device code･･････････････････“46H”
KM0 to KM2･･･････････････････Key Scan output port/Segment output port switching control data
D1 to D37･････････････････････Display data (D1-D4 and D28-D31 are not available)
P0 to P4･･････････････････････Segment / PWM / General Purpose output port switching control data
FL････････････････････････････Line Inversion or Frame Inversion switching control data
DR･･･････････････････････････1/3 bias drive or 1/2 bias drive switching control data
DT0 to DT1･･･････････････････1/4 duty drive, 1/3 duty drive, 1/2 duty drive or Static drive switching control data
FC0 to FC6･･･････････････････Common/Segment output waveform frame frequency switching control data
OC･･････････････････････････Internal oscillator operating mode/External clock operating mode switching control data
SC･･････････････････････････Segment on/off switching control data
BU0 to BU2･･････････････････Normal mode/power-saving mode switching control data
PG1 to PG6･･････････････････PWM/General Purpose Output (GPO) switching control data
EP1 to EP16･････････････････Internal PWM/External PWM switching control data (EP1 to EP6),
GPO/External PWM switching control data (EP7 to EP16)
PF0 to PF3･･･････････････････PWM output waveform frame frequency switching control data.
CT0 to CT3･･･････････････････LCD display contrast switching control data.
W10 to W18, W20 to W28, W30 to W38, W40 to W48, W50 to W58, W60 to W68
･････････････････････････････PWM output duty switching control data
When it is coincident with device code, BU97601FV-M capture display data and control data at falling edge of SCE.
So, please transfer the bit number of send display data and control data as specified number in the above figure.
Specified number of bits is 80bit (Device code: 8bit, Display data and Control data: 70bit, DD: 2bit).
www.rohm.com
© 2016 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
17/63
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05.Jan.2021 Rev.003
BU97601FV-M
Datasheet
MAX 116 Segments (29SEG x 4COM)
Control Data Functions
1. KM0, KM1 and KM2: Key Scan output port/Segment output port switching control data
These control data bits switch the functions of the KS1/S23 to KS5/S27 output pins between key scan output and segment
output.
Output Pin State
Maximum Number
KM0 KM1 KM2
Reset condition
KS1/S23 KS2/S24 KS3/S25 KS4/S26 KS5/S27 of Input keys
0
0
0
KS1(Note 1)
KS2
KS3
KS4
KS5
20
0
0
1
S23(Note 2)
KS2
KS3
KS4
KS5
16
0
1
0
S23
S24
KS3
KS4
KS5
12
0
1
1
S23
S24
S25
KS4
KS5
8
1
0
0
S23
S24
S25
S26
KS5
4
1
0
1
S23
S24
S25
S26
S27
0
1
1
0
S23
S24
S25
S26
S27
0
○
1
1
1
S23
S24
S25
S26
S27
0
(Note 1) KSx: Keyscan Output(x = 1 to 5)
(Note 2) Sx: Segment Output(x = 23 to 27)
2. P0, P1, P2, P3 and P4: Segment / PWM / General Purpose output port switching control data
These control bits are used to select the function of the S5/P1/G1 to S20/P16/G16 output pins (Segment Output Pins or PWM
Output Pins or General Purpose Output Pins).
S5/
P1/
G1
S6/
P2/
G2
S7/
P3/
G3
S8/
P4/
G4
S9/
P5/
G5
S10/
P6/
G6
S11/
P7/
G7
S12/
P8/
G8
S5
P1/G1(Note 3)
P1/G1
P1/G1
P1/G1
P1/G1
P1/G1
P1/G1
P1/G1
P1/G1
P1/G1
P1/G1
P1/G1
P1/G1
P1/G1
P1/G1
P1/G1
P1/G1
P1/G1
P1/G1
P1/G1
P1/G1
P1/G1
P1/G1
P1/G1
P1/G1
P1/G1
P1/G1
P1/G1
P1/G1
P1/G1
P1/G1
S6
S6
P2/G2
P2/G2
P2/G2
P2/G2
P2/G2
P2/G2
P2/G2
P2/G2
P2/G2
P2/G2
P2/G2
P2/G2
P2/G2
P2/G2
P2/G2
P2/G2
P2/G2
P2/G2
P2/G2
P2/G2
P2/G2
P2/G2
P2/G2
P2/G2
P2/G2
P2/G2
P2/G2
P2/G2
P2/G2
P2/G2
S7
S7
S7
P3/G3
P3/G3
P3/G3
P3/G3
P3/G3
P3/G3
P3/G3
P3/G3
P3/G3
P3/G3
P3/G3
P3/G3
P3/G3
P3/G3
P3/G3
P3/G3
P3/G3
P3/G3
P3/G3
P3/G3
P3/G3
P3/G3
P3/G3
P3/G3
P3/G3
P3/G3
P3/G3
P3/G3
P3/G3
S8
S8
S8
S8
P4/G4
P4/G4
P4/G4
P4/G4
P4/G4
P4/G4
P4/G4
P4/G4
P4/G4
P4/G4
P4/G4
P4/G4
P4/G4
P4/G4
P4/G4
P4/G4
P4/G4
P4/G4
P4/G4
P4/G4
P4/G4
P4/G4
P4/G4
P4/G4
P4/G4
P4/G4
P4/G4
P4/G4
S9
S9
S9
S9
S9
P5/G5
P5/G5
P5/G5
P5/G5
P5/G5
P5/G5
P5/G5
P5/G5
P5/G5
P5/G5
P5/G5
P5/G5
P5/G5
P5/G5
P5/G5
P5/G5
P5/G5
P5/G5
P5/G5
P5/G5
P5/G5
P5/G5
P5/G5
P5/G5
P5/G5
P5/G5
P5/G5
S10
S10
S10
S10
S10
S10
P6/G6
P6/G6
P6/G6
P6/G6
P6/G6
P6/G6
P6/G6
P6/G6
P6/G6
P6/G6
P6/G6
P6/G6
P6/G6
P6/G6
P6/G6
P6/G6
P6/G6
P6/G6
P6/G6
P6/G6
P6/G6
P6/G6
P6/G6
P6/G6
P6/G6
P6/G6
S11
S11
S11
S11
S11
S11
S11
P7/G7
P7/G7
P7/G7
P7/G7
P7/G7
P7/G7
P7/G7
P7/G7
P7/G7
P7/G7
P7/G7
P7/G7
P7/G7
P7/G7
P7/G7
P7/G7
P7/G7
P7/G7
P7/G7
P7/G7
P7/G7
P7/G7
P7/G7
P7/G7
P7/G7
S12
S12
S12
S12
S12
S12
S12
S12
P8/G8
P8/G8
P8/G8
P8/G8
P8/G8
P8/G8
P8/G8
P8/G8
P8/G8
P8/G8
P8/G8
P8/G8
P8/G8
P8/G8
P8/G8
P8/G8
P8/G8
P8/G8
P8/G8
P8/G8
P8/G8
P8/G8
P8/G8
P8/G8
P4
S13/
P9/
G9
S14/
P10/
G10
S15/
P11/
G11
S16/
P12/
G12
S17/
P13/
G13
S18/
P14/
G14
S19/
P15/
G15
S20/
P16
G16
Reset
condition
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
S13
S13
S13
S13
S13
S13
S13
S13
S13
P9/G9
P9/G9
P9/G9
P9/G9
P9/G9
P9/G9
P9/G9
P9/G9
P9/G9
P9/G9
P9/G9
P9/G9
P9/G9
P9/G9
P9/G9
P9/G9
P9/G9
P9/G9
P9/G9
P9/G9
P9/G9
P9/G9
P9/G9
S14
S14
S14
S14
S14
S14
S14
S14
S14
S14
P10/G10
P10/G10
P10/G10
P10/G10
P10/G10
P10/G10
P10/G10
P10/G10
P10/G10
P10/G10
P10/G10
P10/G10
P10/G10
P10/G10
P10/G10
P10/G10
P10/G10
P10/G10
P10/G10
P10/G10
P10/G10
P10/G10
S15
S15
S15
S15
S15
S15
S15
S15
S15
S15
S15
P11/G11
P11/G11
P11/G11
P11/G11
P11/G11
P11/G11
P11/G11
P11/G11
P11/G11
P11/G11
P11/G11
P11/G11
P11/G11
P11/G11
P11/G11
P11/G11
P11/G11
P11/G11
P11/G11
P11/G11
P11/G11
S16
S16
S16
S16
S16
S16
S16
S16
S16
S16
S16
S16
P12/G12
P12/G12
P12/G12
P12/G12
P12/G12
P12/G12
P12/G12
P12/G12
P12/G12
P12/G12
P12/G12
P12/G12
P12/G12
P12/G12
P12/G12
P12/G12
P12/G12
P12/G12
P12/G12
P12/G12
S17
S17
S17
S17
S17
S17
S17
S17
S17
S17
S17
S17
S17
P13/G13
P13/G13
P13/G13
P13/G13
P13/G13
P13/G13
P13/G13
P13/G13
P13/G13
P13/G13
P13/G13
P13/G13
P13/G13
P13/G13
P13/G13
P13/G13
P13/G13
P13/G13
P13/G13
S18
S18
S18
S18
S18
S18
S18
S18
S18
S18
S18
S18
S18
S18
P14/G14
P14/G14
P14/G14
P14/G14
P14/G14
P14/G14
P14/G14
P14/G14
P14/G14
P14/G14
P14/G14
P14/G14
P14/G14
P14/G14
P14/G14
P14/G14
P14/G14
P14/G14
S19
S19
S19
S19
S19
S19
S19
S19
S19
S19
S19
S19
S19
S19
S19
P15/G15
P15/G15
P15/G15
P15/G15
P15/G15
P15/G15
P15/G15
P15/G15
P15/G15
P15/G15
P15/G15
P15/G15
P15/G15
P15/G15
P15/G15
P15/G15
P15/G15
S20
S20
S20
S20
S20
S20
S20
S20
S20
S20
S20
S20
S20
S20
S20
S20
P16/G16
P16/G16
P16/G16
P16/G16
P16/G16
P16/G16
P16/G16
P16/G16
P16/G16
P16/G16
P16/G16
P16/G16
P16/G16
P16/G16
P16/G16
P16/G16
○
-
P0
P1
P2
P3
P4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
P0
P1
P2
P3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Reset
condition
○
-
(Note 3) Px/Gx : PWM output or General Purpose output (x = 1 to 16)
PWM is selected by PGx(x = 1 to 6) control data bit
Internal PWM or external PWM output or General Purpose output is selected by EPx(x = 1 to 6).
External PWM / General Purpose output is selected by EPx(x = 7 to 16).
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MAX 116 Segments (29SEG x 4COM)
Datasheet
Control Data Functions – continued
When the General Purpose Output Port Function is selected, the correspondence between the output pins and therespective
display data is given in the table below.
Corresponding Display Data
Output Pins
1/4 Duty mode
1/3 Duty mode
1/2 Duty mode
Static mode
S5/P1/G1
D17
D13
D9
D5
S6/P2/G2
D21
D16
D11
D6
S7/P3/G3
D25
D19
D13
D7
S8/P4/G4
D29
D22
D15
D8
S9/P5/G5
D33
D25
D17
D9
S10/P6/G6
D37
D28
D19
D10
S11/P7/G7
D41
D31
D21
D11
S12/P8/G8
D45
D34
D23
D12
S13/P9/G9
D49
D37
D25
D13
S14/P10/G10
D53
D40
D27
D14
S15/P11/G11
D57
D43
D29
D15
S16/P12/G12
D61
D46
D31
D16
S17/P13/G13
D65
D49
D33
D17
S18/P14/G14
D69
D52
D35
D18
S19/P15/G15
D73
D55
D37
D19
S20/P16/G16
D77
D58
D39
D20
When the General Purpose Output Port Function is selected, the respective output pin outputs a “HIGH” level when its
corresponding display data is set to “1”. Likewise, it will output a “LOW” level, if its corresponding display data is set to “0”. For
example, at 1/4 Duty mode, S8/P4/G4 is used as a General Purpose Output Port, if its corresponding display data D29 is set
to “1”, then S8/P4/G4 will output “HIGH” level. Likewise, if D29 is set to “0”, then S8/P4/G4 will output “LOW” level.
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Datasheet
MAX 116 Segments (29SEG x 4COM)
Control Data Functions – continued
3. FL: Line Inversion or Frame Inversion switching control data
This control data bit selects either line inversion mode or frame inversion mode.
FL
Inversion mode
Reset condition
○
0
Line Inversion
1
Frame Inversion
Typically, when driving large capacitance LCD, Line inversion will increase the influence of crosstalk.
Regarding driving waveform, refer to LCD Driving Waveforms.
4. DR: 1/3 bias drive or 1/2 bias drive switching control data
This control data bit selects either 1/3 bias drive or 1/2 bias drive.
DR
Bias drive scheme
Reset condition
○
0
1/3 bias drive
1
1/2 bias drive
The settings take effect if except Static are already set by DT0 and DT1 control bits.
5. DT: 1/4 duty drive, 1/3 duty drive, 1/2 duty drive or Static drive switching control data
These control data bits select either 1/4 duty drive, 1/3 duty drive, 1/2 duty drive or Static drive
DT0
DT1
Duty drive scheme
Reset condition
0
0
Static drive
0
1
1/2 duty drive
1
0
1/3 duty drive
○
1
1
1/4 duty drive
6. FC0, FC1, FC2, FC3, FC4, FC5, and FC6: Common/Segment output waveform frame frequency switching control data
These control data bits set the frame frequency for common and segment output waveforms.
Frame Frequency
Reset
FC0
FC1
FC2
FC3
FC4
FC5
FC6
fo(Hz)
condition
0
0
0
0
0
0
0
fOSC(Note) /12000
○
0
0
0
0
0
0
1
fOSC /10908
0
0
0
0
0
1
0
fOSC /10000
0
0
0
0
0
1
1
fOSC /9230
0
0
0
0
1
0
0
fOSC /8572
0
0
0
0
1
0
1
fOSC /8000
0
0
0
0
1
1
0
fOSC /7500
0
0
0
0
1
1
1
fOSC /7058
0
0
0
1
0
0
0
fOSC /6666
0
0
0
1
0
0
1
fOSC /6316
0
0
0
1
0
1
0
fOSC /6000
0
0
0
1
0
1
1
fOSC /5714
0
0
0
1
1
0
0
fOSC /5454
0
0
0
1
1
0
1
fOSC /5218
0
0
0
1
1
1
0
fOSC /5000
0
0
0
1
1
1
1
fOSC /4800
0
0
1
0
0
0
0
fOSC /4616
0
0
1
0
0
0
1
fOSC /4444
0
0
1
0
0
1
0
fOSC /4286
0
0
1
0
0
1
1
fOSC /4138
0
0
1
0
1
0
0
fOSC /4000
0
0
1
0
1
0
1
fOSC /3870
0
0
1
0
1
1
0
fOSC /3750
0
0
1
0
1
1
1
fOSC /3636
0
0
1
1
0
0
0
fOSC /3530
0
0
1
1
0
0
1
fOSC /3428
0
0
1
1
0
1
0
fOSC /3334
0
0
1
1
0
1
1
fOSC /3244
0
0
1
1
1
0
0
fOSC /3158
0
0
1
1
1
0
1
fOSC /3076
(Note) fOSC: Internal oscillation frequency (600 kHz Typ)
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Datasheet
MAX 116 Segments (29SEG x 4COM)
Control Data Functions – continued
FC0
FC1
FC2
FC3
FC4
FC5
FC6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Frame Frequency
fo(Hz)
(Note)
fOSC
/3000
fOSC /2926
fOSC /2858
fOSC /2790
fOSC /2728
fOSC /2666
fOSC /2608
fOSC /2554
fOSC /2500
fOSC /2448
fOSC /2400
fOSC /2352
fOSC /2308
fOSC /2264
fOSC /2222
fOSC /2182
fOSC /2142
fOSC /2106
fOSC /2068
fOSC /2034
fOSC /2000
fOSC /1968
fOSC /1936
fOSC /1904
fOSC /1874
fOSC /1846
fOSC /1818
fOSC /1792
fOSC /1764
fOSC /1740
fOSC /1714
fOSC /1690
fOSC /1666
fOSC /1644
fOSC /1622
fOSC /1600
fOSC /1578
fOSC /1558
fOSC /1538
fOSC /1518
fOSC /1500
fOSC /1482
fOSC /1464
fOSC /1446
fOSC /1428
fOSC /1412
fOSC /1396
fOSC /1380
fOSC /1364
fOSC /1348
Reset
condition
-
(Note) fOSC: Internal oscillation frequency (600 kHz Typ)
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Datasheet
MAX 116 Segments (29SEG x 4COM)
Control Data Functions – continued
FC0
FC1
FC2
FC3
FC4
FC5
FC6
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Frame Frequency
fo(Hz)
(Note)
fOSC
/1334
fOSC /1318
fOSC /1304
fOSC /1290
fOSC /1276
fOSC /1264
fOSC /1250
fOSC /1238
fOSC /1224
fOSC /1212
fOSC /1200
fOSC /1188
fOSC /1176
fOSC /1166
fOSC /1154
fOSC /1142
fOSC /1132
fOSC /1122
fOSC /1112
fOSC /1100
fOSC /1090
fOSC /1082
fOSC /1072
fOSC /1062
fOSC /1052
fOSC /1044
fOSC /1034
fOSC /1026
fOSC /1016
fOSC /1008
fOSC /1000
fOSC /992
fOSC /984
fOSC /976
fOSC /968
fOSC /960
fOSC /952
fOSC /944
fOSC /938
fOSC /930
fOSC /924
fOSC /916
fOSC /910
fOSC /902
fOSC /896
fOSC /888
fOSC /882
fOSC /876
Reset
condition
-
(Note) fOSC: Internal oscillation frequency (600 kHz Typ)
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Datasheet
MAX 116 Segments (29SEG x 4COM)
Control Data Functions – continued
7. OC: Internal oscillator operating mode/External clock operating mode switching control data in OSCIN/S37
These control data bits select either Internal oscillator operating or External clock operating mode.
Reset
OC
Operating mode
In/Out pin(OSCIN/S37) status
condition
0
Internal oscillator
S37 (segment output)
○
1
External Clock
OSCIN (clock input)
OC = 1: the OSCIN/S37 pin can be used as input clock pin when External Clock is set by the control data.
Internal oscillation/external clock select signal behavior is below.
Please input external clock after serial data sending.
SCE
SCL
SDI
0
1
1
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
D1
D2
OC
Display Data/
Control Data
Dev ice Code
8bits
SC
BU0
BU1
BU2
0
0
DD
2 bits
Internal oscillation・Extarnal Clock
Select signal(Internal signal)
Internal oscillation
OSC
(Internal signal)
Extarnal Clocl
(OSCIN)
8. SC: Segment on/off switching control data
This control data bit controls the on/off state of the segments.
Reset
condition
0
On
1
Off
○
Note that when the segments are turned off by setting SC to “1”, the segments are turned off by outputting segment
off waveforms from the segment output pins.
SC
Display state
9. BU0, BU1 and BU2: Normal mode/power-saving mode switching control data
These control data bits select either normal mode or power-saving mode.
OSC
Segment outputs Output Pin States During Key Scan Standby
Reset
BU0
BU1 BU2
Mode
Oscillator
Common outputs
condition
KS1
KS2
KS3
KS4
KS5
0
0
0
Normal
Operating
Operating
H
H
H
H
H
0
0
1
L
L
L
L
H
0
1
0
L
L
L
H
H
0
1
1
L
L
H
H
H
Power
1
0
0
Stopped
Low(VSS)
L
H
H
H
H
-saving
1
0
1
H
H
H
H
H
1
1
0
H
H
H
H
H
1
1
1
H
H
H
H
H
○
Power-saving mode status: S5/P1/G1 to S20/P16/G16 = active only General Purpose output
S21 to S22 = low (VSS)
KS1/S23 to KS5/S27 = low (VSS)
KI1/S32 to KS4/S35 = low (VSS)
PWMIN/S36 = low (VSS)
OSCIN/S37 = low (VSS)
COM1 to COM4 = low (VSS)
Stop the LCD drive bias voltage generation circuit
Stop the Internal oscillation circuit
However, serial data transfer is possible when at Power-saving mode.
Regarding the details of INHb pin and the control of each output, refer to “INHb Pin and Display Control”.
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Datasheet
MAX 116 Segments (29SEG x 4COM)
Control Data Functions – continued
10. PG1, PG2, PG3, PG4, PG5 and PG6 : PWM/General Purpose output switching control data
This control data bit selects either PWM output or General Purpose output of Px/Gx pins. (x = 1 to 6)
Reset
PGx(x = 1 to 6)
Px/Gx(x = 1 to 6) pin status
condition
0
PWM output
○
1
General Purpose output
The Px/Gx pin settings take effect only if PWM / General Purpose Output are already set by P0 to P4 control bits.
Normal behavior of changing GPO to PWM is below.
- PWM operation is started by command import timing of DD: 01 during GPO → PWM change.
- Please take care of reflect timing of new duty setting of DD: 10 and DD: 11 is from the next PWM.
DD: 00
DD: 01
DD: 10
DD: 11
SCE
GPO ---> PWM change
new duty decided timing
PWM/GPO output
start of PWM operation
next PWM cycle
(PWM waveform in immediate duty)
(PWM waveform in new duty)
In order to avoid this operation, please input commands in reverse as below.
DD:10
DD:11
DD:01
DD:00
SCE
new duty decided timing
GPO --＞PWM change
PWM/GPO output
Start of PWM operation
(PWM waveform on new duty)
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Datasheet
MAX 116 Segments (29SEG x 4COM)
Control Data Functions – continued
11. PF0, PF1, PF2, and PF3: PWM output waveform frame frequency switching control data
These control data bits set the frame frequency for PWM output waveforms of Px/Gx pins. (x = 1 to 6).
PWM output Frame
Reset
PF0
PF1
PF2
PF3
Frequency fp(Hz)
condition
0
0
0
0
fOSC/4096
○
0
0
0
1
fOSC/3840
0
0
1
0
fOSC/3584
0
0
1
1
fOSC/3328
0
1
0
0
fOSC/3072
0
1
0
1
fOSC/2816
0
1
1
0
fOSC/2560
0
1
1
1
fOSC/2304
1
0
0
0
fOSC/2048
1
0
0
1
fOSC/1792
1
0
1
0
fOSC/1536
1
0
1
1
fOSC/1280
1
1
0
0
fOSC/1024
1
1
0
1
fOSC/768
1
1
1
0
fOSC/512
1
1
1
1
fOSC/256
The following can output PWM output waveforms when selected.
P0 to P4: PWM / General Purpose output is selected.
PG1 to PG6: PWM output is selected.
EP1 to EP6: Internal PWM is selected.
12. CT0, CT1, CT2 and CT3: LCD display contrast switching control data
These control data bits set display contrast
LCD Drive bias voltage
for VLCD Level
0
0
0
0
1.000*VDD
0
0
0
1
0.975*VDD
0
0
1
0
0.950*VDD
0
0
1
1
0.925*VDD
0
1
0
0
0.900*VDD
0
1
0
1
0.875*VDD
0
1
1
0
0.850*VDD
0
1
1
1
0.825*VDD
1
0
0
0
0.800*VDD
1
0
0
1
0.775*VDD
1
0
1
0
0.750*VDD
1
0
1
1
0.725*VDD
1
1
0
0
0.700*VDD
1
1
0
1
0.675*VDD
1
1
1
0
0.650*VDD
1
1
1
1
0.625*VDD
These control data bits set VLCD voltage level (the max level voltage of LCD driving voltage).
CT0
CT1
CT2
CT3
Reset
condition
○
-
Avoid setting VLCD voltage under 2.5 V.
And ensure “VDD – VLCD > 0.6 V” condition is satisfied.
Unstable IC output voltage may result if the above conditions are not satisfied.
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Datasheet
MAX 116 Segments (29SEG x 4COM)
Control Data Functions – continued
The relationship of LCD display contrast setting and VLCD voltage
CT
Setting
Formula
0
VDD
VLCD = 6.000 VLCD = 5.500 VLCD = 5.000 VLCD = 4.500 VLCD = 4.000 VLCD = 3.000 [V]
1
0.975*VDD
VLCD = 5.850 VLCD = 5.363 VLCD = 4.875 VLCD = 4.388 VLCD = 3.900 VLCD = 2.925 [V]
2
0.950*VDD
VLCD = 5.700 VLCD = 5.225 VLCD = 4.750 VLCD = 4.275 VLCD = 3.800 VLCD = 2.850 [V]
3
0.925*VDD
VLCD = 5.550 VLCD = 5.088 VLCD = 4.625 VLCD = 4.163 VLCD = 3.700 VLCD = 2.775 [V]
4
0.900*VDD
VLCD = 5.400 VLCD = 4.950 VLCD = 4.500 VLCD = 4.050 VLCD = 3.600 VLCD = 2.700 [V]
5
0.875*VDD
VLCD = 5.250 VLCD = 4.813 VLCD = 4.375 VLCD = 3.938 VLCD = 3.500 VLCD = 2.625 [V]
6
0.850*VDD
VLCD = 5.100 VLCD = 4.675 VLCD = 4.250 VLCD = 3.825 VLCD = 3.400 VLCD = 2.550 [V]
7
0.825*VDD
VLCD = 4.950 VLCD = 4.538 VLCD = 4.125 VLCD = 3.713 VLCD = 3.300 VLCD = 2.475 [V]
8
0.800*VDD
VLCD = 4.800 VLCD = 4.400 VLCD = 4.000 VLCD = 3.600 VLCD = 3.200 VLCD = 2.400 [V]
9
0.775*VDD
VLCD = 4.650 VLCD = 4.263 VLCD = 3.875 VLCD = 3.488 VLCD = 3.100 VLCD = 2.325 [V]
10
0.750*VDD
VLCD = 4.500 VLCD = 4.125 VLCD = 3.750 VLCD = 3.375 VLCD = 3.000 VLCD = 2.250 [V]
11
0.725*VDD
VLCD = 4.350 VLCD = 3.988 VLCD = 3.625 VLCD = 3.263 VLCD = 2.900 VLCD = 2.175 [V]
12
0.700*VDD
VLCD = 4.200 VLCD = 3.850 VLCD = 3.500 VLCD = 3.150 VLCD = 2.800 VLCD = 2.100 [V]
13
0.675*VDD
VLCD = 4.050 VLCD = 3.713 VLCD = 3.375 VLCD = 3.038 VLCD = 2.700 VLCD = 2.025 [V]
14
0.650*VDD
VLCD = 3.900 VLCD = 3.575 VLCD = 3.250 VLCD = 2.925 VLCD = 2.600 VLCD = 1.950 [V]
15
0.625*VDD
VLCD = 3.750 VLCD = 3.438 VLCD = 3.125 VLCD = 2.813 VLCD = 2.500 VLCD = 1.875 [V]
VDD = 6.000
VDD = 5.500
VDD = 5.000
VDD = 4.500
VDD = 4.000
VDD = 3.000
[V]
Disabled
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Datasheet
MAX 116 Segments (29SEG x 4COM)
Control Data Functions – continued
13. EP1, EP2, EP3, EP4, EP5,EP7,EP8,EP9,EP10,EP11,EP12,EP13,EP14,EP15 and EP16 :
Internal PWM/External PWM switching control data (EP1-EP6),
GPO/External PWM switching control data (EP7-EP16)
This control data bit select either External PWM output or internal generation PWM output of Px/Gx pins(x = 1 to 6).
EPx(x = 1 to 6)
Px/Gx(x = 1 to 6) pin status
Reset condition
0
Internal PWM
○
1
External PWM
The following can output PWM output waveforms when selected:
P0 to P4: PWM/General Purpose output is selected.
PG1 to PG6: PWM output is selected.
This control data bit select either GPO or external PWM output of Px/Gx pins(x = 7 to 16).
EPx(x = 7 to 16)
Px/Gx(x = 7 to 16) pin status
Reset condition
0
GPO
○
1
External PWM output
The following can output PWM output waveforms when selected:
P0 to P4: PWM/General Purpose output is selected.
If any one of external PWM setting in EP1-EP16, PWMIN/S36 pin can be as input pin.
The relation of P0 to P4, Px/Gx(x = 1 to 6), EP1 to EP16 is as follows
Internal PWM / External PWM
Output Switching
GPO/PWM
Output Switching
Segment / others
Output Switching
v
v
v
[PG1-PG6] ： PWM
/ GPO Output
Switching
[EP１-EP6] ： internal PWM
/ External PWM Output
Segment Output
PWMIN / S36
GPO
External PWM
1
0
0
[PF0-PF3] ： PWM Output
waveform Framw Frequency
Switching
Segment Output
[EP7-EP16] ： External
PWM / GPO Output
Switching
1
S5/G1/P1
0
S10/G6/P6
…
Internal PWM
Curcuit
1
[P0-P4] ： Segment
/ PWM/ GPO Output
Switching
[W10 to W18 - W60 to W68] ：
PWM Output Duty Switching
External PWM
1
PGx
EPx
EPx
(x = 1 to 6) (x = 1 to 6) (x = 7 to 16)
Sx(Note 1)
0
0
0
Sx(Note 1)
0
0
1
Sx(Note 1)
0
1
0
Sx(Note 1)
0
1
1
Sx(Note 1)
1
0
0
Sx(Note 1)
1
0
1
Sx(Note 1)
1
1
0
Sx(Note 1)
1
1
1
Px/Gx(Note 2)
0
0
0
Px/Gx(Note 2)
0
0
1
Px/Gx(Note 2)
0
1
0
Px/Gx(Note 2)
0
1
1
Px/Gx(Note 2)
1
0
0
Px/Gx(Note 2)
1
0
1
Px/Gx(Note 2)
1
1
0
Px/Gx(Note 2)
1
1
1
P0 to P4
GPO
0
Segment Output
Px/Gx (x = 1 to 6)
Segment Output
Segment Output
Segment Output
Segment Output
Segment Output
Segment Output
Segment Output
Segment Output
Internal PWM Output
Internal PWM Output
External PWM Output
External PWM Output
GPO
GPO
GPO
GPO
Pin status
Px/Gx(x = 7 to 16)
Segment Output
Segment Output
Segment Output
Segment Output
Segment Output
Segment Output
Segment Output
Segment Output
GPO
External PWM Output
GPO
External PWM Output
GPO
External PWM Output
GPO
External PWM Output
1
S11/G7/P7
0
S20/G16/P16
PWMIN / S36
Segment Output
PWMIN(Note 3)
PWMIN(Note 3)
PWMIN(Note 3)
Segment Output
PWMIN(Note 3)
PWMIN(Note 3)
PWMIN(Note 3)
Segment Output
PWMIN(Note 3)
PWMIN(Note 3)
PWMIN(Note 3)
Segment Output
PWMIN(Note 3)
PWMIN(Note 3)
PWMIN(Note 3)
…
If any one of External PWM setting
in EP1-EP16, PWMIN / S36 pin can
be used as input pin
Reset
condition
○
-
(Note 1) Sx : Segment output is selected (x = 5 to 20)
(Note 2) Px/Gx : PWM / General Purpose output is selected (x = 1 to 16)
(Note 3) PWMIN is External PWM input pin.
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MAX 116 Segments (29SEG x 4COM)
Control Data Functions – continued
14. W10 to W18(Note), W20 to W28, W30 to W38, W40 to W48, W50 to W58 and W60 to W68 : PWM output waveform
duty setting control data.
These control data bits set the high level pulse width (duty) for PWM output waveforms of Px/Gx pins (x = 1 to 6).
N = 1 to 6 , Tp = 1/fp
Reset
Wn0
Wn1
Wn2
Wn3
Wn4
Wn5
Wn6
Wn7
Wn8
PWM duty
condition
(0/256) x Tp
(1/256) x Tp
(2/256) x Tp
(3/256) x Tp
(4/256) x Tp
(5/256) x Tp
(6/256) x Tp
(7/256) x Tp
(8/256) x Tp
(9/256) x Tp
(10/256) x Tp
(11/256) x Tp
(12/256) x Tp
(13/256) x Tp
(14/256) x Tp
(15/256) x Tp
(16/256) x Tp
(17/256) x Tp
(18/256) x Tp
(19/256) x Tp
(20/256) x Tp
○
-
…
…
…
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
(235/256) x Tp
(236/256) x Tp
(237/256) x Tp
(238/256) x Tp
(239/256) x Tp
(240/256) x Tp
(241/256) x Tp
(242/256) x Tp
(243/256) x Tp
(244/256) x Tp
(245/256) x Tp
(246/256) x Tp
(247/256) x Tp
(248/256) x Tp
(249/256) x Tp
(250/256) x Tp
(251/256) x Tp
(252/256) x Tp
(253/256) x Tp
(254/256) x Tp
(255/256) x Tp
(256/256) x Tp
(256/256) x Tp
(256/256) x Tp
(256/256) x Tp
-
…
…
…
0
1
0
1
(256/256) x Tp
(256/256) x Tp
(256/256) x Tp
(256/256) x Tp
-
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
…
…
…
…
…
…
…
…
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
…
…
…
…
…
…
…
…
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
(Note)
W10 to W18:S5/P1/G1 PWM duty data
W20 to W28:S6/P2/G2 PWM duty data
W30 to W38:S7/P3/G3 PWM duty data
W40 to W48:S8/P4/G4 PWM duty data
W50 to W58:S9/P5/G5 PWM duty data
W60 to W68:S10/P6/G6 PWM duty data
It is effective at the case of the following setting.
P0 to P4 : PWM / General Purpose output selected is selected.
PG1 to PG6 : PWM output is selected.
EP1 to EP6 : Internal PWM is selected.
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Datasheet
MAX 116 Segments (29SEG x 4COM)
Display Data and Output Pin Correspondence
1. 1/4 duty
Output pin(Note)
S5/P1/G1
S6/P2/G2
S7/P3/G3
S8/P4/G4
S9/P5/G5
S10/P6/G6
S11/P7/G7
S12/P8/G8
S13/P9/G9
S14/P10/G10
S15/P11/G11
S16/P12/G12
S17/P13/G13
S18/P14/G14
S19/P15/G15
S20/P16/G16
S21
S22
KS1/S23
KS2/S24
KS3/S25
KS4/S26
KS5/S27
KI1/S32
KI2/S33
KI3/S34
KI4/S35
PWMIN/S36
OSCIN/S37
COM1
D17
D21
D25
D29
D33
D37
D41
D45
D49
D53
D57
D61
D65
D69
D73
D77
D81
D85
D89
D93
D97
D101
D105
D125
D129
D133
D137
D141
D145
COM2
D18
D22
D26
D30
D34
D38
D42
D46
D50
D54
D58
D62
D66
D70
D74
D78
D82
D86
D90
D94
D98
D102
D106
D126
D130
D134
D138
D142
D146
COM3
D19
D23
D27
D31
D35
D39
D43
D47
D51
D55
D59
D63
D67
D71
D75
D79
D83
D87
D91
D95
D99
D103
D107
D127
D131
D135
D139
D143
D147
COM4
D20
D24
D28
D32
D36
D40
D44
D48
D52
D56
D60
D64
D68
D72
D76
D80
D84
D88
D92
D96
D100
D104
D108
D128
D132
D136
D140
D144
D148
(Note) The Segment Output Port function is assumed to be selected for the output pins – S5/P1/G1 to S20/P16/G16, KS1/S23 to KS5/S27,
KI1/S32 to KI4/S35, PWMIN/S36, OSCIN/S37.
In case of BU97601FV-M, D1 to D16 and D109 to D124 are not available.
To illustrate further, the states of the S21 output pin is given in the table below.
Display data
State of S21 Output Pin
D81 D82
D83
D84
0
0
0
0
LCD Segments corresponding to COM1 to COM4 are OFF.
0
0
0
1
LCD Segment corresponding to COM4 is ON.
0
0
1
0
LCD Segment corresponding to COM3 is ON.
0
0
1
1
LCD Segments corresponding to COM3 and COM4 are ON.
0
1
0
0
LCD Segment corresponding to COM2 is ON.
0
1
0
1
LCD Segments corresponding to COM2 and COM4 are ON.
0
1
1
0
LCD Segments corresponding to COM2 and COM3 are ON.
0
1
1
1
LCD Segments corresponding to COM2, COM3 and COM4 are ON.
1
0
0
0
LCD Segment corresponding to COM1 is ON.
1
0
0
1
LCD Segments corresponding to COM1 and COM4 are ON.
1
0
1
0
LCD Segments corresponding to COM1 and COM3 are ON.
1
0
1
1
LCD Segments corresponding to COM1, COM3 and COM4 are ON.
1
1
0
0
LCD Segments corresponding to COM1 and COM2 are ON.
1
1
0
1
LCD Segments corresponding to COM1, COM2, and COM4 are ON.
1
1
1
0
LCD Segments corresponding to COM1, COM2, and COM3 are ON.
1
1
1
1
LCD Segments corresponding to COM1 to COM4 are ON.
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Datasheet
MAX 116 Segments (29SEG x 4COM)
Display Data and Output Pin Correspondence – continued
2. 1/3 duty
Output pin(Note)
S5/P1/G1
S6/P2/G2
S7/P3/G3
S8/P4/G4
S9/P5/G5
S10/P6/G6
S11/P7/G7
S12/P8/G8
S13/P9/G9
S14/P10/G10
S15/P11/G11
S16/P12/G12
S17/P13/G13
S18/P14/G14
S19/P15/G15
S20/P16/G16
S21
S22
KS1/S23
KS2/S24
KS3/S25
KS4/S26
KS5/S27
KI1/S32
KI2/S33
KI3/S34
KI4/S35
PWMIN/S36
OSCIN/S37
COM1
D13
D16
D19
D22
D25
D28
D31
D34
D37
D40
D43
D46
D49
D52
D55
D58
D61
D64
D67
D70
D73
D76
D79
D94
D97
D100
D103
D106
D109
COM2
D14
D17
D20
D23
D26
D29
D32
D35
D38
D41
D44
D47
D50
D53
D56
D59
D62
D65
D68
D71
D74
D77
D80
D95
D98
D101
D104
D107
D110
COM3
D15
D18
D21
D24
D27
D30
D33
D36
D39
D42
D45
D48
D51
D54
D57
D60
D63
D66
D69
D72
D75
D78
D81
D96
D99
D102
D105
D108
D111
(Note) The Segment Output Port function is assumed to be selected for the output pins – S5/P1/G1 to S20/P16/G16, KS1/S23 to KS5/S27,
KI1/S32 to KI4/S35, PWMIN/S36, OSCIN/S37.
In case of BU97601FV-M, D1 to D12 and D82 to D93 are not available.
To illustrate further, the states of the S21 output pin is given in the table below.
Display data
State of S21 Output Pin
D61 D62
D63
0
0
0
LCD Segments corresponding to COM1 to COM3 are OFF.
0
0
1
LCD Segment corresponding to COM3 is ON.
0
1
0
LCD Segment corresponding to COM2 is ON.
0
1
1
LCD Segments corresponding to COM2 and COM3 are ON.
1
0
0
LCD Segment corresponding to COM1 is ON.
1
0
1
LCD Segments corresponding to COM1 and COM3 are ON.
1
1
0
LCD Segments corresponding to COM1 and COM2 are ON.
1
1
1
LCD Segments corresponding to COM1 to COM3 are ON.
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Datasheet
MAX 116 Segments (29SEG x 4COM)
Display Data and Output Pin Correspondence – continued
3. 1/2 duty
Output pin(Note)
S5/P1/G1
S6/P2/G2
S7/P3/G3
S8/P4/G4
S9/P5/G5
S10/P6/G6
S11/P7/G7
S12/P8/G8
S13/P9/G9
S14/P10/G10
S15/P11/G11
S16/P12/G12
S17/P13/G13
S18/P14/G14
S19/P15/G15
S20/P16/G16
S21
S22
KS1/S23
KS2/S24
KS3/S25
KS4/S26
KS5/S27
KI1/S32
KI2/S33
KI3/S34
KI4/S35
PWMIN/S36
OSCIN/S37
COM1
D9
D11
D13
D15
D17
D19
D21
D23
D25
D27
D29
D31
D33
D35
D37
D39
D41
D43
D45
D47
D49
D51
D53
D63
D65
D67
D69
D71
D73
COM2
D10
D12
D14
D16
D18
D20
D22
D24
D26
D28
D30
D32
D34
D36
D38
D40
D42
D44
D46
D48
D50
D52
D54
D64
D66
D68
D70
D72
D74
(Note) The Segment Output Port function is assumed to be selected for the output pins – S5/P1/G1 to S20/P16/G16, KS1/S23 to KS5/S27,
KI1/S32 to KI4/S35, PWMIN/S36, OSCIN/S37.
In case of BU97601FV-M, D1 to D8 and D55 to D62 are not available.
To illustrate further, the states of the S21 output pin is given in the table below.
Display data
State of S21 Output Pin
D41
D42
0
0
LCD Segments corresponding to COM1 and COM2 are OFF.
0
1
LCD Segment corresponding to COM2 is ON.
1
0
LCD Segment corresponding to COM1 is ON.
1
1
LCD Segments corresponding to COM1 and COM2 are ON.
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MAX 116 Segments (29SEG x 4COM)
Display Data and Output Pin Correspondence – continued
4. Static
Output pin(Note)
S5/P1/G1
S6/P2/G2
S7/P3/G3
S8/P4/G4
S9/P5/G5
S10/P6/G6
S11/P7/G7
S12/P8/G8
S13/P9/G9
S14/P10/G10
S15/P11/G11
S16/P12/G12
S17/P13/G13
S18/P14/G14
S19/P15/G15
S20/P16/G16
S21
S22
KS1/S23
KS2/S24
KS3/S25
KS4/S26
KS5/S27
KI1/S32
KI2/S33
KI3/S34
KI4/S35
PWMIN/S36
OSCIN/S37
COM1
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D32
D33
D34
D35
D36
D37
(Note) The Segment Output Port function is assumed to be selected for the output pins – S5/P1/G1 to S20/P16/G16, KS1/S23 to KS5/S27,
KI1/S32 to KI4/S35, PWMIN/S36, OSCIN/S37.
In case of BU97601FV-M, D1 to D4 and D28 to D31 are not available.
To illustrate further, the states of the S21 output pin is given in the table below.
Display data
State of S21 Output Pin
D21
0
LCD Segment corresponding to COM1 is OFF.
LCD Segment corresponding to COM1 is ON.
1
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MAX 116 Segments (29SEG x 4COM)
Serial Data Output
1. When SCL is stopped at the low level(Note 1)
SCE
SCL
SDI
1
1
0
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
SDO
X
KD17 KD18
KD1 KD2
PA
KD19 KD20
Output Data
Figure 15. Serial Data Output Format
(Note 1)
1. X = Don’t care
2. B0 to B3, A0 to A3: Serial Interface address
2. When SCL is stopped at the high level(Note 2)
SCE
SCL
SDI
1
1
0
0
B0
B1
B2
B3
0
0
1
0
A0
A1
A2
A3
SDO
KD1
KD2
KD18
KD3
KD19
KD20
PA
X
Output Data
Figure 16. Serial Data Output Format
(Note 2)
1. X = Don’t care
2. B0 to B3, A0 to A3: Serial Interface address
3. Serial Interface address: 43H
4. KD1 to KD20: Key data
5. PA: Power-saving acknowledge data
6. If a key data read operation is executed when SDO is high, the read key data (KD1 to KD20) and power-saving acknowledge data (PA) will be invalid.
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MAX 116 Segments (29SEG x 4COM)
Output Data
1.KD1 to KD20: Key Data
When a key matrix of up to 20 keys is formed from the KS1 to KS5 output pins and the KI1 to KI4 input pins and one of those
keys is pressed, the key output data corresponding to that key will be set to 1. The table shows the relationship between
those pins and the key data bits.
Item
KS1
KS2
KS3
KS4
KS5
KI1
KD1
KD5
KD9
KD13
KD17
KI2
KD2
KD6
KD10
KD14
KD18
KI3
KD3
KD7
KD11
KD15
KD19
KI4
KD4
KD8
KD12
KD16
KD20
2.PA: Power-saving Acknowledge Data
This output data is set to the state when the key is pressed. In that case SDO will go to the low level. If serial data is input
during this period and the mode is set (normal mode or power-saving mode), the IC will be set to that mode. PA is set to 1 in
the power-saving mode and to 0 in the normal mode.
Power-saving Mode
Power-saving mode is activated when least one of control data BU0 or BU1 or BU2 is set to 1. All segment and common
outputs will go low. The oscillation circuit will stop (It can be restarted by a key press), thus reducing power consumption. This
mode can be disabled when control data bits BU0, BU1 and BU2 are all set to 0. However, note that the S5/P1/G1 to
S20/P16/G16 outputs can still be used as general-purpose output ports according to the state of the P0 to P4 control data bits,
even in power-saving mode. (See Control Data Functions)
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MAX 116 Segments (29SEG x 4COM)
Key Scan Operation Function
1. Key scan timing
The key scan period is 4640T(s). To reliably determine the on/off state of the keys, the BU97601FV-M scans the keys twice
and determines that a key has been pressed when the key data agrees. It outputs a key data read request (a low level on
SDO) 9904T(s) after starting a key scan. If the key data does not agree and a key was pressed at that point, it scans the keys
again. Thus the BU97601FV-M cannot detect a key press shorter than 9904T(s).
KS1
*
KS2
*
KS3
*
KS4
*
KS5
*
1
1
2
*
2
*
3
3
*
4
4
5
*
*
5
9280T[S]
T=
*
*
1
fOSC
Figure 17. Key Scan Timing(Note)
(Note) In power-saving mode the high/low state of these pins is determined by the BU0 to BU2 bits in the control data. Key scan output signals are not output from
pins that are set “L”.
2. In Normal Mode
The pins KS1 to KS5 are set “H”.
When a key is pressed a key scan is started and the keys are scanned until all keys are released. Multiple key presses are
recognized by determining whether multiple key data bits are set.
If a key is pressed for longer than 9904T(s) (Where T = 1/fOSC) the BU97601FV-M outputs a key data read request (a low level
on SDO) to the controller. The controller acknowledges this request and reads the key data. However, if SCE is high during a
serial data transfer, SDO will be set “H”.
After the controller reads the key data, the key data read request is cleared (SDO is set high) and the BU97601FV-M
performs another key scan. Also note that SDO, being an open-drain output, requires a pull-up resistor (between 1 kΩ and 10
kΩ)
Key Input 1
Key Input 2
Key scan
9904T[S]
9904T[S]
9904T[S]
SCE
Serial data transf er Serial data transf er
Key address(43H)
Serial data transf er
Key address
Key address
SDI
SDO
Key data read
Key data read
Key data read request
Key data read request
Key data read
Key data read request
1
T=
f
OSC
Figure 18. Key Scan Operation in Normal Mode
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MAX 116 Segments (29SEG x 4COM)
Key Scan Operation Function – continued
3. In Power-saving mode
The pins KS1 to KS5 are set to high or low by the BU0 to BU2 bits in the control data. (See the control data description for
details.)
If a key on one of the lines corresponding to a KS1 to KS5 pin which is set high is pressed, the oscillator on the OSC pin is
started and a key scan is performed. Keys are scanned until all keys are released. Multiple key presses are recognized by
determining whether multiple key data bits are set.
If a key is pressed for longer than 9904T(s)(Where T = 1/fOSC) the BU97601FV-M outputs a key data read request (a low level
on SDO) to the controller. The controller acknowledges this request and reads the key data. However, if SCE is high during a
serial data transfer, SDO will be set high.
After the controller reads the key data, the key data read request is cleared (SDO is set high) and the BU97601FV-M
performs another key scan. However, this does not clear power-saving mode. Also note that SDO, being an open-drain output,
requires a pull-up resistor (between 1 kΩ and 10 kΩ).
Power-saving mode key scan example
Example: BU0 = 0, BU1 = 0, BU2 = 1 (only KS5 high level output)
KS1/S23
KS2/S24
When any one of these keys is pressed,
the oscillator starts and a keys scan
operation is performed.
KS3/S25
KS4/S26
KS5/S27
(Note)
Kl1/S32
Kl2/S33
Kl3/S34
Kl4/S35
(Note)
These diodes are required to reliable recognize multiple key presses on the KS5 line when only KS5 is high, as in the above example. That is, these diodes
prevent incorrect operations due to sneak currents in the KS5 key scan output signal when keys on the KS1 to KS5 lines are pressed at the same time.
Key Input
Key scan
9904T[S]
9904T[S]
SCE
Serial data transf er Serial data transf er
Key address(43H)
Serial data transf er
Key address
SDI
SDO
Key data read
Key data read
Key data read request
Key data read request
T=
1
f osc
Figure 19. Key Scan Operation in Power-saving Mode
Multiple Key Presses
Although the BU97601FV-M is capable of key scanning without inserting diodes for dual key presses, triple key presses on
the KI1 to KI4 input pin lines or multiple key presses on the KS1 to KS5 output pin lines, multiple presses other than these
cases may result in keys that were not pressed recognized as having been pressed. Therefore, a diode must be inserted in
series with each key. Applications that do not recognize multiple key presses of three or more keys should check the key data
for three or more 1 bit and ignore such data.
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MAX 116 Segments (29SEG x 4COM)
Controller Key Data Read Technique
When the controller receives a key data read request from BU97601FV-M, it performs a key data read acquisition operation
using either the Timer Based Key Data Acquisition or the Interrupt Based Key Data Acquisition.
Timer Based Key Data Acquisition Technique
Under the Timer Based Key Data Acquisition Technique, the controller uses a timer to determine the states of the keys (ON or
OFF) and read the key data. Please refer to the flowchart below.
SCE ＝ 「L 」
NO
SDO ＝ 「L 」
YES
Key data read
processing
Key data read processing: Refer to “Serial Data Output”
Figure 20. Flowchart
In this technique, the controller uses a timer to determine key on/off states and read the key data. The controller must check
the SDO state when SCE is low every t7 period without fail. If SDO is low, the controller recognizes that a key has been
pressed and executes the key data read operation.
The period t7 in this technique must satisfy the following condition.
t7 > t4 + t5 + t6
If a key data read operation is executed when SDO is high, the read key data (KD1 to KD20) and power-saving acknowledge
data (PA) will be invalid.
Key on
Key on
Key Input
Key scan
t3
t4
t3
t3
SCE
t6
t6
t6
SDI
t5
t5
t5
Key data read
SDO
Key data read request
t7
t7
t7
t7
Controller determination Controller determination Controller determination Controller determination Controller determination
(key on)
(key on)
(key on)
(key on)
(key on)
t3: Key scan execution time when the key data agreed for two key scans. (9904T(s))
t4: Key scan execution time when the key data did not agree for two key scans and the key scan was executed again.
(19808T(s)) T = 1/fOSC
t5: Key address (43H) transfer time
t6: Key data read time
Figure 21. Timer Based Key Data Read Operation
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Datasheet
Controller Key Data Read Technique – continued
Interrupt Based Key Data Acquisition Technique
Under the Interrupt Based Key Data Acquisition Technique, the controller uses interrupts to determine the state of the keys
(ON or OFF) and read the key data. Please refer to the flow chart diagram below.
CE ＝「L」
SCE
SDO
D0 ＝
「L」
NO
YES
Key data read
processing
Wait for at
least t8
NO
SDO
D0 ＝「H」
YES
Key off
Key data read processing: Refer to “Serial Data Output”
Figure 22. Flowchart
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MAX 116 Segments (29SEG x 4COM)
Controller Key Data Read Technique – continued
In this technique, the controller uses interrupts to determine key on/off states and read the key data. The controller must
check the SDO state when SCE is low. If SDO is low, the controller recognizes that a key has been pressed and executes the
key data read operation. After that the next key on/off determination is performed after the time t8 has elapsed by checking
the SDO state when SCE is low and reading the key data. The period t8 in this technique must satisfy t8 > t4.
If a key data read operation is executed when SDO is high, the read key data (KD1 to KD20) and power-saving acknowledge
data (PA) will be invalid.
Key on
Key on
Key Input
Key scan
t3
t3
t4
t3
SCE
t6
t6
t6
t6
SDI
t5
t5
t5
t5
Key data read
SDO
Key data read request
Controller
Controller
determination determination
(key on)
(key on)
t8
t8
t8
t8
Controller
determination
(key on)
Controller
determination
(key on)
Controller
determination
(key on)
Controller
determination
(key on)
t3: Key scan execution time when the key data agreed for two key scans. (9904T(s))
t4: Key scan execution time when the key data did not agree for two key scans and the key scan was executed again.
(19808T(s)) T = 1/fOSC
t5: Key address (43H) transfer time
t6: Key data read time
Figure 23. Interrupt Based Key Data Read Operation
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MAX 116 Segments (29SEG x 4COM)
LCD Driving Waveforms
1. Line Inversion 1/4 Duty 1/3 Bias Drive Scheme
fo[Hz]
V LCD
V LCD1
V LCD2
COM1
0V
V LCD
V LCD1
V LCD2
COM2
0V
V LCD
V LCD1
V LCD2
COM3
0V
V LCD
V LCD1
V LCD2
COM4
0V
V LCD
LCD driver output w hen all LCD
V LCD1
segment corresponding to COM1,
V LCD2
COM2, COM3 and COM4 are off
0V
V LCD
LCD driver output w hen only LCD segments
V LCD1
corresponding to COM1 is on
V LCD2
0V
V LCD
LCD driver output w hen only LCD segments
V LCD1
corresponding to COM2 is on.
V LCD2
0V
V LCD
LCD driver output w hen only LCD segments
V LCD1
corresponding to COM1 and COM2 are on.
V LCD2
0V
V LCD
LCD driver output w hen only LCD segments
V LCD1
corresponding to COM3 is on.
V LCD2
0V
V LCD
LCD driver output w hen LCD segments
V LCD1
corresponding to COM4 is on.
V LCD2
0V
V LCD
LCD driver output w hen LCD segments
V LCD1
corresponding to COM2 and COM3 are on
V LCD2
0V
V LCD
LCD driver output w hen LCD segments
V LCD1
corresponding to COM1, COM2, COM3,
V LCD2
COM4 are on
0V
Figure 24. LCD Waveform (Line Inversion, 1/4 DUTY, 1/3 BIAS)
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MAX 116 Segments (29SEG x 4COM)
LCD Driving Waveforms – continued
2. Line Inversion 1/4 Duty 1/2 Bias Drive Scheme
fo[Hz]
V LCD
V LCD1, V LCD2
COM1
0V
V LCD
V LCD1, V LCD2
COM2
0V
V LCD
V LCD1, V LCD2
COM3
0V
V LCD
V LCD1, V LCD2
COM4
0V
LCD driver output w hen all LCD
V LCD
segment corresponding to COM1,
V LCD1, V LCD2
COM2, COM3 and COM4 are off
0V
V LCD
LCD driver output w hen only LCD segments
V LCD1, V LCD2
corresponding to COM1 is on
0V
V LCD
LCD driver output w hen only LCD segments
V LCD1, V LCD2
corresponding to COM2 is on.
0V
V LCD
LCD driver output w hen only LCD segments
V LCD1, V LCD2
corresponding to COM1 and COM2 are on.
0V
V LCD
LCD driver output w hen only LCD segments
V LCD1, V LCD2
corresponding to COM3 is on.
0V
V LCD
LCD driver output w hen LCD segments
V LCD1, V LCD2
corresponding to COM1 and COM3 are on
0V
V LCD
LCD driver output w hen LCD segments
V LCD1, V LCD2
corresponding to COM2 and COM3 are on
0V
V LCD
LCD driver output w hen LCD segments
V LCD1, V LCD2
corresponding to COM1, COM2 and COM3 are on
0V
V LCD
LCD driver output w hen LCD segments
V LCD1, V LCD2
corresponding to COM4 is on
0V
V LCD
LCD driver output w hen LCD segments
V LCD1, V LCD2
corresponding to COM2 and COM4 are on
0V
V LCD
LCD driver output w hen LCD segments
V LCD1, V LCD2
corresponding to COM1, COM2, COM3
0V
and COM4 are on
Figure 25. LCD Waveform (Line Inversion, 1/4 DUTY, 1/2 BIAS)
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MAX 116 Segments (29SEG x 4COM)
LCD Driving Waveforms – continued
3. Line Inversion 1/3 Duty 1/3 Bias Drive Scheme
fo[Hz]
V LCD
V LCD1
V LCD2
COM1
0V
V LCD
V LCD1
V LCD2
COM2
0V
V LCD
V LCD1
V LCD2
COM3
0V
V LCD
LCD driver output w hen LCD segments
V LCD1
corresponding to COM1, COM2 and COM3 are off
V LCD2
0V
V LCD
LCD driver output w hen only LCD segments
V LCD1
corresponding to COM1 is on
V LCD2
0V
V LCD
LCD driver output w hen only LCD segments
V LCD1
corresponding to COM2 is on.
V LCD2
0V
V LCD
LCD driver output w hen only LCD segments
V LCD1
corresponding to COM1 and COM2 are on.
V LCD2
0V
V LCD
LCD driver output w hen only LCD segments
V LCD1
corresponding to COM3 is on.
V LCD2
0V
V LCD
LCD driver output w hen LCD segments
V LCD1
corresponding to COM1 and COM3 are on
V LCD2
0V
V LCD
LCD driver output w hen LCD segments
V LCD1
corresponding to COM2 and COM3 are on
V LCD2
0V
V LCD
LCD driver output w hen LCD segments
V LCD1
corresponding to COM1, COM2 and COM3 are on
V LCD2
0V
Figure 26. LCD Waveform (Line Inversion, 1/3 DUTY, 1/3 BIAS) (Note)
(Note) COM4 function is same as COM1 at 1/3 duty.
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MAX 116 Segments (29SEG x 4COM)
LCD Driving Waveforms – continued
4. Line Inversion 1/3 Duty 1/2 Bias Drive Scheme
fo[Hz]
V LCD
V LCD1, V LCD2
COM1
0V
V LCD
V LCD1, V LCD2
COM2
0V
V LCD
V LCD1, V LCD2
COM3
0V
V LCD
LCD driver output w hen LCD segments
V LCD1, V LCD2
corresponding to COM1, COM2 and COM3 are off
0V
V LCD
LCD driver output w hen only LCD segments
V LCD1, V LCD2
corresponding to COM1 is on
0V
V LCD
LCD driver output w hen only LCD segments
V LCD1, V LCD2
corresponding to COM2 is on.
0V
V LCD
LCD driver output w hen only LCD segments
V LCD1, V LCD2
corresponding to COM1 and COM2 are on.
0V
V LCD
LCD driver output w hen only LCD segments
V LCD1, V LCD2
corresponding to COM3 is on.
0V
V LCD
LCD driver output w hen LCD segments
V LCD1, V LCD2
corresponding to COM1 and COM3 are on
0V
V LCD
LCD driver output w hen LCD segments
V LCD1, V LCD2
corresponding to COM2 and COM3 are on
0V
V LCD
LCD driver output w hen LCD segments
V LCD1, V LCD2
corresponding to COM1, COM2 and COM3 are on
0V
Figure 27. LCD Waveform (Line Inversion, 1/3 DUTY, 1/2BIAS) (Note)
(Note) COM4 function is same as COM1 at 1/3 duty.
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MAX 116 Segments (29SEG x 4COM)
LCD Driving Waveforms – continued
5. Line Inversion 1/2 Duty 1/3 Bias Drive Scheme
fo[Hz]
V LCD
V LCD1
V LCD2
COM1
0V
V LCD
V LCD1
V LCD2
COM2
0V
V LCD
LCD driver output w hen LCD segments
V LCD1
corresponding to COM1 and COM2 are off
V LCD2
0V
V LCD
LCD driver output w hen only LCD segments
V LCD1
corresponding to COM1 is on
V LCD2
0V
V LCD
LCD driver output w hen only LCD segments
V LCD1
corresponding to COM2 is on
V LCD2
0V
V LCD
LCD driver output w hen LCD segments
V LCD1
corresponding to COM1 and COM2 are on
V LCD2
0V
Figure 28. LCD Waveform (Line Inversion, 1/2 DUTY, 1/3 BIAS) (Note)
(Note) COM3 function is same as COM1 at 1/2 duty. COM4 function is same as COM2 at 1/2 duty.
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MAX 116 Segments (29SEG x 4COM)
LCD Driving Waveforms – continued
6. Line Inversion 1/2 Duty 1/2 Bias Drive Scheme
fo[Hz]
V LCD
V LCD1, V LCD2
COM1
0V
V LCD
V LCD1, V LCD2
COM2
0V
V LCD
LCD driver output w hen only LCD segments
V LCD1, V LCD2
corresponding to COM1 and COM2 are off.
0V
V LCD
LCD driver output w hen only LCD segments
V LCD1, V LCD2
corresponding to COM1 is on
0V
V LCD
LCD driver output w hen only LCD segments
V LCD1, V LCD2
corresponding to COM2 is on.
0V
V LCD
LCD driver output w hen only LCD segments
V LCD1, V LCD2
corresponding to COM1 and COM2 are on.
0V
Figure 29. LCD Waveform (Line Inversion, 1/2 DUTY, 1/2BIAS) (Note)
(Note) COM3 function is same as COM1 at 1/2 duty. COM4 function is same as COM2 at 1/2 duty.
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MAX 116 Segments (29SEG x 4COM)
LCD Driving Waveforms – continued
7. Line Inversion Static Drive Scheme
fo[Hz]
V LCD
COM1
0V
V LCD
LCD driver output w hen all LCD
segments corresponding to COM1 is off
0V
V LCD
LCD driver output w hen all LCD
segments corresponding to COM1 is on
0V
Figure 30. LCD Waveform (Line Inversion, Static) (Note)
(Note) COM2, COM3 and COM4 function are same as COM1 at Static.
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MAX 116 Segments (29SEG x 4COM)
LCD Driving Waveforms – continued
8. Frame Inversion 1/4 Duty 1/3 Bias Drive Scheme
fo[Hz]
V LCD
V LCD1
V LCD2
COM1
0V
V LCD
V LCD1
V LCD2
COM2
0V
V LCD
V LCD1
V LCD2
COM3
0V
V LCD
V LCD1
V LCD2
COM4
0V
V LCD
LCD driver output w hen LCD segments
V LCD1
corresponding to COM1, COM2, COM3,
V LCD2
COM4 are off
0V
V LCD
LCD driver output w hen only LCD segments
V LCD1
corresponding to COM1 is on
V LCD2
0V
V LCD
LCD driver output w hen only LCD segments
V LCD1
corresponding to COM2 is on.
V LCD2
0V
V LCD
LCD driver output w hen only LCD segments
V LCD1
corresponding to COM1 and COM2 are on.
V LCD2
0V
V LCD
LCD driver output w hen only LCD segments
V LCD1
corresponding to COM3 is on.
V LCD2
0V
V LCD
LCD driver output w hen only LCD segments
V LCD1
corresponding to COM4 is on.
V LCD2
0V
V LCD
LCD driver output w hen LCD segments
V LCD1
corresponding to COM2 and COM3 are on
V LCD2
0V
V LCD
LCD driver output w hen LCD segments
V LCD1
corresponding to COM1, COM2, COM3,
V LCD2
COM4 are on
0V
Figure 31. LCD Waveform (Frame Inversion, 1/4 DUTY, 1/3BIAS)
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MAX 116 Segments (29SEG x 4COM)
LCD Driving Waveforms – continued
9. Frame Inversion 1/4 Duty 1/2 Bias Drive Scheme
fo[Hz]
V LCD
V LCD1, V LCD2
COM1
0V
V LCD
V LCD1, V LCD2
COM2
0V
V LCD
V LCD1, V LCD2
COM3
0V
V LCD
V LCD1, V LCD2
COM4
0V
LCD driver output w hen LCD segments
V LCD
corresponding to COM1, COM2, COM3
V LCD1, V LCD2
and COM4 are off
0V
V LCD
LCD driver output w hen only LCD segments
V LCD1, V LCD2
corresponding to COM1 is on
0V
V LCD
LCD driver output w hen only LCD segments
V LCD1, V LCD2
corresponding to COM2 is on.
0V
V LCD
LCD driver output w hen only LCD segments
V LCD1, V LCD2
corresponding to COM1 and COM2 are on.
0V
V LCD
LCD driver output w hen only LCD segments
V LCD1, V LCD2
corresponding to COM3 is on.
0V
V LCD
LCD driver output w hen LCD segments
V LCD1, V LCD2
corresponding to COM1 and COM3 are on
0V
V LCD
LCD driver output w hen LCD segments
V LCD1, V LCD2
corresponding to COM2 and COM3 are on
0V
V LCD
LCD driver output w hen LCD segments
V LCD1, V LCD2
corresponding to COM1, COM2 and COM3 are on
0V
V LCD
LCD driver output w hen LCD segments
V LCD1, V LCD2
corresponding to COM4 is on
0V
V LCD
LCD driver output w hen LCD segments
V LCD1, V LCD2
corresponding to COM2 and COM4 are on
0V
V LCD
LCD driver output w hen LCD segments
V LCD1, V LCD2
corresponding to COM1, COM2, COM3
0V
and COM4 are on
Figure 32. LCD Waveform (Frame Inversion, 1/4 DUTY, 1/2BIAS)
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MAX 116 Segments (29SEG x 4COM)
LCD Driving Waveforms – continued
10. Frame Inversion 1/3 Duty 1/3 Bias Drive Scheme
fo[Hz]
V LCD
V LCD1
V LCD2
COM1
0V
V LCD
V LCD1
V LCD2
COM2
0V
V LCD
V LCD1
V LCD2
COM3
0V
V LCD
LCD driver output w hen LCD segments
V LCD1
corresponding to COM1, COM2 and COM3 are off
V LCD2
0V
V LCD
LCD driver output w hen only LCD segments
V LCD1
corresponding to COM1 is on
V LCD2
0V
V LCD
LCD driver output w hen only LCD segments
V LCD1
corresponding to COM2 is on.
V LCD2
0V
V LCD
LCD driver output w hen only LCD segments
V LCD1
corresponding to COM1 and COM2 are on.
V LCD2
0V
V LCD
LCD driver output w hen only LCD segments
V LCD1
corresponding to COM3 is on.
V LCD2
0V
V LCD
LCD driver output w hen LCD segments
V LCD1
corresponding to COM1 and COM3 are on
V LCD2
0V
V LCD
LCD driver output w hen LCD segments
V LCD1
corresponding to COM2 and COM3 are on
V LCD2
0V
V LCD
LCD driver output w hen LCD segments
V LCD1
corresponding to COM1, COM2 and COM3 are on
V LCD2
0V
Figure 33. LCD Waveform (Frame Inversion, 1/3 DUTY, 1/3BIAS) (Note)
(Note) COM4 function is same as COM1 at 1/3 duty.
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MAX 116 Segments (29SEG x 4COM)
LCD Driving Waveforms – continued
11. Frame Inversion 1/3 Duty 1/2 Bias Drive Scheme
fo[Hz]
V LCD
V LCD1, V LCD2
COM1
0V
V LCD
V LCD1, V LCD2
COM2
0V
V LCD
V LCD1, V LCD2
COM3
0V
V LCD
LCD driver output w hen LCD segments
V LCD1, V LCD2
corresponding to COM1, COM2 and COM3 are off
0V
V LCD
LCD driver output w hen only LCD segments
V LCD1, V LCD2
corresponding to COM1 is on
0V
V LCD
LCD driver output w hen only LCD segments
V LCD1, V LCD2
corresponding to COM2 is on.
0V
V LCD
LCD driver output w hen only LCD segments
V LCD1, V LCD2
corresponding to COM1 and COM2 are on.
0V
V LCD
LCD driver output w hen only LCD segments
V LCD1, V LCD2
corresponding to COM3 is on.
0V
V LCD
LCD driver output w hen LCD segments
V LCD1, V LCD2
corresponding to COM1 and COM3 are on
0V
V LCD
LCD driver output w hen LCD segments
V LCD1, V LCD2
corresponding to COM2 and COM3 are on
0V
V LCD
LCD driver output w hen LCD segments
V LCD1, V LCD2
corresponding to COM1, COM2 and COM3 are on
0V
Figure 34. LCD Waveform (Frame Inversion, 1/3 DUTY, 1/2 BIAS) (Note)
(Note) COM4 function is same as COM1 at 1/3 duty.
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MAX 116 Segments (29SEG x 4COM)
LCD Driving Waveforms – continued
12. Frame Inversion 1/2 Duty 1/3 Bias Drive Scheme
fo[Hz]
V LCD
V LCD1
V LCD2
COM1
0V
V LCD
V LCD1
V LCD2
COM2
0V
V LCD
V LCD1
LCD driver output w hen LCD segments
V LCD2
corresponding to COM1 and COM2 are off
0V
V LCD
LCD driver output w hen only LCD segments
V LCD1
corresponding to COM1 is on
V LCD2
0V
V LCD
LCD driver output w hen only LCD segments
V LCD1
corresponding to COM2 is on
V LCD2
0V
V LCD
LCD driver output w hen LCD segments
V LCD1
corresponding to COM1 and COM2 are on
V LCD2
0V
Figure 35. LCD Waveform (Frame Inversion, 1/2 DUTY, 1/3BIAS) (Note)
(Note) COM3 function is same as COM1 at 1/2 duty. COM4 function is same as COM2 at 1/2 duty.
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MAX 116 Segments (29SEG x 4COM)
LCD Driving Waveforms – continued
13. Frame Inversion 1/2 Duty 1/2 Bias Drive Scheme
fo[Hz]
V LCD
V LCD1, V LCD2
COM1
0V
V LCD
V LCD1, V LCD2
COM2
0V
V LCD
LCD driver output w hen LCD segments
V LCD1, V LCD2
corresponding to COM1 and COM2 are off
0V
V LCD
LCD driver output w hen only LCD segments
V LCD1, V LCD2
corresponding to COM1 is on
0V
V LCD
LCD driver output w hen only LCD segments
V LCD1, V LCD2
corresponding to COM2 is on
0V
V LCD
LCD driver output w hen LCD segments
V LCD1, V LCD2
corresponding to COM1 and COM2 are on
0V
Figure 36. LCD Waveform (Frame Inversion, 1/2 DUTY, 1/2 BIAS) (Note)
(Note) COM3 function is same as COM1 at 1/2 duty. COM4 function is same as COM2 at 1/2 duty.
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Datasheet
MAX 116 Segments (29SEG x 4COM)
LCD Driving Waveforms – continued
14. Frame Inversion Static Drive Scheme
fo[Hz]
V LCD
COM1
0V
V LCD
LCD driver output w hen all LCD
segments corresponding to COM1 is off
0V
V LCD
LCD driver output w hen all LCD
segments corresponding to COM1 is on
0V
Figure 37. LCD Waveform (Frame Inversion, Static) (Note)
(Note) COM2, COM3 and COM4 function are same as COM1 at Static.
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Datasheet
MAX 116 Segments (29SEG x 4COM)
INHb Pin and Display Control
The INHb pin operates Display off of LCD.
INHb control depends on set pin function.
Below table shows terminal function and control by INHb pin.
Control
Pin Function
INHb = L
INHb = H
SEG/COM
Display forced off
Display on
PWM/GPO
Operation Stop
Operation Available
Key Scan
Available regardless of INHb
External Clock Input
External PWM Input
Available regardless of INHb
Below table shows pin name and pin state of INHb = L.
Each output state are decided by Control data(P0 to P4, KM0 to KM2, OC, EPx(x = 1 to 16), PGx(x = 1 to 6))
For the details, please refer to “Control Data Functions”.
Pin Function(Note) (In case of INHb = L)
Pin Name
SEG
COM
PWM
GPO
Keyscan
External
Clock Input
External
PWM Input
S5/P1/G1 to
S20/P16/G16
Stop
(VSS)
-
Stop
(VSS)
Stop
(VSS)
-
-
-
S1 to S4, S21 to S22,
S28 to S31
Stop
(VSS)
-
-
-
-
-
-
KS1/S23 to KS5/S27
Stop
(VSS)
-
-
-
Keyscan Output
operation
-
-
KI1/S32 to KI4/S35
Stop
(VSS)
-
-
-
Keyscan
Input
operation
-
-
PWMIN/S36
Stop
(VSS)
-
-
-
-
-
PWM Input
operation
OSCIN/S37
Stop
(VSS)
-
-
-
-
Clock Input
operation
-
COM1 to COM4
-
Stop
(VSS)
-
-
-
-
-
(Note) “-” means the terminal does not have the function
For example, S5/P1/G1 to S20/P16/G16 are not set COM, Keyscan, External Clock Input and External PWM Input
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MAX 116 Segments (29SEG x 4COM)
INHb Pin and Display Control – continued
Since the IC internal data (1/4-Duty: the display data D1 to D148 and the control data, 1/3-Duty: the display data D1 to D111
and the control data, 1/2-Duty: the display data D1 to D74 and the control data, Static: the display data D1 to D37 and the
control data) is undefined when power is first applied, applications should set the INHb pin low at the same time as power is
applied to turn off the display (This sets the S5 to S27, S32 to S37, COM1 to COM4 to the VSS level.) and during this period
send serial data from the controller. The controller should then set the INHb pin high after the data transfer has completed.
This procedure prevents meaningless displays at power on.
1. 1/4-Duty
t2 (Note 1)
90 %
V DET (Min)
VDD
VIL1
(Note 1)
INHb
t1
tc
(Note 1)
VIL1
SCE
Display data and control data transfer
Internal data
D1 to D37, KM0 to KM2,
P0 to P4, FL, DR, DT0 to DT1,
Undefined
OC, FC0 to FC6, SC, BU0 to BU2
Internal data
D38 to D74,EP1 to EP16,
Undefined
PG1 to PG6,PF0 to PF3, CT0 to CT1
Internal data
D75 to D111, W10 to
Undefined
Internal data
D112 to D148, W40 to W68
Undefined
(Note 2)
Default
(Note 2)
Default
(Note 2)
Default
Defined
Undefined
Defined
Undefined
Defined
Undefined
(Note 2)
Default
Undefined
Defined
(Note 1) t1 ≥ 0, t2 ≥ 0, tc: 10 µs(Min)
When VDD level is over 90 %, there may be cases where command is not received correctly in unstable VDD.
(Note 2) Display data are undefined. Regarding default value, refer to Reset Condition.
Figure 38. Power ON/OFF and INHb Control Sequence (1/4-Duty)
2. 1/3-Duty
(Note 3)
t2
90 %
V DET (Min)
VDD
VIL1
(Note 3)
INHb
t1
tc
(Note 3)
VIL1
SCE
Display data and control data transfer
Internal data
D1 to D37, KM0 to KM2,
Undefined
P0 to P4, FL, DR, DT0 to DT1,
OC, FC0 to FC6, SC, BU0 to BU2
Internal data
Undefined
D38 to D74,EP1 to EP16,
PG1 to PG6,PF0 to PF3, CT0 to CT1
Internal data
D75 to D111, W10 to W38
Undefined
Internal data
W40 to W68
Undefined
(Note 4)
Default
(Note 4)
Default
(Note 4)
Default
Defined
Undefined
Defined
Undefined
Defined
Undefined
(Note 4)
Default
Defined
Undefined
(Note 3) t1 ≥ 0, t2 ≥ 0, tc: 10 µs(Min)
When VDD level is over 90 %, there may be cases where command is not received correctly in unstable VDD.
(Note 4) Display data are undefined. Regarding default value, refer to Reset Condition.
Figure 39. Power ON/OFF and INHb Control Sequence (1/3-Duty)
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MAX 116 Segments (29SEG x 4COM)
INHb Pin and Display Control – continued
3. 1/2-Duty
t2 (Note 1)
90 %
V DET (Min)
VDD
VIL1
(Note 1)
INHb
t1
tc
(Note 1)
VIL1
SCE
Display data and control data transfer
Internal data
D1 to D37, KM0 to KM2,
Undefined
P0 to P4, FL, DR, DT0 to DT1,
OC, FC0 to FC6, SC, BU0 to BU2
Internal data
Undefined
D38 to D74,EP1 to EP16,
PG1 to PG6,PF0 to PF3, CT0 to CT1
Internal data
W10 to W38
Undefined
Internal data
W40 to W68
Undefined
(Note 2)
Default
(Note 2)
Default
(Note 2)
Default
Defined
Undefined
Defined
Undefined
Defined
Undefined
(Note 2)
Default
Defined
Undefined
(Note 1) t1 ≥ 0, t2 ≥ 0, tc: 10 µs(Min)
When VDD level is over 90 %, there may be cases where command is not received correctly in unstable VDD.
(Note 2) Display data are undefined. Regarding default value, refer to Reset Condition.
Figure 40. Power ON/OFF and INHb Control Sequence (1/2-Duty)
4. Static
(Note 3)
t2
90 %
V DET (Min)
VDD
VIL1
(Note 3)
INHb
t1
tc
(Note 3)
VIL1
SCE
Display data and control data transfer
Internal data
D1 to D37, KM0 to KM2,
P0 to P4, FL, DR, DT0 to DT1,
OC, FC0 to FC6, SC, BU0 to BU2
Internal data
EP1 to EP16, PG1 to PG6,
PF0 to PF3, CT0 to CT1
Undefined
Undefined
Internal data
W10 to W38
Undefined
Internal data
W40 to W68
Undefined
(Note 4)
Default
(Note 4)
Default
(Note 4)
Default
Defined
Undefined
Defined
Undefined
Defined
Undefined
(Note 4)
Default
Defined
Undefined
(Note 3) t1 ≥ 0, t2 ≥ 0, tc: 10 µs(Min)
When VDD level is over 90 %, there may be cases where command is not received correctly in unstable VDD.
(Note 4) Display data are undefined. Regarding default value, refer to Reset Condition.
Figure 41. Power ON/OFF and INHb Control Sequence (Static)
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Datasheet
MAX 116 Segments (29SEG x 4COM)
Oscillation Stabilization Time
It must be noted that the oscillation of the internal oscillation circuit is unstable for a maximum of 100 μs (oscillation
stabilization time) after oscillation has started.
Internal oscillation
circuit
Oscillation
stabilization time
(100 µs Max.)
Oscillation stopped
Oscillation operation
(under normal conditions)
When control data OC = "0" and BU0 to BU2 = "000"
Figure 42. Oscillation Stabilization Time
Power-saving mode operation in external clock mode
After receiving [BU0,BU1,BU2] = [1,1,1], BU97601FV-M enters to power saving mode synchronized with frame then Segment
and Common ports output VSS level.
Therefore, in external clock mode, it is necessary to input the external clock based on each frame frequency setting after
sending [BU0,BU1,BU2] = [1,1,1].
For the required number of clock, refer to “6. FC0, FC1, FC2, FC3, FC4, FC5, and FC6: Common/Segment output waveform
frame frequency switching control data”.
For example, please input the external clock as below.
[FC0, FC1, FC2, FC3, FC4, FC5, FC6] = [0,0,0,0,0,0,0]: In case of fOSC/12000 setting, it needs over 12000 clk,
[FC0, FC1, FC2, FC3, FC4, FC5, FC6] = [0,1,0,1,0,1,0]: In case of fOSC/2308 setting, it needs over 2308 clk,
[FC0, FC1, FC2, FC3, FC4, FC5, FC6] = [1,1,1,1,1,1,1]: In case of fOSC/876 setting, it needs over 876 clk
Please refer to the timing chart below.
SCE
SCL
SDI
0
1
1
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
Device Code
8bits
D1
D2
OC
SC
BU0
Display Data/
Control Data
BU1
BU2
0
0
DD
2 bits
OSC
To input External clock at
least more than 1 frame
SEG
VSS
COM1
VSS
COM2
VSS
COM3
VSS
COM4
VSS
Output at Normal mode
Output at Power saving mode(VSS level)
Power saving
Last Display flame
of Sirial data
receiving
Figure 43. External Stop Timing(1/4-Duty)
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Datasheet
MAX 116 Segments (29SEG x 4COM)
Voltage Detection Type Reset Circuit (VDET)
The Voltage Detection Type Reset Circuit generates an output signal that resets the system when power is applied for the
first time and when the power supply voltage drops (that is, for example, the power supply voltage is less than or equal to the
power down detection voltage (VDET = 1.8 V Typ). To ensure that this reset function works properly, it is recommended that a
capacitor be connected to the power supply line so that both the power supply voltage (VDD) rise time when power is first
applied and the power supply voltage (VDD) fall time when the voltage drops are at least 1 ms.
To refrain from data transmission is strongly recommended while power supply is rising up or falling down to prevent from the
occurrence of disturbances on transmission and reception.
t1
VDD
t2
VDD (Min)
VDD (Min)
t3
VDD = 1.0 V
Figure 44. VDET Detection Timing
Power supply voltage VDD fall time: t1 > 1 ms
Power supply voltage VDD rise time: t2 > 1 ms
Internal reset power supply retain time: t3 > 1 ms
When it is difficult to keep above conditions, it is possibility to cause meaningless display due to no IC initialization.
Please execute the IC initialization as quickly as possible after Power-on to reduce such an affect.
See the IC initialization flow as below.
But since commands are not received when the power is OFF, the IC initialization flow is not the same function as POR.
Set [BU0,BU1,BU2] = [1,1,1](power-saving mode) and SC = 1(Display Off) as quickly as possible after Power-on.
BU97601FV-M can receive commands in 0ns after Power-on(VDD level is 90 %).
Please refer to the timing chart of “INHb Pin and Display Control”.
Reset Condition
When BU97601FV-M is initialized, the internal status after power supply has been reset as the following table.
Instruction
Key Scan mode
S5/P1/G1 to S20/P16/G16 pin
Inversion mode
LCD bias
LCD duty
DISPLAY frequency
Display clock mode
LCD display
Power mode
PWM/GPO output
External PWM
PWM frequency
PWM duty
Display Contrast setting
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At Reset Condition
[KM0,KM1,KM2] = [1,1,1]:Keyscan no use
[P0,P1,P2,P3,P4] = [0,0,0,0,0]:all segment output
FL = 0:Line Inversion
DR = 0:1/3 bias
[DT0,DT1] = [1,1]:1/4 duty
[FC0,FC1,FC2,FC3,FC4,FC5,FC6] = [0,0,0,0,0,0,0]:fOSC/12000
OC = 0:Internal oscillator
SC = 1:OFF
[BU0, BU1, BU2] = [1,1,1]:Power saving mode
PGx = 0:PWM output(x = 1 to 6)
[EP1,EP2,EP3,EP4,EP5,EP6,EP7,EP8,EP9,EP10,EP11,EP12,EP13,EP14,EP16]
= [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0]: External PWM OFF
[PF0,PF1,PF2,PF3] = [0,0,0,0]: fOSC/4096
[Wn0 to Wn8] = [0,0,0,0,0,0,0,0,0]:0/256)xTp
(n = 1 to 6,Tp = 1/fp)
[CT0,CT1,CT2,CT3] = [0,0,0,0]:VLCD Level is 1.00*VDD
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Datasheet
MAX 116 Segments (29SEG x 4COM)
Operational Notes
1.
Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power
supply pins.
2.
Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the
digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog
block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and
aging on the capacitance value when using electrolytic capacitors.
3.
Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.
4.
Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5.
Thermal Consideration
Should by any chance the power dissipation rating be exceeded the rise in temperature of the chip may result in
deterioration of the properties of the chip. The absolute maximum rating of the Pd stated in this specification is when
the IC is mounted on a 70mm x 70mm x 1.6mm glass epoxy board. In case of exceeding this absolute maximum
rating, increase the board size and copper area to prevent exceeding the Pd rating.
6.
Recommended Operating Conditions
These conditions represent a range within which the expected characteristics of the IC can be approximately
obtained. The electrical characteristics are guaranteed under the conditions of each parameter.
7.
Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may
flow instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power
supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring,
and routing of connections.
8.
Operation Under Strong Electromagnetic Field
Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction.
9.
Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may
subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply
should always be turned off completely before connecting or removing it from the test setup during the inspection
process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during
transport and storage.
10. Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment)
and unintentional solder bridge deposited in between pins during assembly to name a few.
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MAX 116 Segments (29SEG x 4COM)
Datasheet
Operational Notes – continued
11. Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small
charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and
cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the
power supply or ground line.
12. Regarding the Input Pin of the IC
In the construction of this IC, P-N junctions are inevitably formed creating parasitic diodes or transistors. The
operation of these parasitic elements can result in mutual interference among circuits, operational faults, or physical
damage. Therefore, conditions which cause these parasitic elements to operate, such as applying a voltage to an
input pin lower than the ground voltage should be avoided. Furthermore, do not apply a voltage to the input pins
when no power supply voltage is applied to the IC. Even if the power supply voltage is applied, make sure that the
input pins have voltages within the values specified in the electrical characteristics of this IC.
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Datasheet
MAX 116 Segments (29SEG x 4COM)
Ordering Information
B
U
9
7
6
0
1
Part Number
F
V
Package
FV : SSOP-B40
-
ME 2
Product Rank
M: for Automotive
Packaging Specification
E2: Embossed tape and reel
(SSOP-B40)
Marking Diagram
SSOP-B40 (TOP VIEW)
Part Number Marking
BU97601FV
LOT Number
1PIN MARK
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MAX 116 Segments (29SEG x 4COM)
Datasheet
Physical Dimension, Tape and Reel Information
Package Name
SSOP-B40
(Max 13.95 (include. BURR)
(UNIT ; mm)
PKG : SSOP-B40
Drawing No. EX157-5001
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Datasheet
Version / Revision History
Version
001
002
003
date
description
13. Sep. 2016 New Release
Page.4 Delete temperature condition in Absolute Maximum Rating
Page.6 Modify Figure Name.
Page.8 Add Pin Description Note
Page.11,13,15,17and 23 Add Description
Page.27 Correction of errors of Pin stats table.
01. Oct. 2019
Page.54 Add INHb Pin and Display Control description
Page.58 Add Voltage Detection Type Reset Circuit (VDET) additional explanation.
Page.60 Delete 13. Data transmission in Operational Notes (Move to Voltage Detection Type
Reset Circuit (VDET))
Minor correction to have more conformity between Japanese and English version.
05. Jan. 2021 Page.26 Modify The relationship of LCD display contrast setting and VLCD voltage.
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Notice
Precaution on using ROHM Products
1.
If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment (Note 1),
aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,
bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales
representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any
ROHM’s Products for Specific Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅣ
CLASSⅢ
2.
ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3.
Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below.
Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the
use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our
Products under any special or extraordinary environments or conditions (as exemplified below), your independent
verification and confirmation of product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used.
However, recommend sufficiently about the residue.); or Washing our Products by using water or water-soluble
cleaning agents for cleaning residue after soldering
[h] Use of the Products in places subject to dew condensation
4.
The Products are not subject to radiation-proof design.
5.
Please verify and confirm characteristics of the final or mounted products in using the Products.
6.
In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7.
De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in
the range that does not exceed the maximum junction temperature.
8.
Confirm that operation temperature is within the specified range described in the product specification.
9.
ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1.
When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2.
In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PAA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.004
Precautions Regarding Application Examples and External Circuits
1.
If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2.
You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1.
Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl 2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2.
Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3.
Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4.
Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
trade act, please consult with ROHM in case of export.
Precaution Regarding Intellectual Property Rights
1.
All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data.
2.
ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the
Products with other articles such as components, circuits, systems or external equipment (including software).
3.
No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM
will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to
manufacture or sell products containing the Products, subject to the terms and conditions herein.
Other Precaution
1.
This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2.
The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3.
In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4.
The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice-PAA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.004
Datasheet
General Precaution
1. Before you use our Products, you are requested to carefully read this document and fully understand its contents.
ROHM shall not be in any way responsible or liable for failure, malfunction or accident arising from the use of any
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this document is current as of the issuing date and subject to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the latest information with a ROHM sales
representative.
3.
The information contained in this document is provided on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate and/or error-free. ROHM shall not be in any way responsible or
liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccuracy or errors of or
concerning such information.
Notice – WE
© 2015 ROHM Co., Ltd. All rights reserved.
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