Datasheet
Low Duty LCD Segment Driver
BU9795BKV
MAX 140 Segments (SEG35×COM4)
Key Specifications
General Description
■
■
■
■
■
■
BU9795BKV is a 1/4 Duty General-purpose LCD driver
that can be used for consumer / battery operated
products.BU9795KV can drive up to 140 LCD Segments.
It has integrated display RAM for reducing CPU load.
Also, it is designed with low power consumption and no
external component needed.
Supply Voltage Range:
+2.5V to +5.5V
Operating Temperature Range:
-40°C to +85°C
Max Segments:
140 Segments
Display Duty:
1/4
Bias:
1/2, 1/3 selectable
Interface:
3wire serial interface
Features
Integrated RAM for Display Data (DDRAM) :
35 × 4bit (Max 140 Segments)
LCD Drive Output :
4 Common output, Max 35 Segment output
Integrated Buffer AMP for LCD Driving
Integrated Oscillator Circuit
No external Components
Low Power Consumption Design
Package
W (Typ) x D (Typ) x H (Max)
Applications
etc.
VQFP48C
9.00mm x 9.00mm x 1.60mm
Metering
Home Automation Goods
White Goods
Small Appliances
Healthcare Products
Battery Operated Products
Typical Application Circuit
VDD
(Note 1)
COM0
COM1
COM2
COM3
VDD
VLCD
INHb
CSB
SD
SCL
Segment
LCD
SEG0
SEG1
………
Controller
OSCIN
TEST
VSS
・・・・・・・
………
C ≥ 0.1µF
・・・・・・・
SEG34
(Note 1) Insert Capacitors between VDD and VSS
Internal Oscillator Circuit Mode
Figure 1. Typical Application Circuit
○Product structure：Silicon monolithic integrated circuit
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BU9795BKV
MAX 140 Segments (SEG35×COM4)
Segment
driver
SEG25
SEG24
SEG27
SEG26
SEG29
SEG28
SEG31
SEG30
25
Common
driver
SEG33
COM0
LCD voltage generator
36
VDD
SEG32
SEG0 … SEG34
COM0…… COM3
SEG34
Block Diagrams / Pin Configurations / Pin Description
37
COM1
24
SEG23
LCD BIAS
COM2
SEG22
SELECTOR
COM3
SEG21
VLCD
SEG20
VDD
SEG19
VSS
SEG18
OSCIN
SEG17
CSB
SEG16
SCL
SEG15
SD
SEG14
TEST
SEG13
＋
－
Common
counter
＋
－
Blink timing
generator
DDRAM
VLCD
INHb
Command
register
OSCIN
OSCILLATOR
Power On Reset
Command
Data Decoder
INHb
Serial inter face
SEG12
13
48
12
1
IF FILTER
SD
Figure 2. Block Diagram
Pin Name
Pin No.
I/O
INHb
48
I
TEST
47
I
OSCIN
43
I
SD
SCL
CSB
VSS
VDD
VLCD
SEG0 to 34
COM0 to 3
46
45
44
42
41
40
1 to 35
36 to 39
I
I
I
I
O
O
SEG8
SEG9
SEG6
SEG7
SEG4
SEG5
SEG2
SEG3
SCL
SEG10
CSB
SEG11
TEST
SEG1
SEG0
VSS
Figure 3. Pin Configuration (TOP VIEW)
Table 1 Pin Description
Function
Input pin for turn off display
H : turn on display
L : turn off display
POR enable setting
VDD: POR disenable (Note)
VSS: POR enable
Input pin for external clock
External clock and Internal clock can be changed by
command.
Must be connected to VSS when using internal
oscillation circuit.
Serial data input
Serial data transfer clock
Chip select : ”L” active
Ground
Power supply
Power supply for LCD driving
Segment output for LCD driving
Common output for LCD driving
Handling when unused
VDD
VSS
VSS
OPEN
OPEN
(Note) This function is guaranteed by design, not tested in production process.
Software Reset is necessary to initialize IC in case of TEST=VDD.
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BU9795BKV
MAX 140 Segments (SEG35×COM4)
Absolute Maximum Ratings (VSS=0V)
Symbol
Ratings
Unit
Power Supply Voltage1
VDD
-0.5 to +7.0
V
Power Supply
Power Supply Voltage2
VLCD
-0.5 to VDD
V
LCD Drive Voltage
Parameter
(Note 1)
Power Dissipation
Pd
0.60
Input Voltage Range
VIN
-0.5 to VDD+0.5
V
Operating Temperature Range
Topr
-40 to +85
°C
Storage Temperature Range
Tstg
-55 to +125
°C
Remark
W
(Note 1) Derate by 6.0mW/°C when exceeding above Ta=25°C (when mounted in ROHM’s standard board).
Caution: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated over the
absolute maximum ratings.
Caution2: Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in deterioration of the
properties of the chip. In case of exceeding this absolute maximum rating, design a PCB boards with power dissipation taken into consideration by increasing
board size and copper area so as not to exceed the maximum junction temperature rating.
Recommended Operating Conditions (Ta=-40°C to +85°C, VSS=0V)
Symbol
Parameter
Ratings
Min
Typ
Max
Unit
Remark
Power Supply Voltage1
VDD
2.5
-
5.5
V
Power Supply
Power Supply Voltage2
VLCD
0
-
VDD-2.4
V
LCD Drive Voltage, VDD-VLCD
2.4V
Electrical Characteristics
DC Characteristics (VDD=2.5V to 5.5V, VSS=0V, Ta=-40°C to +85°C, unless otherwise specified)
Limit
Parameter
Symbol
Unit
Min
Typ
Max
Conditions
“H” Level Input Voltage
VIH
0.7VDD
-
VDD
V
SD, SCL, CSB, INHb, OSCIN
“L” Level Input Voltage
VIL
VSS
-
0.3VDD
V
SD, SCL, CSB, INHb, OSCIN
“H” Level Input Current
IIH
-
-
1
µA
“L” Level Input Current
IIL
-1
-
-
µA
SEG
RON
-
-
kΩ
COM
RON
-
3.5
3.5
-
kΩ
VLCD
0
-
VDD -2.4
V
VDD-VLCD 2.4V
Standby Current
Ist
-
-
5
µA
Display off, Oscillator off
Power Consumption 1
IDD1
-
12.5
30
µA
VDD=3.3V, VLCD=0V, Ta=25°C,
Power save mode1, FR=70Hz,
1/3 bias, Frame inverse
Power Consumption 2
IDD2
-
20
40
µA
VDD=3.3V, VLCD=0V, Ta=25°C,
Normal mode, FR=80Hz,
1/3 bias, Line inverse
LCD Driver
ON-Resistance
VLCD Supply Voltage
SD, SCL, CSB, INHb, OSCIN(Note 2),
TEST
SD, SCL, CSB, INHb, OSCIN(Note 2),
TEST
Iload=±10µA
(Note 2) For External clock mode only
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Electrical Characteristics – continued
Oscillation Characteristics (VDD=2.5V to 5.5V, VSS=0V, Ta=-40°C to +85°C, unless otherwise specified)
Limits
Parameter
Symbol
Unit
Conditions
Min
Typ
Max
FR = 80Hz setting,
Frame Frequency1
fCLK1
56
80
104
Hz
VDD=2.5V to 5.5V,
Ta=-40°C to +85°C
FR = 80Hz setting, VDD=3.3V,
Frame Frequency2
fCLK2
70
80
90
Hz
Ta=25°C
FR = 80Hz setting, VDD=5.0V,
Frame Frequency3
fCLK3
77.5
87.5
97.5
Hz
Ta=25°C
FR = 80Hz setting, VDD=5.0V,
Frame Frequency4
fCLK4
67.5
87.5
108
Hz
Ta=-40°C to +85°C
External Clock Rise Time
tr
0.3
µs
External Clock Fall Time
tf
-
-
0.3
µs
External Frequency
fEXCLK
15
-
300
kHz
External Clock Duty
tDTY
30
50
70
%
External clock mode (OSCIN) (Note)
(Note)
DISCTL 320Hz setting: Frame frequency [Hz] = External clock [Hz] / 128
DISCTL 284Hz setting: Frame frequency [Hz] = External clock [Hz] / 144
DISCTL 213Hz setting: Frame frequency [Hz] = External clock [Hz] / 192
DISCTL 160Hz setting: Frame frequency [Hz] = External clock [Hz] / 256
DISCTL 80Hz setting: Frame frequency [Hz] = External clock [Hz] / 512
DISCTL 71Hz setting: Frame frequency [Hz] = External clock [Hz] / 576
DISCTL 64Hz setting: Frame frequency [Hz] = External clock [Hz] / 648
DISCTL 53Hz setting: Frame frequency [Hz] = External clock [Hz] / 768
【Reference Data】
110
VDD = 6.0V
Frame Frequency [Hz]
100
VDD = 5.0V
90
VDD = 3.3V
VDD = 2.7V
80
70
60
50
-40 -20
0
20
40
60
80 100
Temperature [°C]
Figure 4. Frame Frequency Typical Temperature Characteristics
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Electrical Characteristics – continued
MPU Interface Characteristics (VDD=2.5V to 5.5V, VSS=0V, Ta=-40°C to +85°C, unless otherwise specified)
Limit
Parameter
Unit
Conditions
Symbol
Min
Typ
Max
Input Rise Time
tr
-
-
80
ns
Input Fall Time
tf
-
-
80
ns
SCL Cycle Time
tSCYC
400
-
-
ns
“H” SCL Pulse Width
tSHW
100
ns
tSLW
100
-
-
“L” SCL Pulse Width
-
ns
SD Setup Time
tSDS
20
-
-
ns
SD Hold Time
tSDH
50
-
-
ns
CSB Setup Time
tCSS
50
-
-
ns
CSB Hold Time
tCSH
50
-
-
ns
“H” CSB Pulse Width
tCHW
50
-
-
ns
Figure 5. Interface Timing
I/O Equivalent Circuit
VDD
VLCD
VSS
CSB, SD, SCL
TEST
VSS
OSCIN
VSS
VDD
VSS
VDD
INHb
VSS
VSS
VDD
SEG/COM
VSS
Figure 6. I/O Equivalent Circuit
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MAX 140 Segments (SEG35×COM4)
Application Example
VDD
VDD
VLCD
COM0
COM1
COM2
COM3
INHb
CSB
SD
SCL
Controller
Segment
LCD
SEG0
SEG1
・
・
・
OSCIN
TEST
VSS
・
・
・
SEG34
External clock mode
VDD
VDD
VLCD
Controller
COM0
COM1
COM2
COM3
INHb
CSB
SD
SCL
SEG0
SEG1
・
・
・
・
SEG34
OSCIN
TEST
VSS
Segment
LCD
・
・
・
Internal Clock Mode
Figure 7. Example of Application Circuit
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MAX 140 Segments (SEG35×COM4)
Function Descriptions
1.Command and Data Transfer Method
1.1 3-SPI (3wire Serial Interface)
BU9795BKV is controlled by 3-wire signal (CSB, SCL, and SD).
First, Interface counter is initialized with CSB=“H", and CSB=“L” makes SD and SCL input enable.
The protocol of 3-SPI transfer is as follows.
Each command starts with Command or Data judgment bit (D/C) as MSB data, followed by D6 to D0 during
CSB =“L”.
(Internal data is latched at the rising edge of SCL, it is converted to 8bits parallel data at the falling edge of 8th CLK.)
Command/Data
Command
CSB
SCL
SD
D/C D6
D5
D4
D/C = “H” : Command
D3
D2
D1
D0
D/C
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D/C = “L” : Data
Figure 8. 3-SPI Command/Data Transfer Format
1.2 Command Transfer Method
After CSB=“H”→”L”, 1st byte is always a command input.
MSB of the command input data will be judged that the next byte data, it is a command or Display Data (This bit is called
“command or data judgment bit”).
When set “command or data judge bit”=“1”, next byte will be (continuously) command.
When set “command or data judge bit”=“0”, next byte data is Display Data.
1 Command
1 Command
…
Display Data
0 Command
1 Command
Once it becomes Display Data transfer condition, it will not be back to command input condition even if D/C=1.
So if you want to send command data again, set CSB=“L”→”H”.
(CSB “L”→”H” will cancel data transfer condition.)
Command transfer is done by 8bits unit, so if CSB=“L”→”H” with less than 8bits data transfer, command will be cancelled.
It will be able to transfer command with CSB=“L” again.
In Case Of Command Transfer
Command
Command
CSB
1
SCL
SD
STATUS
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
DISCTL Command Transfer
Command Cancelled (Less Than 8bits)
DISPON Command Transfer
Figure 9. Command Transfer Format
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1. Command and Data Transfer Method – continued
1.3 Write Display Data and transfer method
BU9795BKV has Display Data RAM (DDRAM) of 35×4=140bit.
The relationship between data input and display data, DDRAM data and address are as follows.
8bit data will be stored in DDRAM. The address to be written is the address specified by ADSET command, and the
address is automatically incremented in every 4bit data.
Data can be continuously written in DDRAM by transmitting Data continuously.
(When RAM data is written successively after writing RAM data to 22h (SEG34), the address is returned to 00h (SEG0) by
the auto-increment function. (Refer to ADSET command for the Address set order.)
DDRAM address
00h 01h 02h 03h 04h 05h 06h 07h ・・・・・・ 1Eh 1Fh 20h 21h 22h
BIT
0
a
e
i
m
q
u
COM0
1
b
f
j
n
r
v
COM1
2
c
g
k
o
s
x
COM2
3
d
h
l
p
t
y
COM3
SEG SEG SEG SEG SEG SEG SEG SEG
SEG SEG SEG SEG SEG
・・・・・・
0
1
2
3
4
5
6
7
30 31 32 33 34
As data transfer to DDRAM happens every 4bit data, it will be cancelled if it changes CSB=“L”→”H” before
4bits data transfer. (Command transfer is done every 8bits)
Command
RAM Write
CSB
SCL
SD
Address set
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Internal signal
RAM Write
Address00h
Address01h
Address02h
Write data will be canceled ,
when CSB='H' without
4bit data transfer.
RAM Write (Every 4bit data)
Command
RAM Write
CSB
SCL
SD
Address set
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Internal signal
RAM Write
Address00h
Address21h
Address22h
Address00h
Return to address "0"
by automatically increment.
Figure 10. Data Transfer Format
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MAX 140 Segments (SEG35×COM4)
Function Descriptions – continued
2. OSCILLATOR
There are two kinds of clock for logic and analog circuit; from internal oscillator circuit or external clock input. If internal
oscillator circuit will be used, OSCIN must be connected to VSS.
When you use external clock, execute ICSET command and connect OSCIN to external clock.
OSCIN
OSCIN
BU9795BKV
Clock Input
BU9795BKV
VSS
Figure 11. Internal Oscillator Circuit Mode
Figure 12. External clock mode
3. LCD Driver Bias Circuit
This LSI generates LCD driving voltage with on-chip Buffer AMP.
And it can drive LCD at low power consumption.
1/3 and 1/2Bias can be set in MODESET command.
Line and frame inversion can be set in DISCTL command.
Refer to “LCD Driving Waveform” about each LCD driving waveform.
4. Blink Timing Generator
BU9795BKV is equipped with Blinking function.
Blink mode is asserted by BLKCTL command.
The Blink frequency varies depending on fCLK characteristics at Internal clock mode.
Refer to Oscillation Characteristics for fCLK.
5.Reset (Initial) Condition
Initial condition after executing Software Reset is as follows.
(1)Display is OFF.
(2)DDRAM address is initialized (DDRAM Data is not initialized).
Refer to Command Description about initialize value of register.
Command / Function List
Table of Functions Description
No.
Command
Function
1
Mode Set (MODESET)
Set LCD Drive Mode
2
Address Set (ADSET)
Set LCD Display Mode 1
3
Display Control (DISCTL)
Set LCD Display Mode 2
4
Set IC Operation (ICSET)
Set IC Operation
5
Blink Control (BLKCTL)
Set Blink Mode
6
All Pixel Control (APCTL)
Set All Pixels ON/OFF Display
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Detailed Command Description
D7 (MSB) is bit for command or data judgment.
Refer to Command and data transfer method.
C : 0 : Next byte is RAM Write data.
1 : Next byte is command.
1.Mode Set (MODE SET)
MSB
D7
C
D6
1
D5
0
LSB
D4
*
D3
P3
D2
P2
D1
*
D0
*
(* : Don’t care)
Set Display on and off
Setting
Display off (DISPOFF)
P3
Reset initial condition
0
○
Display on (DISPON)
1
Display off : Regardless of DDRAM data, all Segment and Common output will be stopped after 1 frame of
data write. Display off mode will be finished by Display on.
Display on : Segment and Common output will be active and start to read the Display Data from DDRAM.
(Note) When Display on/off is controlled by INHb terminal, it is not synchronized with display frame period.
Set bias level
Setting
1/3 Bias
P2
Reset initial condition
0
○
1/2 Bias
1
Refer to LCD driving waveform(Example of SEG and COM output waveform by Bias level setting.).
2.Address Set (ADSET)
MSB
D7
D6
D5
C
0
0
D4
P4
D3
P3
D2
P2
D1
P1
LSB
D0
P0
Address data is specified in P[4 : 0] and P2 (ICSET command) as follows.
MSB
LSB
Internal register
Address [5]
Address [4]
・・・
Address [0]
Bit of each command
ICSET [P2]
ADSET [P4]
・・・
ADSET [P0]
The address is 00h in reset condition. The valid address is 00h to 22h.
Another address is invalid, (otherwise address will be set to 00h.)
The ICSET command is only to define the register setting (“0” or “1”) of MSB of the address and does not set the
address. Address counter will be set only when ADSET command is executed. When ICSET[P2] is set, the
previous state is maintained until ICSET command is executed again or when Software Reset is executed.
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Detailed Command Description – continued
(1)
CSB
COMMAND
ADSET”00010”
RAM Write
RAM Write
・・・・・
RAM Write
RAM Write
DISCTL
RAM Write
RAM Write
・・・
RAM Write
Internal Signal
ICSET P2
Internal Signal
Address
000010
000011
・・・
000100
100010
000000
000001
000010
Set address by ADSET command.
P2(ICSET command) is referd to set address.
Address will be set "000010", because P2(ICSET)="0".
000011
000100
000101
Because of no setting ADSET command,
it will be kept the previous address.
It will be start to write RAM data from maintained address.
When RAM data is continuously trasmitted,
address will be increment automaticaly.
When write at 22h address, address will be
returen to 00h automaticaly.
The following address that write at the end is maintained.
(2)
CSB
ADSET”11111”
COMMAND
RAM Write
RAM Write
・・・・・
RAM Write
ADSET”00000”
RAM Write
RAM Write
RAM Write
・・・
RAM Write
Internal Signal
ICSET P2
Internal Signal
Address
011111
100000
100001
100010
000000
000001
000010
000011
Set address by ADSET command.
P2(ICSET command) is referd to set address.
Address will be set "011111", because P2(ICSET)="0".
000000
000001
000010
000011
New address will be set by ADSET command.
When RAM data is continuously trasmitted,
address will be increment automaticaly.
When write at 22h address, address will be
returen to 00h automaticaly.
The following address that write at the end is maintained.
(3)
CSB
ICSET P2=1
COMMAND
ADSET”00000”
RAM Write
・・・・・
RAM Write
ADSET”00000”
RAM Write
RAM Write
RAM Write
・・・
RAM Write
Internal Signal
ICSET P2
Internal Signal
Address
100000
100001
100010
000000
000001
000010
000011
Set address by ADSET command.
P2(ICSET command) is referd to set address.
Address will be set "100000", because P2(ICSET)="1".
It will be set P2="1" by ICSET command.
(ICSET command can not set addres)
100000
100001
100010
000000
New address will be set by ADSET command.
Address will be set "100000", because P2(ICSET)="1".
(P2(ICSET) will maintain the previous address
until ICSET command input.
When RAM data is continuously trasmitted,
address will be increment automaticaly.
When write at 22h address, address will be
returen to 00h automaticaly.
The following address that write at the end is maintained.
(4)
CSB
COMMAND
ICSET P2=1
ADSET”00000”
RAM Write
・・・・・
RAM Write
RAM Write
ICSET P2=0
RAM Write
RAM Write
・・・
RAM Write
Internal Signal
ICSET P2
Internal Signal
Address
100000
100001
100010
000000
・・・・・
100000
100001
Set address by ADSET command.
P2(ICSET command) is referd to set address.
100010
000000
000001
It is written to RAM continuously
from the previous address.
The address maintain the previous address
because it doesn't input the ADSET command
though ICSET P2="0" setting.
When RAM data is continuously trasmitted,
address will be increment automaticaly.
When write at 22h address, address will be
returen to 00h automaticaly.
The following address that write at the end is maintained.
Figure 13. Address Set Sequence
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BU9795BKV
MAX 140 Segments (SEG35×COM4)
Detailed Command Description – continued
3.Display Control (DISCTL)
MSB
D7
D6
D5
C
0
1
D4
P4
LSB
D0
P0
D2
P2
D1
P1
P4
P3
FRSEL(Note 2)
Reset initial condition
80Hz
0
0
0
○
71Hz
0
1
0
-
64Hz
1
0
0
-
Set Frame Frequency
Setting(Note 1)
D3
P3
53Hz
1
1
0
-
160Hz
0
0
1
-
213Hz
1
1
1
-
284Hz
0
1
1
-
320Hz
1
0
1
-
(Note 1) The frame frequency varies according to the characteristics of fCLK when internal oscillation circuit is used.
(Refer to Oscillation Characteristics for fCLK properties).
(Note 2) Refer to BLKCTL for FRSEL
Set LCD Drive Waveform
Setting
P2
Reset initial condition
Line Inversion
0
○
Frame Inversion
1
Power consumption is reduced in the following order:
Line inversion > Frame inversion
Typically, when driving large capacitance LCD, Line inversion will increase the influence of crosstalk.
Regarding driving waveform, refer to LCD Driving Waveform.
Set Power Save Mode (low current consumption mode)
Setting
P1
P0
Reset initial condition
Power Save Mode 1
0
0
Power Save Mode 2
0
1
-
Normal Mode
1
0
○
-
High Power Mode
1
1
Power consumption is increased in the following order:
Power save mode 1 < Power save mode 2 < Normal mode < High power mode
Use VDD- VLCD ≥ 3.0V in High power mode condition.
(Reference Current Consumption data)
Setting
Reset initial condition
Power Save Mode 1
×0.5
Power Save Mode 2
×0.67
Normal Mode
×1.0
High Power Mode
×1.8
The data above is for reference only. Actual consumption depends on Panel load.
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BU9795BKV
MAX 140 Segments (SEG35×COM4)
Detailed Command Description – continued
4.Set IC Operation (ICSET)
MSB
D7
D6
D5
C
1
1
D4
0
D3
1
D2
P2
LSB
D0
P0
D1
P1
P2 : Set MSB data of DDRAM address.
Execute ADSET command for it to take effect on an address.
Refer to “ADSET” command for details.
Setting
P2
Reset initial condition
Address MSB”0”
0
○
Address MSB”1”
1
-
Set Software Reset Condition
Setting
P1
No Operation
0
Software Reset
1
When “Software Reset” is executed, BU9795BKV will be reset to initial condition.
If software reset is executed, the value of P2 and P0 will be ignored and they will be reset to initial condition.
(Refer to “Reset initial condition”)
Switch between Internal oscillator operating mode and external clock mode.
Setting
P0
Reset initial condition
Internal oscillator
0
○
operating mode
External Clock
1
Input mode
Internal oscillator operating mode: OSCIN must be connected to VSS level.
External Clock mode: Input external clock from OSCIN terminal.
< Frame frequency Calculation at External clock mode >
DISCTL 320Hz select : Frame frequency [Hz] = External clock[Hz] / 128
DISCTL 284Hz select : Frame frequency [Hz] = External clock[Hz] / 144
DISCTL 213Hz select : Frame frequency [Hz] = External clock[Hz] / 192
DISCTL 160Hz select : Frame frequency [Hz] = External clock[Hz] / 256
DISCTL 80Hz select : Frame frequency [Hz] = External clock[Hz] / 512
DISCTL 71Hz select : Frame frequency [Hz] = External clock[Hz] / 576
DISCTL 64Hz select : Frame frequency [Hz] = External clock[Hz] / 648
DISCTL 53Hz select : Frame frequency [Hz] = External clock[Hz] / 768
Command
OSCIN_EN
(Internal signal)
ICSET
Internal clock mode
External clock mode
Internal oscillation
(Internal signal)
External clock
(OSCIN)
Figure 14. OSC MODE Switching Timing
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BU9795BKV
MAX 140 Segments (SEG35×COM4)
Detailed Command Description – continued
5.Blink Control (BLKCTL)
MSB
D7
D6
D5
C
1
1
D4
1
Set Blink Condition
Setting
D3
0
D2
P2
LSB
D0
P0
D1
P1
P1
P0
Reset initial condition
OFF
0
0
○
0.5 (Hz)
0
1
-
1 (Hz)
1
0
-
2 (Hz)
1
1
The Blink frequency varies depending on fCLK characteristics at Internal oscillator operating mode.
Refer to Oscillation Characteristics for fCLK.
Set Frame Frequency Setting(FRSEL)
Setting
P2
Reset initial condition
Normal
0
○
200Hz mode
1
-
6.All Pixel Control (APCTL)
MSB
D7
D6
D5
C
1
1
D4
1
D3
1
All Display Set ON/OFF
Setting
P1
D2
1
LSB
D0
P0
D1
P1
Reset initial condition
Normal
0
○
All Pixel on
1
-
Setting
P0
Reset initial condition
Normal
0
○
All Pixel off
1
All pixels on: All pixels are on regardless of DDRAM data.
All pixels off: All pixels are off regardless of DDRAM data.
This command is valid in Display on status. The data of DDRAM is not changed by this command.
If set both P1 and P0 =”1”, APOFF will be selected.
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BU9795BKV
MAX 140 Segments (SEG35×COM4)
LCD Driving Waveform
(1/3bias)
Line Inversion
Frame Inversion
SEGn SEGn+1 SEGn+2 SEGn+3
SEGn SEGn+1 SEGn+2 SEGn+3
COM0
stateA
COM0
stateA
COM1
stateB
COM1
stateB
COM2
COM2
COM3
COM3
1frame
VDD
1frame
VDD
COM0
COM0
VLCD
VLCD
VDD
VDD
COM1
COM1
VLCD
VLCD
VDD
VDD
COM2
COM2
VLCD
VDD
VLCD
VDD
COM3
COM3
VLCD
VDD
VLCD
VDD
SEGn
SEGn
VLCD
VDD
VLCD
VDD
SEGn+1
SEGn+1
VLCD
VDD
VLCD
VDD
SEGn+2
SEGn+2
VLCD
VDD
VLCD
VDD
SEGn+3
SEGn+3
VLCD
VLCD
stateA
stateA
(COM0 to SEGn)
(COM0 to SEGn)
stateB
stateB
(COM1 to SEGn)
(COM1 to SEGn)
Figure 15. Line Inversion Waveform (1/3bias)
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Figure 16. Frame Inversion Waveform (1/3bias)
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BU9795BKV
MAX 140 Segments (SEG35×COM4)
LCD Driving Waveform – continued
(1/2bias)
Line Inversion
Frame Inversion
SEGn SEGn+1 SEGn+2 SEGn+3
SEGn SEGn+1 SEGn+2 SEGn+3
COM0
stateA
COM0
stateA
COM1
stateB
COM1
stateB
COM2
COM2
COM3
COM3
VDD
1frame
1frame
VDD
COM0
COM0
VLCD
VLCD
VDD
VDD
COM1
COM1
VLCD
VLCD
VDD
VDD
COM2
COM2
VLCD
VLCD
VDD
VDD
COM3
COM3
VLCD
VLCD
VDD
VDD
SEGn
SEGn
VLCD
VLCD
VDD
VDD
SEGn+1
SEGn+1
VLCD
VLCD
VDD
VDD
SEGn+2
SEGn+2
VLCD
VLCD
VDD
VDD
SEGn+3
SEGn+3
VLCD
VLCD
stateA
stateA
(COM0 to SEGn)
(COM0 to SEGn)
stateB
stateB
(COM1 to SEGn)
(COM1 to SEGn)
Figure 17. Line Inversion Waveform (1/2bias)
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Figure 18. Frame Inversion Waveform (1/2bias)
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01.Apr.2020 Rev.003
BU9795BKV
MAX 140 Segments (SEG35×COM4)
Example of Display Data
If COM and SEG line pattern is shown as in Figure 19 and Figure 20, and DDRAM data is shown as in Table 2, display
pattern will be shown as in Figure 21.
Figure 19. Example COM Line Pattern
SEG1 SEG3
SEG2
SEG5 SEG7
SEG4 SEG6 SEG8
SEG9
SEG10
Figure 20. Example SEG Line Pattern
Figure 21. Example Display Pattern
S
E
G
0
S
E
G
1
S
E
G
2
S
E
G
3
S
E
G
4
S
E
G
5
Table 2. DDRAM Data Map
S
S
S
S
S
S
E
E
E
E
E
E
G G G G G G
6
7
8
9 10 11
S
E
G
12
S
E
G
13
S
E
G
14
S
E
G
15
S
E
G
16
S
E
G
17
S
E
G
18
S
E
G
19
COM0
D0
0
1
1
0
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
COM1
D1
0
0
1
1
1
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
COM2
D2
0
0
0
1
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
0
COM3
D3
0
0
1
1
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
Address
00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h
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BU9795BKV
MAX 140 Segments (SEG35×COM4)
Initialize Sequence
Follow sequence below after Power ON to set BU9795BKV to initial condition.
Power ON
↓
CSB ”H” …I/F initialize condition
↓
CSB ”L” …I/F Data transfer start
↓
Execute Software Reset by sending ICSET command (Refer to “ICSET” command)
* Each register value, DDRAM address and DDRAM data are random after Power ON until initialize sequence is executed.
Start Sequence
Start Sequence Example 1
No.
Input
1
D7
D6
D5
D4
D3
D2
D1
D0
Power ON
Descriptions
VDD=0V to 5V (Tr=0.1ms)
↓
2
Wait 100µs
Initialize IC
↓
3
CSB ”H”
4
CSB ”L”
5
ICSET
Initialize I/F data
↓
I/F Data transfer start
↓
1
1
1
0
1
*
1
0
Software Reset
1
1
1
1
0
*
0
1
1
0
1
0
0
1
1
0
1
1
1
0
1
0
0
0
RAM Address MSB set
0
0
0
0
0
0
0
0
RAM Address set
Display Data
*
*
*
*
*
*
*
*
Address
00h to 01h
Display Data
*
*
*
*
*
*
*
*
Address
02h to 03h
*
*
*
*
*
*
*
*
Address
↓
6
BLKCTL
↓
7
DISCTL
↓
8
ICSET
9
ADSET
↓
↓
10
…
…
Display Data
22h to 00h
↓
11
CSB ”H”
I/F Data transfer stop
↓
12
CSB ”L”
I/F Data transfer start
↓
13
MODESET
1
1
0
*
1
0
*
*
Display on
↓
14
(*: don’t care)
CSB ”H”
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I/F Data transfer stop
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BU9795BKV
MAX 140 Segments (SEG35×COM4)
Start Sequence – continued
Start Sequence Example 2
Initialize
Initialize Sequence
DISPON
DISPON Sequence
RAM Write
RAM Write Sequence
DISPOFF
DISPOFF Sequence
BU9795BKV is initialized with Initialize Sequence, starts to display with “DISPON Sequence”,
updates Display Data with “RAM Write Sequence” and stops the display with “DISPOFF sequence”.
If you want to resume to display, BU9795BKV will resume display with DISPON Sequence.
Initialize Sequence
Input
Power ON
Wait 100us
CSB ”H”
CSB ”L”
ICSET
MODESET
ADSET
Display Data
…
CSB ”H”
DATA
D7 D6 D5 D4 D3 D2 D1 D0
Description
IC initialized
I/F initialized
1
1
1
0
1
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
*
*
*
*
*
*
*
*
Software Reset
Display off
RAM Address set
Display Data
DISPON Sequence
Input
CSB ”L”
DISCTL
BLKCTL
APCTL
MODESET
CSB ”H”
DATA
D7 D6 D5 D4 D3 D2 D1 D0
1
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
0
0
0
Description
Display Control
BLKCTL
APCTL
Display on
RAM Write Sequence
Input
CSB ”L”
DISCTL
BLKCTL
APCTL
MODESET
ADSET
Display Data
…
DATA
D7 D6 D5 D4 D3 D2 D1 D0
1
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
*
*
*
*
*
*
*
*
Description
Display Control
BLKCTL
APCTL
Display on
RAM Address set
Display Data
CSB ”H”
DISPOFF Sequence
Input
CSB 'L'
MODESET
CSB 'H'
DATA
D7 D6 D5 D4 D3 D2 D1 D0
1
1
0
0
0
0
0
0
Description
Display off
Abnormal operation may occur in BU9795BKV due to the effect of noise or other external factor. To
avoid this phenomenon, it is highly recommended to input command according to sequence when the
operating of initialize, Display On/Off and the refresh of RAM Data.
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display ON/OFF and refresh of TSZ02201-0P4P0D301490-1-2
RAM data.
TSZ22111･15･001
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BU9795BKV
MAX 140 Segments (SEG35×COM4)
Cautions of “Power ON Condition”
Power supply sequence
Keep Power ON/OFF sequence as below waveform.
To prevent incorrect display, malfunction and abnormal current,
VDD must be turned on before VLCD in power up sequence.
VDD must be turned off after VLCD in power down sequence.
Satisfy VDD-2.4V ≥ VLCD, t1 > 0ns and t2 > 0ns.
To refrain from data transmission is strongly recommended while power supply is rising up or falling down to prevent from
the occurrence of disturbances on transmission and reception.
VDD Min
VDD Min
VDD
t1
VLCD
t2
10%
10%
Figure 22. Power Supply Sequence
BU9795BKV has “POR” (Power ON Reset) circuit and Software Reset function.
Keep the following recommended Power ON conditions in order to power up properly.
(1)Set power up conditions to meet the recommended tR, tF, tOFF, and VBOT specification below in order to ensure POR
operation.
Set pin TEST=”L” to enable POR circuit.
VDD
tF
tR
tOFF
Recommended condition of tR, tF, tOFF, VBOT (Ta=+25°C)
tR(Note)
tF(Note)
tOFF(Note)
VBOT(Note)
Less than
Max 5ms
Max 5ms Min 20ms
0.3V
VBOT
(Note) This function is guaranteed by design, not tested in production process.
Figure 23. Rising Waveform Diagram
(2)If it is difficult to meet the above condition, execute the following sequence after Power ON.
Note however that it cannot accept command while supply is unstable or below the minimum supply range.
Note also that software reset is not a complete alternative to POR function.
(a)CSB =“L”→”H” condition
VDD
CSB
Figure 24. CSB Timing
(b)Execute Software Reset in ICSET command after CSB to “L”.
(Refer to “ICSET” command)
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BU9795BKV
MAX 140 Segments (SEG35×COM4)
Display off Operation in External clock mode
After receiving MODESET(Display off), BU9795BKV enter to DISPOFF sequence synchronized with frame then
Segment and Common pins output VSS level after 1frame of OFF data write.
Therefore, in External clock mode, it is necessary to input the external clock based on each frame frequency setting
after sending MODESET(Display off).
For the required number of clock, refer to Power save mode FR of DISCTL.
Input the external clock as below.
DISCTL 320HZ setting(Frame frequency [Hz] = External clock [Hz] / 128), it needs over 256clk
DISCTL 284HZ setting(Frame frequency [Hz] = External clock [Hz] / 144) , it needs over 288clk
DISCTL 213HZ setting(Frame frequency [Hz] = External clock [Hz] / 192) , it needs over 384clk
DISCTL 160HZ setting(Frame frequency [Hz] = External clock [Hz] / 256) , it needs over 512clk
DISCTL 80HZ setting(Frame frequency [Hz] = External clock [Hz] / 512), it needs over 1024clk
DISCTL 71HZ setting(Frame frequency [Hz] = External clock [Hz] / 576) , it needs over 1152clk
DISCTL 64HZ setting(Frame frequency [Hz] = External clock [Hz] / 648) , it needs over 1296clk
DISCTL 53HZ setting(Frame frequency [Hz] = External clock [Hz] / 768) , it needs over 1536clk
Refer to the timing chart below.
Command
MODESET
OSCIN
To input External clock at
least 2 f rames or more
SEG
VSS
COM0
VSS
COM1
VSS
COM2
VSS
COM3
VSS
Display on
Display of f
Last Display f rame of
MODESET receiv ing
1 f rame of OFF
data write
Figure 25. External Clock Stop Timing
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BU9795BKV
MAX 140 Segments (SEG35×COM4)
Operational Notes
1. Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power
supply pins.
2. Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the
digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog
block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and
aging on the capacitance value when using electrolytic capacitors.
3. Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition
4. Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5. Recommended Operating Conditions
These conditions represent a range within which the expected characteristics of the IC can be approximately
obtained. The electrical characteristics are guaranteed under the conditions of each parameter.
6. Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may
flow instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power
supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring,
and routing of connections.
7. Operation Under Strong Electromagnetic Field
Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction.
8. Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may
subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply
should always be turned off completely before connecting or removing it from the test setup during the inspection
process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during
transport and storage.
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BU9795BKV
MAX 140 Segments (SEG35×COM4)
Operational Notes – continued
9. Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment)
and unintentional solder bridge deposited in between pins during assembly to name a few.
10.
Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small
charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and
cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the
power supply or ground line.
11.
Regarding the Input Pin of the IC
In the construction of this IC, P-N junctions are inevitably formed creating parasitic diodes or transistors. The
operation of these parasitic elements can result in mutual interference among circuits, operational faults, or physical
damage. Therefore, conditions which cause these parasitic elements to operate, such as applying a voltage to an
input pin lower than the ground voltage should be avoided. Furthermore, do not apply a voltage to the input pins
when no power supply voltage is applied to the IC. Even if the power supply voltage is applied, make sure that the
input pins have voltages within the values specified in the electrical characteristics of this IC.
12.
Ceramic Capacitor
When using a ceramic capacitor, determine a capacitance value considering the change of capacitance with
temperature and the decrease in nominal capacitance due to DC bias and others.
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BU9795BKV
MAX 140 Segments (SEG35×COM4)
Ordering Information
B
U
9
7
9
5
B
K
V
-
Package
KV : VQFP48C
Part Number
E2
Packaging Specification
E2: Embossed tape and reel
Lineup
Package
VQFP48C
Orderable Part Number
Reel of 1500
BU9795BKV-E2
Marking Diagram
VQFP48C (TOP VIEW)
Part Number Marking
BU9795B
LOT Number
Pin 1 Mark
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BU9795BKV
MAX 140 Segments (SEG35×COM4)
Physical Dimension and Packing Information
Package Name
VQFP48C
1PIN MARK
www.rohm.com
© 2016 ROHM Co., Ltd. All rights reserved.
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BU9795BKV
MAX 140 Segments (SEG35×COM4)
Revision History
Date
25. Apr. 2016
Revision
001
10. Nov. 2017
002
01. Apr. 2020
003
Changes
New Release
Add BU9795BKV(VQFP48C)
P.4 Add Caution2 in Absolute Maximum Ratings condition. (Moved from Operational Notes)
P.23 Add the comment in Caution in Cautions of “Power- ON Condition.
(Moved from Operational Notes)
P.24 Add Display off operation in External clock mode
P.25 Move “5. Thermal Consideration” to “Absolute Maximum Ratings condition”
P.26 Move “13. Data transmission” to “Cautions of “Power ON Condition”.
P.27 Add VQFP48C to Ordering Information, Lineup and Marking Diagram
P.29 Add VQFP48C Physical Dimension and Packing Information
Remove BU9795BGUW (VBGA049W040A)
www.rohm.com
© 2016 ROHM Co., Ltd. All rights reserved.
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Notice
Precaution on using ROHM Products
1.
Our Products are designed and manufactured for application in ordinary electronic equipment (such as AV equipment,
OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you
intend to use our Products in devices requiring extremely high reliability (such as medical equipment (Note 1), transport
equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car
accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or
serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.
Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any
damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific
Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅣ
CLASSⅢ
2.
ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3.
Our Products are designed and manufactured for use under standard conditions and not under any special or
extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any
special or extraordinary environments or conditions. If you intend to use our Products under any special or
extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of
product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used.
However, recommend sufficiently about the residue.) ; or Washing our Products by using water or water-soluble
cleaning agents for cleaning residue after soldering
[h] Use of the Products in places subject to dew condensation
4.
The Products are not subject to radiation-proof design.
5.
Please verify and confirm characteristics of the final or mounted products in using the Products.
6.
In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7.
De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in
the range that does not exceed the maximum junction temperature.
8.
Confirm that operation temperature is within the specified range described in the product specification.
9.
ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1.
When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2.
In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PGA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.004
Precautions Regarding Application Examples and External Circuits
1.
If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2.
You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1.
Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl 2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2.
Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3.
Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4.
Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
trade act, please consult with ROHM in case of export.
Precaution Regarding Intellectual Property Rights
1.
All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data.
2.
ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the
Products with other articles such as components, circuits, systems or external equipment (including software).
3.
No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM
will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to
manufacture or sell products containing the Products, subject to the terms and conditions herein.
Other Precaution
1.
This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2.
The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3.
In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4.
The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice-PGA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.004
Datasheet
General Precaution
1. Before you use our Products, you are requested to carefully read this document and fully understand its contents.
ROHM shall not be in any way responsible or liable for failure, malfunction or accident arising from the use of any
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this document is current as of the issuing date and subject to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the latest information with a ROHM sales
representative.
3.
The information contained in this document is provided on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate and/or error-free. ROHM shall not be in any way responsible or
liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccuracy or errors of or
concerning such information.
Notice – WE
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.001
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